refactor: remove iseg prefix from segment constants
This commit is contained in:
Christopher Mosher
parent
e187549210
commit
b5446cca3f
236
cpu.cpp
236
cpu.cpp
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@ -52,118 +52,7 @@ static void pHexw(const unsigned short x) {
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/* power */
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static nodes* n;
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#define VCC sg->isegVCC
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#define VSS sg->isegVSS
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/* inputs */
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#define CLK0 sg->isegCLK0
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#define IRQ sg->isegIRQ
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#define RES sg->isegRES
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#define NMI sg->isegNMI
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#define RDY sg->isegRDY
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#define SO sg->isegSO
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/* data bus (I/O) */
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#define DB0 sg->isegDB0
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#define DB1 sg->isegDB1
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#define DB3 sg->isegDB3
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#define DB2 sg->isegDB2
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#define DB5 sg->isegDB5
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#define DB4 sg->isegDB4
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#define DB7 sg->isegDB7
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#define DB6 sg->isegDB6
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/* address bus (output) */
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#define AB0 sg->isegAB0
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#define AB1 sg->isegAB1
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#define AB2 sg->isegAB2
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#define AB3 sg->isegAB3
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#define AB4 sg->isegAB4
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#define AB5 sg->isegAB5
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#define AB6 sg->isegAB6
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#define AB7 sg->isegAB7
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#define AB8 sg->isegAB8
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#define AB9 sg->isegAB9
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#define AB12 sg->isegAB12
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#define AB13 sg->isegAB13
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#define AB10 sg->isegAB10
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#define AB11 sg->isegAB11
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#define AB14 sg->isegAB14
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#define AB15 sg->isegAB15
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/* outputs */
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#define RW sg->isegRW
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#define SYNC sg->isegSYNC
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#define CLK1OUT sg->isegCLK1OUT
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#define CLK2OUT sg->isegCLK2OUT
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/* internal registers */
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#define A0 sg->isegA0
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#define A1 sg->isegA1
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#define A2 sg->isegA2
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#define A3 sg->isegA3
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#define A4 sg->isegA4
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#define A5 sg->isegA5
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#define A6 sg->isegA6
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#define A7 sg->isegA7
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#define X0 sg->isegX0
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#define X1 sg->isegX1
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#define X2 sg->isegX2
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#define X3 sg->isegX3
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#define X4 sg->isegX4
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#define X5 sg->isegX5
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#define X6 sg->isegX6
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#define X7 sg->isegX7
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#define Y0 sg->isegY0
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#define Y1 sg->isegY1
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#define Y2 sg->isegY2
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#define Y3 sg->isegY3
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#define Y4 sg->isegY4
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#define Y5 sg->isegY5
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#define Y6 sg->isegY6
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#define Y7 sg->isegY7
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#define PCL0 sg->isegPCL0
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#define PCL1 sg->isegPCL1
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#define PCL2 sg->isegPCL2
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#define PCL3 sg->isegPCL3
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#define PCL4 sg->isegPCL4
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#define PCL5 sg->isegPCL5
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#define PCL6 sg->isegPCL6
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#define PCL7 sg->isegPCL7
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#define PCH0 sg->isegPCH0
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#define PCH1 sg->isegPCH1
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#define PCH2 sg->isegPCH2
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#define PCH3 sg->isegPCH3
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#define PCH4 sg->isegPCH4
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#define PCH5 sg->isegPCH5
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#define PCH6 sg->isegPCH6
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#define PCH7 sg->isegPCH7
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#define P0 sg->isegP0
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#define P1 sg->isegP1
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#define P2 sg->isegP2
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#define P3 sg->isegP3
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#define P4 sg->isegP4
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#define P6 sg->isegP6
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#define P7 sg->isegP7
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#define S0 sg->isegS0
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#define S1 sg->isegS1
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#define S2 sg->isegS2
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#define S3 sg->isegS3
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#define S4 sg->isegS4
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#define S5 sg->isegS5
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#define S6 sg->isegS6
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#define S7 sg->isegS7
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static nodes* sg;
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static std::map<int,std::string> map_i_seg;
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static std::map<int,std::string> map_i_seg;
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@ -218,24 +107,21 @@ addressBus(addressBus) {
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}
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}
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n = new nodes(map_seg_i);
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const int isegVSS = map_seg_i["-vss"];
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const int isegVCC = map_seg_i["-vcc"];
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for (int i = 0; i != trns.size(); ++i) {
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for (int i = 0; i != trns.size(); ++i) {
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trn& t = trns[i];
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trn& t = trns[i];
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if (t.c1 == isegVSS) {
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if (t.c1 == n->VSS) {
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t.c1 = t.c2;
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t.c1 = t.c2;
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t.c2 = isegVSS;
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t.c2 = n->VSS;
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} else if (t.c1 == isegVCC) {
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} else if (t.c1 == n->VCC) {
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t.c1 = t.c2;
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t.c1 = t.c2;
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t.c2 = isegVCC;
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t.c2 = n->VCC;
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}
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}
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segs[t.gate].gates.push_back(i);
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segs[t.gate].gates.push_back(i);
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segs[t.c1].c1c2s.push_back(i);
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segs[t.c1].c1c2s.push_back(i);
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segs[t.c2].c1c2s.push_back(i);
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segs[t.c2].c1c2s.push_back(i);
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}
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}
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sg = new nodes(map_seg_i);
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}
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}
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CPU::~CPU() {
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CPU::~CPU() {
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@ -259,7 +145,7 @@ void CPU::powerOn() {
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* temporary variable (see "step" method), we
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* temporary variable (see "step" method), we
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* need to initialize it here, to "phase one".
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* need to initialize it here, to "phase one".
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*/
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*/
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segs[CLK0].on = true;
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segs[n->CLK0].on = true;
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@ -274,18 +160,18 @@ void CPU::powerOn() {
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void CPU::initPins() {
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void CPU::initPins() {
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// set voltage supply and ground.
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// set voltage supply and ground.
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setSeg(VCC, true);
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setSeg(n->VCC, true);
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setSeg(VSS, false);
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setSeg(n->VSS, false);
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// don't do the set-overflow overriding functionality
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// don't do the set-overflow overriding functionality
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setSeg(SO, false);
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setSeg(n->SO, false);
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// ready to run (i.e., do not do single-stepping of instructions)
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// ready to run (i.e., do not do single-stepping of instructions)
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setSeg(RDY, true);
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setSeg(n->RDY, true);
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// pull up to indicate that we are not interrupting now
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// pull up to indicate that we are not interrupting now
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setSeg(IRQ, true);
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setSeg(n->IRQ, true);
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setSeg(NMI, true);
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setSeg(n->NMI, true);
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/*
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/*
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@ -299,12 +185,12 @@ void CPU::initPins() {
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* CPU does not start up normal operations yet. The caller can set RES_BAR high (by calling
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* CPU does not start up normal operations yet. The caller can set RES_BAR high (by calling
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* reset) whenever he is ready to start the CPU running.
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* reset) whenever he is ready to start the CPU running.
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*/
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*/
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setSeg(RES, false);
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setSeg(n->RES, false);
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}
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}
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void CPU::reset() {
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void CPU::reset() {
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setSeg(RES, true);
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setSeg(n->RES, true);
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recalc(RES);
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recalc(n->RES);
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}
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}
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void CPU::tick() {
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void CPU::tick() {
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@ -323,13 +209,13 @@ void CPU::step() {
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*
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*
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* The real 6502, of course, does not do this.
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* The real 6502, of course, does not do this.
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*/
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*/
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const bool nextPhase = !segs[CLK0].on;
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const bool nextPhase = !segs[n->CLK0].on;
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setSeg(CLK0, nextPhase);
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setSeg(n->CLK0, nextPhase);
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recalc(CLK0);
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recalc(n->CLK0);
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// database read/write happens during Clock Phase 2 (only)
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// database read/write happens during Clock Phase 2 (only)
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if (segs[CLK2OUT].on) {
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if (segs[n->CLK2OUT].on) {
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rw();
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rw();
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}
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}
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@ -355,13 +241,13 @@ void CPU::rw() {
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void CPU::readBus() {
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void CPU::readBus() {
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if (segs[RW].on) {
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if (segs[n->RW].on) {
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setDataSegs(mRead(rAddr()));
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setDataSegs(mRead(rAddr()));
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}
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}
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}
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}
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void CPU::writeBus() {
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void CPU::writeBus() {
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if (!segs[RW].on) {
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if (!segs[n->RW].on) {
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mWrite(rAddr(), rData());
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mWrite(rAddr(), rData());
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}
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}
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}
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}
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@ -369,32 +255,32 @@ void CPU::writeBus() {
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void CPU::setDataSegs(const unsigned char data) {
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void CPU::setDataSegs(const unsigned char data) {
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unsigned char x = data;
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unsigned char x = data;
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setSeg(DB0, x & 1);
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setSeg(n->DB0, x & 1);
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x >>= 1;
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x >>= 1;
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setSeg(DB1, x & 1);
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setSeg(n->DB1, x & 1);
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x >>= 1;
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x >>= 1;
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setSeg(DB2, x & 1);
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setSeg(n->DB2, x & 1);
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x >>= 1;
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x >>= 1;
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setSeg(DB3, x & 1);
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setSeg(n->DB3, x & 1);
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x >>= 1;
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x >>= 1;
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setSeg(DB4, x & 1);
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setSeg(n->DB4, x & 1);
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x >>= 1;
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x >>= 1;
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setSeg(DB5, x & 1);
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setSeg(n->DB5, x & 1);
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x >>= 1;
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x >>= 1;
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setSeg(DB6, x & 1);
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setSeg(n->DB6, x & 1);
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x >>= 1;
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x >>= 1;
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setSeg(DB7, x & 1);
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setSeg(n->DB7, x & 1);
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}
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}
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void CPU::addDataToRecalc(std::set<int>& s) {
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void CPU::addDataToRecalc(std::set<int>& s) {
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s.insert(DB0);
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s.insert(n->DB0);
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s.insert(DB1);
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s.insert(n->DB1);
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s.insert(DB2);
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s.insert(n->DB2);
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s.insert(DB3);
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s.insert(n->DB3);
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s.insert(DB4);
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s.insert(n->DB4);
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s.insert(DB5);
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s.insert(n->DB5);
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s.insert(DB6);
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s.insert(n->DB6);
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s.insert(DB7);
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s.insert(n->DB7);
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}
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}
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unsigned char CPU::mRead(unsigned short addr) {
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unsigned char CPU::mRead(unsigned short addr) {
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@ -438,31 +324,31 @@ void CPU::setSeg(const int iSeg, const bool up) {
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unsigned char CPU::rData() {
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unsigned char CPU::rData() {
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return readByte(DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0);
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return readByte(n->DB7, n->DB6, n->DB5, n->DB4, n->DB3, n->DB2, n->DB1, n->DB0);
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}
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}
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unsigned short CPU::rAddr() {
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unsigned short CPU::rAddr() {
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return readWord(AB15, AB14, AB13, AB12, AB11, AB10, AB9, AB8, AB7, AB6, AB5, AB4, AB3, AB2, AB1, AB0);
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return readWord(n->AB15, n->AB14, n->AB13, n->AB12, n->AB11, n->AB10, n->AB9, n->AB8, n->AB7, n->AB6, n->AB5, n->AB4, n->AB3, n->AB2, n->AB1, n->AB0);
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}
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}
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unsigned char CPU::rA() {
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unsigned char CPU::rA() {
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return readByte(A7, A6, A5, A4, A3, A2, A1, A0);
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return readByte(n->A7, n->A6, n->A5, n->A4, n->A3, n->A2, n->A1, n->A0);
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}
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}
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unsigned char CPU::rX() {
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unsigned char CPU::rX() {
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return readByte(X7, X6, X5, X4, X3, X2, X1, X0);
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return readByte(n->X7, n->X6, n->X5, n->X4, n->X3, n->X2, n->X1, n->X0);
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}
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}
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unsigned char CPU::rY() {
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unsigned char CPU::rY() {
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return readByte(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0);
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return readByte(n->Y7, n->Y6, n->Y5, n->Y4, n->Y3, n->Y2, n->Y1, n->Y0);
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}
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}
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unsigned char CPU::rS() {
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unsigned char CPU::rS() {
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return readByte(S7, S6, S5, S4, S3, S2, S1, S0);
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return readByte(n->S7, n->S6, n->S5, n->S4, n->S3, n->S2, n->S1, n->S0);
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}
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}
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unsigned short CPU::rPC() {
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unsigned short CPU::rPC() {
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return readWord(PCH7, PCH6, PCH5, PCH4, PCH3, PCH2, PCH1, PCH0, PCL7, PCL6, PCL5, PCL4, PCL3, PCL2, PCL1, PCL0);
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return readWord(n->PCH7, n->PCH6, n->PCH5, n->PCH4, n->PCH3, n->PCH2, n->PCH1, n->PCH0, n->PCL7, n->PCL6, n->PCL5, n->PCL4, n->PCL3, n->PCL2, n->PCL1, n->PCL0);
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}
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}
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@ -555,7 +441,7 @@ void CPU::recalc(const std::set<int>& riSeg) {
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* to riSegChanged.
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* to riSegChanged.
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*/
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*/
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void CPU::recalcNode(const int iSeg, std::set<int>& riSegChanged) {
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void CPU::recalcNode(const int iSeg, std::set<int>& riSegChanged) {
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if (!(iSeg == VCC || iSeg == VSS)) {
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if (!(iSeg == n->VCC || iSeg == n->VSS)) {
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std::set<int> riSegGroup;
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std::set<int> riSegGroup;
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addToGroup(iSeg, riSegGroup);
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addToGroup(iSeg, riSegGroup);
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const bool groupOn = getGroupValue(riSegGroup);
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const bool groupOn = getGroupValue(riSegGroup);
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@ -581,7 +467,7 @@ void CPU::setTrans(trn& t, const bool on, std::set<int>& riSeg) {
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}
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}
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void CPU::addRecalc(const int iSeg, std::set<int>& riSeg) {
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void CPU::addRecalc(const int iSeg, std::set<int>& riSeg) {
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if (!(iSeg == VCC || iSeg == VSS)) {
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if (!(iSeg == n->VCC || iSeg == n->VSS)) {
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riSeg.insert(iSeg);
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riSeg.insert(iSeg);
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}
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}
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}
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}
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@ -595,7 +481,7 @@ void CPU::addToGroup(int iSeg, std::set<int>& riSeg) {
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if (!ret.second) {
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if (!ret.second) {
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return;
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return;
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}
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}
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if (iSeg == VCC || iSeg == VSS) {
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if (iSeg == n->VCC || iSeg == n->VSS) {
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return;
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return;
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}
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}
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@ -628,11 +514,11 @@ void CPU::addToGroup(int iSeg, std::set<int>& riSeg) {
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*/
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*/
|
||||||
bool CPU::getGroupValue(const std::set<int>& riSeg) {
|
bool CPU::getGroupValue(const std::set<int>& riSeg) {
|
||||||
/* If group contains ground, it's OFF, */
|
/* If group contains ground, it's OFF, */
|
||||||
if (riSeg.find(VSS) != riSeg.end()) {
|
if (riSeg.find(n->VSS) != riSeg.end()) {
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
/* otherwise, if group contains voltage supply, it's ON. */
|
/* otherwise, if group contains voltage supply, it's ON. */
|
||||||
else if (riSeg.find(VCC) != riSeg.end()) {
|
else if (riSeg.find(n->VCC) != riSeg.end()) {
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -691,30 +577,30 @@ void CPU::dumpRegisters() {
|
||||||
std::cout << " Y";
|
std::cout << " Y";
|
||||||
pHex(rY());
|
pHex(rY());
|
||||||
std::cout << " ";
|
std::cout << " ";
|
||||||
std::cout << (segs[P7].on ? "N" : "n");
|
std::cout << (segs[n->P7].on ? "N" : "n");
|
||||||
std::cout << (segs[P6].on ? "V" : "v");
|
std::cout << (segs[n->P6].on ? "V" : "v");
|
||||||
std::cout << ".";
|
std::cout << ".";
|
||||||
std::cout << (segs[P4].on ? "B" : "b");
|
std::cout << (segs[n->P4].on ? "B" : "b");
|
||||||
std::cout << (segs[P3].on ? "D" : "d");
|
std::cout << (segs[n->P3].on ? "D" : "d");
|
||||||
std::cout << (segs[P2].on ? "I" : "i");
|
std::cout << (segs[n->P2].on ? "I" : "i");
|
||||||
std::cout << (segs[P1].on ? "Z" : "z");
|
std::cout << (segs[n->P1].on ? "Z" : "z");
|
||||||
std::cout << (segs[P0].on ? "C" : "c");
|
std::cout << (segs[n->P0].on ? "C" : "c");
|
||||||
std::cout << " S";
|
std::cout << " S";
|
||||||
pHex(rS());
|
pHex(rS());
|
||||||
std::cout << " PC";
|
std::cout << " PC";
|
||||||
pHexw(rPC());
|
pHexw(rPC());
|
||||||
if (segs[CLK1OUT].on) {
|
if (segs[n->CLK1OUT].on) {
|
||||||
std::cout << " PH1 ";
|
std::cout << " PH1 ";
|
||||||
}
|
}
|
||||||
if (segs[CLK2OUT].on) {
|
if (segs[n->CLK2OUT].on) {
|
||||||
std::cout << " PH2";
|
std::cout << " PH2";
|
||||||
if (segs[RW].on) {
|
if (segs[n->RW].on) {
|
||||||
std::cout << " R";
|
std::cout << " R";
|
||||||
} else {
|
} else {
|
||||||
std::cout << " W";
|
std::cout << " W";
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (!(segs[CLK1OUT].on || segs[CLK2OUT].on)) {
|
if (!(segs[n->CLK1OUT].on || segs[n->CLK2OUT].on)) {
|
||||||
std::cout << " PH- ";
|
std::cout << " PH- ";
|
||||||
}
|
}
|
||||||
std::cout << " DB";
|
std::cout << " DB";
|
||||||
|
|
|
||||||
182
nodes.cpp
182
nodes.cpp
|
|
@ -4,112 +4,112 @@
|
||||||
|
|
||||||
nodes::nodes(std::map<std::string,int>& map_seg_i) {
|
nodes::nodes(std::map<std::string,int>& map_seg_i) {
|
||||||
/* power */
|
/* power */
|
||||||
isegVCC = map_seg_i["+vcc"];
|
VCC = map_seg_i["+vcc"];
|
||||||
isegVSS = map_seg_i["-vss"];
|
VSS = map_seg_i["-vss"];
|
||||||
|
|
||||||
/* inputs */
|
/* inputs */
|
||||||
isegCLK0 = map_seg_i["-clk0"];
|
CLK0 = map_seg_i["-clk0"];
|
||||||
isegIRQ = map_seg_i["-irq"];
|
IRQ = map_seg_i["-irq"];
|
||||||
isegRES = map_seg_i["-res"];
|
RES = map_seg_i["-res"];
|
||||||
isegNMI = map_seg_i["-nmi"];
|
NMI = map_seg_i["-nmi"];
|
||||||
isegRDY = map_seg_i["+rdy"];
|
RDY = map_seg_i["+rdy"];
|
||||||
isegSO = map_seg_i["+s0"];
|
SO = map_seg_i["+s0"];
|
||||||
|
|
||||||
/* data bus (I/O) */
|
/* data bus (I/O) */
|
||||||
isegDB0 = map_seg_i["-db0"];
|
DB0 = map_seg_i["-db0"];
|
||||||
isegDB1 = map_seg_i["-db1"];
|
DB1 = map_seg_i["-db1"];
|
||||||
isegDB2 = map_seg_i["-db2"];
|
DB2 = map_seg_i["-db2"];
|
||||||
isegDB3 = map_seg_i["-db3"];
|
DB3 = map_seg_i["-db3"];
|
||||||
isegDB4 = map_seg_i["-db4"];
|
DB4 = map_seg_i["-db4"];
|
||||||
isegDB5 = map_seg_i["-db5"];
|
DB5 = map_seg_i["-db5"];
|
||||||
isegDB6 = map_seg_i["-db6"];
|
DB6 = map_seg_i["-db6"];
|
||||||
isegDB7 = map_seg_i["-db7"];
|
DB7 = map_seg_i["-db7"];
|
||||||
|
|
||||||
/* address bus (output) */
|
/* address bus (output) */
|
||||||
isegAB0 = map_seg_i["-ab0"];
|
AB0 = map_seg_i["-ab0"];
|
||||||
isegAB1 = map_seg_i["-ab1"];
|
AB1 = map_seg_i["-ab1"];
|
||||||
isegAB2 = map_seg_i["-ab2"];
|
AB2 = map_seg_i["-ab2"];
|
||||||
isegAB3 = map_seg_i["-ab3"];
|
AB3 = map_seg_i["-ab3"];
|
||||||
isegAB4 = map_seg_i["-ab4"];
|
AB4 = map_seg_i["-ab4"];
|
||||||
isegAB5 = map_seg_i["-ab5"];
|
AB5 = map_seg_i["-ab5"];
|
||||||
isegAB6 = map_seg_i["-ab6"];
|
AB6 = map_seg_i["-ab6"];
|
||||||
isegAB7 = map_seg_i["-ab7"];
|
AB7 = map_seg_i["-ab7"];
|
||||||
isegAB8 = map_seg_i["-ab8"];
|
AB8 = map_seg_i["-ab8"];
|
||||||
isegAB9 = map_seg_i["-ab9"];
|
AB9 = map_seg_i["-ab9"];
|
||||||
isegAB10 = map_seg_i["-ab10"];
|
AB10 = map_seg_i["-ab10"];
|
||||||
isegAB11 = map_seg_i["-ab11"];
|
AB11 = map_seg_i["-ab11"];
|
||||||
isegAB12 = map_seg_i["-ab12"];
|
AB12 = map_seg_i["-ab12"];
|
||||||
isegAB13 = map_seg_i["-ab13"];
|
AB13 = map_seg_i["-ab13"];
|
||||||
isegAB14 = map_seg_i["-ab14"];
|
AB14 = map_seg_i["-ab14"];
|
||||||
isegAB15 = map_seg_i["-ab15"];
|
AB15 = map_seg_i["-ab15"];
|
||||||
|
|
||||||
/* outputs */
|
/* outputs */
|
||||||
isegRW = map_seg_i["-rw"];
|
RW = map_seg_i["-rw"];
|
||||||
isegSYNC = map_seg_i["-sync"];
|
SYNC = map_seg_i["-sync"];
|
||||||
isegCLK1OUT = map_seg_i["-clk1out"];
|
CLK1OUT = map_seg_i["-clk1out"];
|
||||||
isegCLK2OUT = map_seg_i["-clk2out"];
|
CLK2OUT = map_seg_i["-clk2out"];
|
||||||
|
|
||||||
/* internal registers */
|
/* internal registers */
|
||||||
isegA0 = map_seg_i["-a0"];
|
A0 = map_seg_i["-a0"];
|
||||||
isegA1 = map_seg_i["-a1"];
|
A1 = map_seg_i["-a1"];
|
||||||
isegA2 = map_seg_i["-a2"];
|
A2 = map_seg_i["-a2"];
|
||||||
isegA3 = map_seg_i["-a3"];
|
A3 = map_seg_i["-a3"];
|
||||||
isegA4 = map_seg_i["-a4"];
|
A4 = map_seg_i["-a4"];
|
||||||
isegA5 = map_seg_i["-a5"];
|
A5 = map_seg_i["-a5"];
|
||||||
isegA6 = map_seg_i["-a6"];
|
A6 = map_seg_i["-a6"];
|
||||||
isegA7 = map_seg_i["-a7"];
|
A7 = map_seg_i["-a7"];
|
||||||
|
|
||||||
isegX0 = map_seg_i["-x0"];
|
X0 = map_seg_i["-x0"];
|
||||||
isegX1 = map_seg_i["-x1"];
|
X1 = map_seg_i["-x1"];
|
||||||
isegX2 = map_seg_i["-x2"];
|
X2 = map_seg_i["-x2"];
|
||||||
isegX3 = map_seg_i["-x3"];
|
X3 = map_seg_i["-x3"];
|
||||||
isegX4 = map_seg_i["-x4"];
|
X4 = map_seg_i["-x4"];
|
||||||
isegX5 = map_seg_i["-x5"];
|
X5 = map_seg_i["-x5"];
|
||||||
isegX6 = map_seg_i["-x6"];
|
X6 = map_seg_i["-x6"];
|
||||||
isegX7 = map_seg_i["-x7"];
|
X7 = map_seg_i["-x7"];
|
||||||
|
|
||||||
isegY0 = map_seg_i["-y0"];
|
Y0 = map_seg_i["-y0"];
|
||||||
isegY1 = map_seg_i["-y1"];
|
Y1 = map_seg_i["-y1"];
|
||||||
isegY2 = map_seg_i["-y2"];
|
Y2 = map_seg_i["-y2"];
|
||||||
isegY3 = map_seg_i["-y3"];
|
Y3 = map_seg_i["-y3"];
|
||||||
isegY4 = map_seg_i["-y4"];
|
Y4 = map_seg_i["-y4"];
|
||||||
isegY5 = map_seg_i["-y5"];
|
Y5 = map_seg_i["-y5"];
|
||||||
isegY6 = map_seg_i["-y6"];
|
Y6 = map_seg_i["-y6"];
|
||||||
isegY7 = map_seg_i["-y7"];
|
Y7 = map_seg_i["-y7"];
|
||||||
|
|
||||||
isegPCL0 = map_seg_i["-pcl0"];
|
PCL0 = map_seg_i["-pcl0"];
|
||||||
isegPCL1 = map_seg_i["-pcl1"];
|
PCL1 = map_seg_i["-pcl1"];
|
||||||
isegPCL2 = map_seg_i["-pcl2"];
|
PCL2 = map_seg_i["-pcl2"];
|
||||||
isegPCL3 = map_seg_i["-pcl3"];
|
PCL3 = map_seg_i["-pcl3"];
|
||||||
isegPCL4 = map_seg_i["-pcl4"];
|
PCL4 = map_seg_i["-pcl4"];
|
||||||
isegPCL5 = map_seg_i["-pcl5"];
|
PCL5 = map_seg_i["-pcl5"];
|
||||||
isegPCL6 = map_seg_i["-pcl6"];
|
PCL6 = map_seg_i["-pcl6"];
|
||||||
isegPCL7 = map_seg_i["-pcl7"];
|
PCL7 = map_seg_i["-pcl7"];
|
||||||
|
|
||||||
isegPCH0 = map_seg_i["-pch0"];
|
PCH0 = map_seg_i["-pch0"];
|
||||||
isegPCH1 = map_seg_i["-pch1"];
|
PCH1 = map_seg_i["-pch1"];
|
||||||
isegPCH2 = map_seg_i["-pch2"];
|
PCH2 = map_seg_i["-pch2"];
|
||||||
isegPCH3 = map_seg_i["-pch3"];
|
PCH3 = map_seg_i["-pch3"];
|
||||||
isegPCH4 = map_seg_i["-pch4"];
|
PCH4 = map_seg_i["-pch4"];
|
||||||
isegPCH5 = map_seg_i["-pch5"];
|
PCH5 = map_seg_i["-pch5"];
|
||||||
isegPCH6 = map_seg_i["-pch6"];
|
PCH6 = map_seg_i["-pch6"];
|
||||||
isegPCH7 = map_seg_i["-pch7"];
|
PCH7 = map_seg_i["-pch7"];
|
||||||
|
|
||||||
isegP0 = map_seg_i["+Pout0"];
|
P0 = map_seg_i["+Pout0"];
|
||||||
isegP1 = map_seg_i["+Pout1"];
|
P1 = map_seg_i["+Pout1"];
|
||||||
isegP2 = map_seg_i["+Pout2"];
|
P2 = map_seg_i["+Pout2"];
|
||||||
isegP3 = map_seg_i["+Pout3"];
|
P3 = map_seg_i["+Pout3"];
|
||||||
isegP4 = map_seg_i["+Pout4"];
|
P4 = map_seg_i["+Pout4"];
|
||||||
// P5 does not exist in the 6502 chip
|
// P5 does not exist in the 6502 chip
|
||||||
isegP6 = map_seg_i["+Pout6"];
|
P6 = map_seg_i["+Pout6"];
|
||||||
isegP7 = map_seg_i["+Pout7"];
|
P7 = map_seg_i["+Pout7"];
|
||||||
|
|
||||||
isegS0 = map_seg_i["-s0"];
|
S0 = map_seg_i["-s0"];
|
||||||
isegS1 = map_seg_i["-s1"];
|
S1 = map_seg_i["-s1"];
|
||||||
isegS2 = map_seg_i["-s2"];
|
S2 = map_seg_i["-s2"];
|
||||||
isegS3 = map_seg_i["-s3"];
|
S3 = map_seg_i["-s3"];
|
||||||
isegS4 = map_seg_i["-s4"];
|
S4 = map_seg_i["-s4"];
|
||||||
isegS5 = map_seg_i["-s5"];
|
S5 = map_seg_i["-s5"];
|
||||||
isegS6 = map_seg_i["-s6"];
|
S6 = map_seg_i["-s6"];
|
||||||
isegS7 = map_seg_i["-s7"];
|
S7 = map_seg_i["-s7"];
|
||||||
}
|
}
|
||||||
|
|
|
||||||
182
nodes.h
182
nodes.h
|
|
@ -7,113 +7,113 @@
|
||||||
class nodes {
|
class nodes {
|
||||||
public:
|
public:
|
||||||
/* power */
|
/* power */
|
||||||
int isegVCC;
|
int VCC;
|
||||||
int isegVSS;
|
int VSS;
|
||||||
|
|
||||||
/* inputs */
|
/* inputs */
|
||||||
int isegCLK0;
|
int CLK0;
|
||||||
int isegIRQ;
|
int IRQ;
|
||||||
int isegRES;
|
int RES;
|
||||||
int isegNMI;
|
int NMI;
|
||||||
int isegRDY;
|
int RDY;
|
||||||
int isegSO;
|
int SO;
|
||||||
|
|
||||||
/* data bus; */
|
/* data bus; */
|
||||||
int isegDB0;
|
int DB0;
|
||||||
int isegDB1;
|
int DB1;
|
||||||
int isegDB3;
|
int DB3;
|
||||||
int isegDB2;
|
int DB2;
|
||||||
int isegDB5;
|
int DB5;
|
||||||
int isegDB4;
|
int DB4;
|
||||||
int isegDB7;
|
int DB7;
|
||||||
int isegDB6;
|
int DB6;
|
||||||
|
|
||||||
/* address bus; */
|
/* address bus; */
|
||||||
int isegAB0;
|
int AB0;
|
||||||
int isegAB1;
|
int AB1;
|
||||||
int isegAB2;
|
int AB2;
|
||||||
int isegAB3;
|
int AB3;
|
||||||
int isegAB4;
|
int AB4;
|
||||||
int isegAB5;
|
int AB5;
|
||||||
int isegAB6;
|
int AB6;
|
||||||
int isegAB7;
|
int AB7;
|
||||||
int isegAB8;
|
int AB8;
|
||||||
int isegAB9;
|
int AB9;
|
||||||
int isegAB12;
|
int AB12;
|
||||||
int isegAB13;
|
int AB13;
|
||||||
int isegAB10;
|
int AB10;
|
||||||
int isegAB11;
|
int AB11;
|
||||||
int isegAB14;
|
int AB14;
|
||||||
int isegAB15;
|
int AB15;
|
||||||
|
|
||||||
/* outputs */
|
/* outputs */
|
||||||
int isegRW;
|
int RW;
|
||||||
int isegSYNC;
|
int SYNC;
|
||||||
int isegCLK1OUT;
|
int CLK1OUT;
|
||||||
int isegCLK2OUT;
|
int CLK2OUT;
|
||||||
|
|
||||||
/* internal registers */
|
/* internal registers */
|
||||||
int isegA0;
|
int A0;
|
||||||
int isegA1;
|
int A1;
|
||||||
int isegA2;
|
int A2;
|
||||||
int isegA3;
|
int A3;
|
||||||
int isegA4;
|
int A4;
|
||||||
int isegA5;
|
int A5;
|
||||||
int isegA6;
|
int A6;
|
||||||
int isegA7;
|
int A7;
|
||||||
|
|
||||||
int isegX0;
|
int X0;
|
||||||
int isegX1;
|
int X1;
|
||||||
int isegX2;
|
int X2;
|
||||||
int isegX3;
|
int X3;
|
||||||
int isegX4;
|
int X4;
|
||||||
int isegX5;
|
int X5;
|
||||||
int isegX6;
|
int X6;
|
||||||
int isegX7;
|
int X7;
|
||||||
|
|
||||||
int isegY0;
|
int Y0;
|
||||||
int isegY1;
|
int Y1;
|
||||||
int isegY2;
|
int Y2;
|
||||||
int isegY3;
|
int Y3;
|
||||||
int isegY4;
|
int Y4;
|
||||||
int isegY5;
|
int Y5;
|
||||||
int isegY6;
|
int Y6;
|
||||||
int isegY7;
|
int Y7;
|
||||||
|
|
||||||
int isegPCL0;
|
int PCL0;
|
||||||
int isegPCL1;
|
int PCL1;
|
||||||
int isegPCL2;
|
int PCL2;
|
||||||
int isegPCL3;
|
int PCL3;
|
||||||
int isegPCL4;
|
int PCL4;
|
||||||
int isegPCL5;
|
int PCL5;
|
||||||
int isegPCL6;
|
int PCL6;
|
||||||
int isegPCL7;
|
int PCL7;
|
||||||
|
|
||||||
int isegPCH0;
|
int PCH0;
|
||||||
int isegPCH1;
|
int PCH1;
|
||||||
int isegPCH2;
|
int PCH2;
|
||||||
int isegPCH3;
|
int PCH3;
|
||||||
int isegPCH4;
|
int PCH4;
|
||||||
int isegPCH5;
|
int PCH5;
|
||||||
int isegPCH6;
|
int PCH6;
|
||||||
int isegPCH7;
|
int PCH7;
|
||||||
|
|
||||||
int isegP0;
|
int P0;
|
||||||
int isegP1;
|
int P1;
|
||||||
int isegP2;
|
int P2;
|
||||||
int isegP3;
|
int P3;
|
||||||
int isegP4;
|
int P4;
|
||||||
int isegP6;
|
int P6;
|
||||||
int isegP7;
|
int P7;
|
||||||
|
|
||||||
int isegS0;
|
int S0;
|
||||||
int isegS1;
|
int S1;
|
||||||
int isegS2;
|
int S2;
|
||||||
int isegS3;
|
int S3;
|
||||||
int isegS4;
|
int S4;
|
||||||
int isegS5;
|
int S5;
|
||||||
int isegS6;
|
int S6;
|
||||||
int isegS7;
|
int S7;
|
||||||
|
|
||||||
nodes(std::map<std::string,int>& map_seg_i);
|
nodes(std::map<std::string,int>& map_seg_i);
|
||||||
};
|
};
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue