refactor: rearrange methods
This commit is contained in:
Christopher Mosher
parent
0e589f56d2
commit
fbb8227f17
759
cpu.cpp
759
cpu.cpp
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@ -14,6 +14,12 @@
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#include "nodes.h"
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#include "addressbus.h"
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#define TRACEREG 1
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//#define TRACESEG 1
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//#define TRACEMEM 1
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@ -30,6 +36,12 @@
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#define dumpSegs()
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#endif
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CPU::CPU(AddressBus& addressBus) :
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addressBus(addressBus) {
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std::cout << "reading segsonly";
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@ -107,368 +119,11 @@ addressBus(addressBus) {
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CPU::~CPU() {
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}
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void CPU::tick() {
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step();
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step();
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}
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unsigned char CPU::readByte(unsigned int b7, unsigned int b6, unsigned int b5, unsigned int b4, unsigned int b3, unsigned int b2, unsigned int b1, unsigned int b0) {
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return
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segs[b7].on << 7 |
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segs[b6].on << 6 |
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segs[b5].on << 5 |
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segs[b4].on << 4 |
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segs[b3].on << 3 |
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segs[b2].on << 2 |
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segs[b1].on << 1 |
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segs[b0].on;
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}
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unsigned short CPU::readWord(unsigned int b15, unsigned int b14, unsigned int b13, unsigned int b12, unsigned int b11, unsigned int b10, unsigned int b9, unsigned int b8, unsigned int b7, unsigned int b6, unsigned int b5, unsigned int b4, unsigned int b3, unsigned int b2, unsigned int b1, unsigned int b0) {
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return
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segs[b15].on << 15 |
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segs[b14].on << 14 |
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segs[b13].on << 13 |
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segs[b12].on << 12 |
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segs[b11].on << 11 |
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segs[b10].on << 10 |
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segs[b9].on << 9 |
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segs[b8].on << 8 |
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segs[b7].on << 7 |
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segs[b6].on << 6 |
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segs[b5].on << 5 |
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segs[b4].on << 4 |
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segs[b3].on << 3 |
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segs[b2].on << 2 |
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segs[b1].on << 1 |
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segs[b0].on;
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}
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bool CPU::isSegOn(int iSeg) {
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return segs[iSeg].on;
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}
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unsigned char CPU::rData() {
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return readByte(DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0);
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}
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unsigned short CPU::rAddr() {
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return readWord(AB15, AB14, AB13, AB12, AB11, AB10, AB9, AB8, AB7, AB6, AB5, AB4, AB3, AB2, AB1, AB0);
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}
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unsigned char CPU::rA() {
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return readByte(A7, A6, A5, A4, A3, A2, A1, A0);
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}
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unsigned char CPU::rX() {
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return readByte(X7, X6, X5, X4, X3, X2, X1, X0);
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}
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unsigned char CPU::rY() {
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return readByte(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0);
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}
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unsigned char CPU::rS() {
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return readByte(S7, S6, S5, S4, S3, S2, S1, S0);
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}
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unsigned short CPU::rPC() {
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return readWord(PCH7, PCH6, PCH5, PCH4, PCH3, PCH2, PCH1, PCH0, PCL7, PCL6, PCL5, PCL4, PCL3, PCL2, PCL1, PCL0);
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}
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static void pHex(unsigned char x) {
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std::cout << std::setw(2) << std::setfill('0') << std::hex << (unsigned long) x << std::dec;
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}
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static void pHexw(unsigned short x) {
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std::cout << std::setw(4) << std::setfill('0') << std::hex << (unsigned long) x << std::dec;
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}
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void CPU::dumpSegments() {
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for (int i = 0; i < segs.size(); ++i) {
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// std::cout << i << " ";
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seg& s = segs[i];
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if (s.pullup) {
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std::cout << "U";
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} else if (s.pulldown) {
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std::cout << "D";
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} else {
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std::cout << "f";
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}
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if (s.on) {
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std::cout << "+";
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} else {
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std::cout << "-";
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}
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// std::cout << std::endl;
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}
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std::cout << std::endl;
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}
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unsigned char CPU::mRead(unsigned short addr) {
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unsigned char x;
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x = this->addressBus.read(addr);
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#ifdef TRACEMEM
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std::cout << "-------------------------------------------------- ";
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pHex(x);
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std::cout << "<";
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pHexw(addr);
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std::cout << std::endl;
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#endif
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return x;
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}
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void CPU::mWrite(unsigned short addr, unsigned char data) {
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this->addressBus.write(addr, data);
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#ifdef TRACEMEM
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std::cout << "-------------------------------------------------- ";
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pHex(data);
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std::cout << ">";
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pHexw(addr);
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std::cout << std::endl;
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#endif
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}
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void CPU::dumpRegisters() {
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std::cout << "A";
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pHex(rA());
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std::cout << " X";
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pHex(rX());
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std::cout << " Y";
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pHex(rY());
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std::cout << " ";
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std::cout << (isSegOn(P7) ? "N" : "n");
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std::cout << (isSegOn(P6) ? "V" : "v");
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std::cout << ".";
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std::cout << (isSegOn(P4) ? "B" : "b");
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std::cout << (isSegOn(P3) ? "D" : "d");
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std::cout << (isSegOn(P2) ? "I" : "i");
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std::cout << (isSegOn(P1) ? "Z" : "z");
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std::cout << (isSegOn(P0) ? "C" : "c");
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std::cout << " S";
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pHex(rS());
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std::cout << " PC";
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pHexw(rPC());
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if (isSegOn(CLK1OUT)) {
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std::cout << " PH1 ";
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}
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if (isSegOn(CLK2OUT)) {
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std::cout << " PH2";
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if (isSegOn(RW)) {
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std::cout << " R";
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} else {
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std::cout << " W";
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}
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}
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if (!(isSegOn(CLK1OUT) || isSegOn(CLK2OUT))) {
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std::cout << " PH- ";
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}
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std::cout << " DB";
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pHex(rData());
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std::cout << " AB";
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pHexw(rAddr());
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std::cout << std::endl;
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//pZP();
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}
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static void addRecalc(const int iSeg, std::set<int>& riSeg) {
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if (!(iSeg == VCC || iSeg == VSS)) {
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riSeg.insert(iSeg);
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}
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}
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static void setTrans(trn& t, const bool on, std::set<int>& riSeg) {
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if (t.on != on) {
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t.on = on;
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addRecalc(t.c1, riSeg);
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addRecalc(t.c2, riSeg);
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}
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}
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bool CPU::getGroupValue(const std::set<int>& riSeg) {
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/* If group contain ground, it's OFF. */
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if (riSeg.find(VSS) != riSeg.end()) {
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return false;
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}
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/* If group contain voltage supply, it's ON. */
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if (riSeg.find(VCC) != riSeg.end()) {
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return true;
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}
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for (std::set<int>::const_iterator iSeg = riSeg.begin(); iSeg != riSeg.end(); ++iSeg) {
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const seg& s = segs[*iSeg];
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if (s.pullup) {
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return true;
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}
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if (s.pulldown) {
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return false;
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}
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if (s.on) {
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return true;
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}
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}
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return false;
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}
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/*
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* Adds segment iSeg, and all segments electrically connected to it, to riSeg.
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* This happens recursively, but we don't recurse past ground or voltage supply.
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*/
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void CPU::addToGroup(int iSeg, std::set<int>& riSeg) {
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const std::pair<std::set<int>::iterator, bool> ret = riSeg.insert(iSeg);
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if (!ret.second) {
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return;
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}
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if (iSeg == VCC || iSeg == VSS) {
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return;
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}
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/*
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* For every ON transistor this seg is connected to via a leg (source or
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* drain), add the seg that's connected to the OTHER leg of the transistor.
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* This is a RECURSIVE addition.
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*/
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const seg& s = segs[iSeg];
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for (std::vector<int>::const_iterator iTrn = s.c1c2s.begin(); iTrn != s.c1c2s.end(); ++iTrn) {
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const trn& t = trns[*iTrn];
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if (t.on) {
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if (t.c1 == iSeg) {
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addToGroup(t.c2, riSeg);
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} else if (t.c2 == iSeg) {
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addToGroup(t.c1, riSeg);
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}
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}
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}
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}
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void CPU::recalcNode(const int iSeg, std::set<int>& riSegChanged) {
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if (!(iSeg == VCC || iSeg == VSS)) {
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std::set<int> riSegGroup;
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addToGroup(iSeg, riSegGroup);
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const bool groupOn = getGroupValue(riSegGroup);
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for (std::set<int>::iterator iSegGroup = riSegGroup.begin(); iSegGroup != riSegGroup.end(); ++iSegGroup) {
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seg& s = segs[*iSegGroup];
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if (s.on != groupOn) {
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s.on = groupOn;
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for (std::vector<int>::iterator iTrnGate = s.gates.begin(); iTrnGate != s.gates.end(); ++iTrnGate) {
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setTrans(trns[*iTrnGate], s.on, riSegChanged);
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}
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}
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}
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}
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}
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void CPU::recalc(const std::set<int>& riSeg) {
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std::set<int> riSegRecalc(riSeg);
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// std::set<int> done;
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for (int sane = 0; sane < 100; ++sane) {
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if (!riSegRecalc.size()) {
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return;
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}
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std::set<int> riSegChanged;
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for (std::set<int>::const_iterator iSegRecalc = riSegRecalc.begin(); iSegRecalc != riSegRecalc.end(); ++iSegRecalc) {
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recalcNode(*iSegRecalc, riSegChanged);
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}
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// done.insert(rcl.begin(),rcl.end());
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// std::set<int> v;
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// std::set_difference(rcl.begin(),rcl.end(),done.begin(),done.end(),std::inserter(v,v.end()));
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// list = v;
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// if (std::equal(list.begin(),list.end(),rcl.begin())) {
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//std::cout << "hit stasis" << std::endl;
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// return;
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// }
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riSegRecalc = riSegChanged;
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}
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std::cerr << "ERROR: reached maximum iteration limit while recalculating CPU state" << std::endl;
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}
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void CPU::recalc(const int iSeg) {
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std::set<int> riSeg;
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addRecalc(iSeg,riSeg);
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recalc(riSeg);
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}
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void CPU::recalcAll() {
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std::set<int> riSeg;
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for (int iSeg = 0; iSeg < segs.size(); ++iSeg) {
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addRecalc(iSeg,riSeg);
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}
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recalc(riSeg);
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}
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void CPU::setSeg(const int iSeg, const bool up) {
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seg& s = segs[iSeg];
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s.pullup = up;
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s.pulldown = !up;
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}
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void CPU::setDataSegs(const unsigned char data) {
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unsigned char x = data;
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setSeg(DB0, x & 1);
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x >>= 1;
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setSeg(DB1, x & 1);
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x >>= 1;
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setSeg(DB2, x & 1);
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x >>= 1;
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setSeg(DB3, x & 1);
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x >>= 1;
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setSeg(DB4, x & 1);
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x >>= 1;
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setSeg(DB5, x & 1);
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x >>= 1;
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setSeg(DB6, x & 1);
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x >>= 1;
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setSeg(DB7, x & 1);
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}
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void CPU::readBus() {
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if (isSegOn(RW)) {
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setDataSegs(mRead(rAddr()));
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}
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}
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void CPU::writeBus() {
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if (!isSegOn(RW)) {
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mWrite(rAddr(), rData());
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}
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}
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static void addDataToRecalc(std::set<int>& s) {
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s.insert(DB0);
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s.insert(DB1);
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s.insert(DB2);
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s.insert(DB3);
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s.insert(DB4);
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s.insert(DB5);
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s.insert(DB6);
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s.insert(DB7);
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}
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void CPU::rw() {
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readBus();
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std::set<int> s;
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addDataToRecalc(s);
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recalc(s);
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writeBus();
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}
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void CPU::step() {
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const bool h = isSegOn(CLK0);
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setSeg(CLK0, !h);
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recalc(CLK0);
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if (!h) {
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rw();
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}
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dumpRegs();
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dumpSegs();
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}
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void CPU::powerOn() {
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std::cout << "initial state" << std::endl;
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@ -505,3 +160,393 @@ void CPU::reset() {
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setSeg(RES, true);
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recalc(RES);
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}
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void CPU::tick() {
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step();
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step();
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}
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void CPU::step() {
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const bool h = segs[CLK0].on;
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setSeg(CLK0, !h);
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recalc(CLK0);
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if (!h) {
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rw();
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}
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dumpRegs();
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dumpSegs();
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}
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void CPU::rw() {
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readBus();
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std::set<int> s;
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addDataToRecalc(s);
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recalc(s);
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writeBus();
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}
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void CPU::readBus() {
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if (segs[RW].on) {
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setDataSegs(mRead(rAddr()));
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}
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}
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void CPU::writeBus() {
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if (!segs[RW].on) {
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mWrite(rAddr(), rData());
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}
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}
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void CPU::setDataSegs(const unsigned char data) {
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unsigned char x = data;
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setSeg(DB0, x & 1);
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x >>= 1;
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setSeg(DB1, x & 1);
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x >>= 1;
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setSeg(DB2, x & 1);
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x >>= 1;
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setSeg(DB3, x & 1);
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x >>= 1;
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setSeg(DB4, x & 1);
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x >>= 1;
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setSeg(DB5, x & 1);
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x >>= 1;
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setSeg(DB6, x & 1);
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x >>= 1;
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setSeg(DB7, x & 1);
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}
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void CPU::addDataToRecalc(std::set<int>& s) {
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s.insert(DB0);
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s.insert(DB1);
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s.insert(DB2);
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s.insert(DB3);
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s.insert(DB4);
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s.insert(DB5);
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s.insert(DB6);
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s.insert(DB7);
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}
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unsigned char CPU::mRead(unsigned short addr) {
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unsigned char x;
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x = this->addressBus.read(addr);
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#ifdef TRACEMEM
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std::cout << "-------------------------------------------------- ";
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pHex(x);
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std::cout << "<";
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pHexw(addr);
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std::cout << std::endl;
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#endif
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return x;
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}
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void CPU::mWrite(unsigned short addr, unsigned char data) {
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this->addressBus.write(addr, data);
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#ifdef TRACEMEM
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std::cout << "-------------------------------------------------- ";
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pHex(data);
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std::cout << ">";
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pHexw(addr);
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std::cout << std::endl;
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#endif
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}
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void CPU::setSeg(const int iSeg, const bool up) {
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seg& s = segs[iSeg];
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|
||||
s.pullup = up;
|
||||
s.pulldown = !up;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
unsigned char CPU::rData() {
|
||||
return readByte(DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0);
|
||||
}
|
||||
|
||||
unsigned short CPU::rAddr() {
|
||||
return readWord(AB15, AB14, AB13, AB12, AB11, AB10, AB9, AB8, AB7, AB6, AB5, AB4, AB3, AB2, AB1, AB0);
|
||||
}
|
||||
|
||||
unsigned char CPU::rA() {
|
||||
return readByte(A7, A6, A5, A4, A3, A2, A1, A0);
|
||||
}
|
||||
|
||||
unsigned char CPU::rX() {
|
||||
return readByte(X7, X6, X5, X4, X3, X2, X1, X0);
|
||||
}
|
||||
|
||||
unsigned char CPU::rY() {
|
||||
return readByte(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0);
|
||||
}
|
||||
|
||||
unsigned char CPU::rS() {
|
||||
return readByte(S7, S6, S5, S4, S3, S2, S1, S0);
|
||||
}
|
||||
|
||||
unsigned short CPU::rPC() {
|
||||
return readWord(PCH7, PCH6, PCH5, PCH4, PCH3, PCH2, PCH1, PCH0, PCL7, PCL6, PCL5, PCL4, PCL3, PCL2, PCL1, PCL0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
unsigned char CPU::readByte(unsigned int b7, unsigned int b6, unsigned int b5, unsigned int b4, unsigned int b3, unsigned int b2, unsigned int b1, unsigned int b0) {
|
||||
return
|
||||
segs[b7].on << 7 |
|
||||
segs[b6].on << 6 |
|
||||
segs[b5].on << 5 |
|
||||
segs[b4].on << 4 |
|
||||
segs[b3].on << 3 |
|
||||
segs[b2].on << 2 |
|
||||
segs[b1].on << 1 |
|
||||
segs[b0].on;
|
||||
}
|
||||
|
||||
unsigned short CPU::readWord(unsigned int b15, unsigned int b14, unsigned int b13, unsigned int b12, unsigned int b11, unsigned int b10, unsigned int b9, unsigned int b8, unsigned int b7, unsigned int b6, unsigned int b5, unsigned int b4, unsigned int b3, unsigned int b2, unsigned int b1, unsigned int b0) {
|
||||
return
|
||||
segs[b15].on << 15 |
|
||||
segs[b14].on << 14 |
|
||||
segs[b13].on << 13 |
|
||||
segs[b12].on << 12 |
|
||||
segs[b11].on << 11 |
|
||||
segs[b10].on << 10 |
|
||||
segs[b9].on << 9 |
|
||||
segs[b8].on << 8 |
|
||||
segs[b7].on << 7 |
|
||||
segs[b6].on << 6 |
|
||||
segs[b5].on << 5 |
|
||||
segs[b4].on << 4 |
|
||||
segs[b3].on << 3 |
|
||||
segs[b2].on << 2 |
|
||||
segs[b1].on << 1 |
|
||||
segs[b0].on;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void CPU::recalcAll() {
|
||||
std::set<int> riSeg;
|
||||
for (int iSeg = 0; iSeg < segs.size(); ++iSeg) {
|
||||
addRecalc(iSeg,riSeg);
|
||||
}
|
||||
recalc(riSeg);
|
||||
}
|
||||
|
||||
void CPU::recalc(const int iSeg) {
|
||||
std::set<int> riSeg;
|
||||
addRecalc(iSeg,riSeg);
|
||||
recalc(riSeg);
|
||||
}
|
||||
|
||||
void CPU::recalc(const std::set<int>& riSeg) {
|
||||
std::set<int> riSegRecalc(riSeg);
|
||||
for (int sane = 0; sane < 100; ++sane) {
|
||||
if (!riSegRecalc.size()) {
|
||||
return;
|
||||
}
|
||||
|
||||
std::set<int> riSegChanged;
|
||||
for (std::set<int>::const_iterator iSegRecalc = riSegRecalc.begin(); iSegRecalc != riSegRecalc.end(); ++iSegRecalc) {
|
||||
recalcNode(*iSegRecalc, riSegChanged);
|
||||
}
|
||||
riSegRecalc = riSegChanged;
|
||||
}
|
||||
std::cerr << "ERROR: reached maximum iteration limit while recalculating CPU state" << std::endl;
|
||||
}
|
||||
|
||||
void CPU::recalcNode(const int iSeg, std::set<int>& riSegChanged) {
|
||||
if (!(iSeg == VCC || iSeg == VSS)) {
|
||||
std::set<int> riSegGroup;
|
||||
addToGroup(iSeg, riSegGroup);
|
||||
const bool groupOn = getGroupValue(riSegGroup);
|
||||
|
||||
for (std::set<int>::iterator iSegGroup = riSegGroup.begin(); iSegGroup != riSegGroup.end(); ++iSegGroup) {
|
||||
seg& s = segs[*iSegGroup];
|
||||
if (s.on != groupOn) {
|
||||
s.on = groupOn;
|
||||
for (std::vector<int>::iterator iTrnGate = s.gates.begin(); iTrnGate != s.gates.end(); ++iTrnGate) {
|
||||
setTrans(trns[*iTrnGate], s.on, riSegChanged);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void CPU::setTrans(trn& t, const bool on, std::set<int>& riSeg) {
|
||||
if (t.on != on) {
|
||||
t.on = on;
|
||||
addRecalc(t.c1, riSeg);
|
||||
addRecalc(t.c2, riSeg);
|
||||
}
|
||||
}
|
||||
|
||||
void CPU::addRecalc(const int iSeg, std::set<int>& riSeg) {
|
||||
if (!(iSeg == VCC || iSeg == VSS)) {
|
||||
riSeg.insert(iSeg);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Adds segment iSeg, and all segments electrically connected to it, to riSeg.
|
||||
* This happens recursively, but we don't recurse past ground or voltage supply.
|
||||
*/
|
||||
void CPU::addToGroup(int iSeg, std::set<int>& riSeg) {
|
||||
const std::pair<std::set<int>::iterator, bool> ret = riSeg.insert(iSeg);
|
||||
if (!ret.second) {
|
||||
return;
|
||||
}
|
||||
if (iSeg == VCC || iSeg == VSS) {
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* For every ON transistor this seg is connected to via a leg (source or
|
||||
* drain), add the seg that's connected to the OTHER leg of the transistor.
|
||||
* This is a RECURSIVE addition.
|
||||
*/
|
||||
const seg& s = segs[iSeg];
|
||||
for (std::vector<int>::const_iterator iTrn = s.c1c2s.begin(); iTrn != s.c1c2s.end(); ++iTrn) {
|
||||
const trn& t = trns[*iTrn];
|
||||
if (t.on) {
|
||||
if (t.c1 == iSeg) {
|
||||
addToGroup(t.c2, riSeg);
|
||||
} else if (t.c2 == iSeg) {
|
||||
addToGroup(t.c1, riSeg);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool CPU::getGroupValue(const std::set<int>& riSeg) {
|
||||
/* If group contain ground, it's OFF. */
|
||||
if (riSeg.find(VSS) != riSeg.end()) {
|
||||
return false;
|
||||
}
|
||||
/* If group contain voltage supply, it's ON. */
|
||||
if (riSeg.find(VCC) != riSeg.end()) {
|
||||
return true;
|
||||
}
|
||||
|
||||
for (std::set<int>::const_iterator iSeg = riSeg.begin(); iSeg != riSeg.end(); ++iSeg) {
|
||||
const seg& s = segs[*iSeg];
|
||||
if (s.pullup) {
|
||||
return true;
|
||||
}
|
||||
if (s.pulldown) {
|
||||
return false;
|
||||
}
|
||||
if (s.on) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
static void pHex(unsigned char x) {
|
||||
std::cout << std::setw(2) << std::setfill('0') << std::hex << (unsigned long) x << std::dec;
|
||||
}
|
||||
|
||||
static void pHexw(unsigned short x) {
|
||||
std::cout << std::setw(4) << std::setfill('0') << std::hex << (unsigned long) x << std::dec;
|
||||
}
|
||||
|
||||
void CPU::dumpSegments() {
|
||||
for (int i = 0; i < segs.size(); ++i) {
|
||||
seg& s = segs[i];
|
||||
if (s.pullup) {
|
||||
std::cout << "U";
|
||||
} else if (s.pulldown) {
|
||||
std::cout << "D";
|
||||
} else {
|
||||
std::cout << "f";
|
||||
}
|
||||
if (s.on) {
|
||||
std::cout << "+";
|
||||
} else {
|
||||
std::cout << "-";
|
||||
}
|
||||
}
|
||||
std::cout << std::endl;
|
||||
}
|
||||
|
||||
void CPU::dumpRegisters() {
|
||||
std::cout << "A";
|
||||
pHex(rA());
|
||||
std::cout << " X";
|
||||
pHex(rX());
|
||||
std::cout << " Y";
|
||||
pHex(rY());
|
||||
std::cout << " ";
|
||||
std::cout << (segs[P7].on ? "N" : "n");
|
||||
std::cout << (segs[P6].on ? "V" : "v");
|
||||
std::cout << ".";
|
||||
std::cout << (segs[P4].on ? "B" : "b");
|
||||
std::cout << (segs[P3].on ? "D" : "d");
|
||||
std::cout << (segs[P2].on ? "I" : "i");
|
||||
std::cout << (segs[P1].on ? "Z" : "z");
|
||||
std::cout << (segs[P0].on ? "C" : "c");
|
||||
std::cout << " S";
|
||||
pHex(rS());
|
||||
std::cout << " PC";
|
||||
pHexw(rPC());
|
||||
if (segs[CLK1OUT].on) {
|
||||
std::cout << " PH1 ";
|
||||
}
|
||||
if (segs[CLK2OUT].on) {
|
||||
std::cout << " PH2";
|
||||
if (segs[RW].on) {
|
||||
std::cout << " R";
|
||||
} else {
|
||||
std::cout << " W";
|
||||
}
|
||||
}
|
||||
if (!(segs[CLK1OUT].on || segs[CLK2OUT].on)) {
|
||||
std::cout << " PH- ";
|
||||
}
|
||||
std::cout << " DB";
|
||||
pHex(rData());
|
||||
std::cout << " AB";
|
||||
pHexw(rAddr());
|
||||
std::cout << std::endl;
|
||||
//pZP();
|
||||
}
|
||||
|
|
|
|||
4
cpu.h
4
cpu.h
|
|
@ -29,9 +29,11 @@ private:
|
|||
std::vector<trn> trns;
|
||||
AddressBus& addressBus;
|
||||
|
||||
void addDataToRecalc(std::set<int>& s);
|
||||
void addRecalc(const int iSeg, std::set<int>& riSeg);
|
||||
void setTrans(trn& t, const bool on, std::set<int>& riSeg);
|
||||
unsigned char readByte(unsigned int b7, unsigned int b6, unsigned int b5, unsigned int b4, unsigned int b3, unsigned int b2, unsigned int b1, unsigned int b0);
|
||||
unsigned short readWord(unsigned int b15, unsigned int b14, unsigned int b13, unsigned int b12, unsigned int b11, unsigned int b10, unsigned int b9, unsigned int b8, unsigned int b7, unsigned int b6, unsigned int b5, unsigned int b4, unsigned int b3, unsigned int b2, unsigned int b1, unsigned int b0);
|
||||
bool isSegOn(int iseg);
|
||||
unsigned char rData();
|
||||
unsigned short rAddr();
|
||||
unsigned char rA();
|
||||
|
|
|
|||
Loading…
Reference in New Issue