2010-09-18 16:56:48 +00:00
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/*
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2010-10-30 20:23:56 +00:00
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Copyright (c) 2010 Brian Silverman, Barry Silverman, Ed Spittles, Segher Boessenkool
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2010-09-18 16:56:48 +00:00
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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var nodenames ={
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2010-09-23 18:53:43 +00:00
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res: 159, // pads: reset
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rw: 1156, // pads: read not write
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db0: 1005, // pads: databus
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2010-09-18 16:56:48 +00:00
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db1: 82,
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db3: 650,
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db2: 945,
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db5: 175,
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db4: 1393,
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db7: 1349,
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db6: 1591,
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2010-09-23 18:53:43 +00:00
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ab0: 268, // pads: address bus
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2010-09-18 16:56:48 +00:00
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ab1: 451,
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ab2: 1340,
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ab3: 211,
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ab4: 435,
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ab5: 736,
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ab6: 887,
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ab7: 1493,
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ab8: 230,
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ab9: 148,
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2010-09-23 18:53:43 +00:00
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ab12: 1237,
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ab13: 349,
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ab10: 1443,
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ab11: 399,
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ab14: 672,
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ab15: 195,
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sync: 539, // pads
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so: 1672, // pads: set overflow
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clk0: 1171, // pads
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clk1out: 1163, // pads
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clk2out: 421, // pads
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rdy: 89, // pads: ready
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nmi: 1297, // pads: non maskable interrupt
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irq: 103, // pads
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vcc: 657, // pads
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vss: 558, // pads
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a0: 737, // machine state: accumulator
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a1: 1234,
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a2: 978,
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a3: 162,
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a4: 727,
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a5: 858,
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a6: 1136,
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a7: 1653,
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y0: 64, // machine state: y index register
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y1: 1148,
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y2: 573,
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y3: 305,
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y4: 989,
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y5: 615,
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y6: 115,
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y7: 843,
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x0: 1216, // machine state: x index register
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x1: 98,
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x2: 1,
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x3: 1648,
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x4: 85,
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x5: 589,
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x6: 448,
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x7: 777,
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2011-02-15 20:04:08 +00:00
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pcl0: 1139, // machine state: program counter low (first storage node output)
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2010-09-23 18:53:43 +00:00
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pcl1: 1022,
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pcl2: 655,
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pcl3: 1359,
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pcl4: 900,
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pcl5: 622,
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pcl6: 377,
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pcl7: 1611,
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2011-02-15 20:04:08 +00:00
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pclp0: 488, // machine state: program counter low (pre-incremented?, second storage node)
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pclp1: 976,
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pclp2: 481,
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pclp3: 723,
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pclp4: 208,
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pclp5: 72,
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pclp6: 1458,
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pclp7: 1647,
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"#pclp0": 1227, // machine state: program counter low (pre-incremented?, inverse second storage node)
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"#pclp1": 1102,
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"#pclp2": 1079,
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"#pclp3": 868,
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"#pclp4": 39,
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"#pclp5": 1326,
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"#pclp6": 731,
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"#pclp7": 536,
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2010-09-25 10:30:25 +00:00
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pch0: 1670, // machine state: program counter high (first storage node)
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2010-09-18 16:56:48 +00:00
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pch1: 292,
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2010-09-25 10:30:25 +00:00
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pch2: 502,
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pch3: 584,
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pch4: 948,
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pch5: 49,
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pch6: 1551,
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pch7: 205,
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2011-04-01 11:59:22 +00:00
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pchp0: 1722, // machine state: program counter high (pre-incremented?, second storage node output)
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pchp1: 209,
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pchp2: 1496,
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pchp3: 141,
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pchp4: 27,
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pchp5: 1301,
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pchp6: 652,
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pchp7: 1206,
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"#pchp0": 780, // machine state: program counter high (pre-incremented?, inverse second storage node)
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"#pchp1": 113,
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"#pchp2": 114,
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"#pchp3": 124,
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"#pchp4": 820,
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"#pchp5": 33,
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"#pchp6": 751,
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"#pchp7": 535,
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// machine state: status register (not the storage nodes)
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p0: 32, // C bit of status register (storage node)
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p1: 627, // Z bit of status register (storage node)
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p2: 1553, // I bit of status register (storage node)
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p3: 348, // D bit of status register (storage node)
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p4: 1119, // there is no bit4 in the status register! (not a storage node)
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p5: -1, // there is no bit5 in the status register! (not a storage node)
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p6: 77, // V bit of status register (storage node)
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p7: 1370, // N bit of status register (storage node)
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// internal bus: status register outputs for push P
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Pout0: 687,
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Pout1: 1444,
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Pout2: 1421,
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Pout3: 439,
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Pout4: 1119, // there is no bit4 in the status register!
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Pout5: -1, // there is no bit5 in the status register!
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Pout6: 77,
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Pout7: 1370,
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2010-09-23 18:53:43 +00:00
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s0: 1403, // machine state: stack pointer
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s1: 183,
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s2: 81,
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s3: 1532,
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s4: 1702,
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s5: 1098,
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s6: 1212,
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s7: 1435,
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2010-09-24 14:02:57 +00:00
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ir0: 328, // internal state: instruction register
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ir1: 1626,
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ir2: 1384,
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ir3: 1576,
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ir4: 1112,
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2010-09-26 19:55:54 +00:00
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ir5: 1329, // ir5 distinguishes branch set from branch clear
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2010-09-24 14:02:57 +00:00
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ir6: 337,
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ir7: 1328,
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notir0: 194, // internal signal: instruction register inverted outputs
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2010-09-18 17:25:33 +00:00
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notir1: 702,
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2010-09-23 18:53:43 +00:00
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notir2: 1182,
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notir3: 1125,
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notir4: 26,
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notir5: 1394,
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notir6: 895,
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notir7: 1320,
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2010-09-24 14:02:57 +00:00
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irline3: 996, // internal signal: PLA input - ir0 AND ir1
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2011-04-01 11:59:22 +00:00
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clock1: 1536, // internal state: timing control aka #T0
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clock2: 156, // internal state: timing control aka #T+
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2010-09-23 18:53:43 +00:00
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t2: 971, // internal state: timing control
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2010-09-18 17:25:33 +00:00
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t3: 1567,
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t4: 690,
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t5: 909,
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2011-04-01 11:59:22 +00:00
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noty0: 1025, // datapath state: not Y register
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noty1: 1138,
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noty2: 1484,
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noty3: 184,
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noty4: 565,
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noty5: 981,
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noty6: 1439,
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noty7: 1640,
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notx0: 987, // datapath state: not X register
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notx1: 1434,
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notx2: 890,
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notx3: 1521,
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notx4: 485,
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notx5: 1017,
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notx6: 730,
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notx7: 1561,
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2010-09-23 18:53:43 +00:00
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nots0: 418, // datapath state: not stack pointer
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nots1: 1064,
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nots2: 752,
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nots3: 828,
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nots4: 1603,
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nots5: 601,
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nots6: 1029,
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nots7: 181,
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2010-09-25 10:30:25 +00:00
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notidl0: 116, // datapath state: internal data latch (first storage node)
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notidl1: 576,
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notidl2: 1485,
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notidl3: 1284,
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notidl4: 1516,
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notidl5: 498,
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notidl6: 1537,
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notidl7: 529,
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idl0: 1597, // datapath signal: internal data latch (driven output)
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idl1: 870,
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idl2: 1066,
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idl3: 464,
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idl4: 1306,
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idl5: 240,
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idl6: 1116,
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idl7: 391,
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2010-09-23 18:53:43 +00:00
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sb0: 54, // datapath bus: special bus
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sb1: 1150,
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sb2: 1287,
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sb3: 1188,
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sb4: 1405,
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sb5: 166,
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sb6: 1336,
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sb7: 1001,
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2011-04-01 11:59:22 +00:00
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notalu0: 394, // datapath state: alu output storage node (inverse) aka #ADD0
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2010-09-25 11:06:44 +00:00
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notalu1: 697,
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notalu2: 276,
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notalu3: 495,
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notalu4: 1490,
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notalu5: 893,
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notalu6: 68,
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notalu7: 1123,
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2011-04-01 11:59:22 +00:00
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alu0: 401, // datapath signal: ALU output aka ADD0out
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2010-09-25 11:06:44 +00:00
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alu1: 872,
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alu2: 1637,
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alu3: 1414,
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alu4: 606,
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alu5: 314,
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alu6: 331,
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alu7: 765,
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2010-09-27 17:24:42 +00:00
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// datapath signal: decimally adjusted special bus
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dasb0: 54, // same node as sb0
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dasb1: 1009,
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dasb2: 450,
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dasb3: 1475,
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dasb4: 1405, // same node as sb4
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dasb5: 263,
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dasb6: 679,
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dasb7: 1494,
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2011-04-01 11:59:22 +00:00
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adl0: 413, // internal bus: address low
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2010-09-18 17:25:33 +00:00
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adl1: 1282,
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adl2: 1242,
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adl3: 684,
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adl4: 1437,
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adl5: 1630,
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adl6: 121,
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adl7: 1299,
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2011-04-01 11:59:22 +00:00
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adh0: 407, // internal bus: address high
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2010-09-18 17:25:33 +00:00
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adh1: 52,
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adh2: 1651,
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adh3: 315,
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adh4: 1160,
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adh5: 483,
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adh6: 13,
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adh7: 1539,
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2011-04-01 11:59:22 +00:00
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idb0: 1108, // internal bus: data bus
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2010-09-18 17:25:33 +00:00
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idb1: 991,
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idb2: 1473,
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idb3: 1302,
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idb4: 892,
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idb5: 1503,
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idb6: 833,
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idb7: 493,
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2010-09-25 11:06:44 +00:00
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notdor0: 222, // internal state: data output register (storage node)
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notdor1: 527,
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notdor2: 1288,
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notdor3: 823,
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notdor4: 873,
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notdor5: 1266,
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notdor6: 1418,
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notdor7: 158,
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dor0: 97, // internal signal: data output register
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dor1: 746,
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dor2: 1634,
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dor3: 444,
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dor4: 1088,
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dor5: 1453,
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dor6: 1415,
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dor7: 63,
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2010-11-19 21:50:20 +00:00
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"pd0.clearIR": 1622, // internal state: predecode register output (anded with not ClearIR)
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"pd1.clearIR": 809,
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"pd2.clearIR": 1671,
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"pd3.clearIR": 1587,
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"pd4.clearIR": 540,
|
|
|
|
|
"pd5.clearIR": 667,
|
|
|
|
|
"pd6.clearIR": 1460,
|
|
|
|
|
"pd7.clearIR": 1410,
|
|
|
|
|
pd0: 758, // internal state: predecode register (storage node)
|
|
|
|
|
pd1: 361,
|
|
|
|
|
pd2: 955,
|
|
|
|
|
pd3: 894,
|
|
|
|
|
pd4: 369,
|
|
|
|
|
pd5: 829,
|
|
|
|
|
pd6: 1669,
|
|
|
|
|
pd7: 1690,
|
2011-04-01 11:59:22 +00:00
|
|
|
// internal signals: predecode latch partial decodes
|
|
|
|
|
"PD-xxxx10x0": 1019,
|
|
|
|
|
"PD-1xx000x0": 1294,
|
|
|
|
|
"PD-0xx0xx0x": 365,
|
|
|
|
|
"PD-xxx010x1": 302,
|
|
|
|
|
"PD-n-0xx0xx0x": 125,
|
|
|
|
|
"#TWOCYCLE": 851,
|
|
|
|
|
"#TWOCYCLE.phi1": 792,
|
|
|
|
|
"ONEBYTE": 778,
|
|
|
|
|
|
|
|
|
|
abl0: 1096, // internal bus: address bus low latched data out (inverse of inverted storage node)
|
|
|
|
|
abl1: 376,
|
|
|
|
|
abl2: 1502,
|
|
|
|
|
abl3: 1250,
|
|
|
|
|
abl4: 1232,
|
|
|
|
|
abl5: 234,
|
|
|
|
|
abl6: 178,
|
|
|
|
|
abl7: 567,
|
|
|
|
|
"#ABL0": 153, // internal state: address bus low latched data out (storage node, inverted)
|
|
|
|
|
"#ABL1": 107,
|
|
|
|
|
"#ABL2": 707,
|
|
|
|
|
"#ABL3": 825,
|
|
|
|
|
"#ABL4": 364,
|
|
|
|
|
"#ABL5": 1513,
|
|
|
|
|
"#ABL6": 1307,
|
|
|
|
|
"#ABL7": 28,
|
|
|
|
|
abh0: 1429, // internal bus: address bus high latched data out (inverse of inverted storage node)
|
|
|
|
|
abh1: 713,
|
|
|
|
|
abh2: 287,
|
|
|
|
|
abh3: 422,
|
|
|
|
|
abh4: 1143,
|
|
|
|
|
abh5: 775,
|
|
|
|
|
abh6: 997,
|
|
|
|
|
abh7: 489,
|
|
|
|
|
"#ABH0": 1062, // internal state: address bus high latched data out (storage node, inverted)
|
|
|
|
|
"#ABH1": 907,
|
|
|
|
|
"#ABH2": 768,
|
|
|
|
|
"#ABH3": 92,
|
|
|
|
|
"#ABH4": 668,
|
|
|
|
|
"#ABH5": 1128,
|
|
|
|
|
"#ABH6": 289,
|
|
|
|
|
"#ABH7": 429,
|
|
|
|
|
|
|
|
|
|
"branch-back": 626, // distinguish forward from backward branches
|
|
|
|
|
"branch-forward.phi1": 1110, // distinguish forward from backward branches
|
|
|
|
|
"branch-back.phi1": 771, // distinguish forward from backward branches in IPC logic
|
|
|
|
|
notRdy0: 248, // internal signal: global pipeline control
|
|
|
|
|
"notRdy0.phi1": 1272, // delayed pipeline control
|
|
|
|
|
"notRdy0.delay": 770, // global pipeline control latched by phi1 and then phi2
|
|
|
|
|
"#notRdy0.delay": 559, // global pipeline control latched by phi1 and then phi2 (storage node)
|
2010-09-30 19:20:56 +00:00
|
|
|
Reset0: 67, // internal signal: retimed reset from pin
|
|
|
|
|
C1x5Reset: 926, // retimed and pipelined reset in progress
|
|
|
|
|
notRnWprepad: 187, // internal signal: to pad, yet to be inverted and retimed
|
2011-04-01 11:59:22 +00:00
|
|
|
RnWstretched: 353, // internal signal: control datapad output drivers, aka TRISTATE
|
|
|
|
|
"#DBE": 1035, // internal signal: formerly from DBE pad (6501)
|
2010-09-23 18:53:43 +00:00
|
|
|
cp1: 710, // internal signal: clock phase 1
|
2010-09-24 14:02:57 +00:00
|
|
|
cclk: 943, // unbonded pad: internal non-overlappying phi2
|
2010-09-23 18:53:43 +00:00
|
|
|
fetch: 879, // internal signal
|
|
|
|
|
clearIR: 1077, // internal signal
|
|
|
|
|
H1x1: 1042, // internal signal: drive status byte onto databus
|
2010-09-23 19:38:16 +00:00
|
|
|
|
2010-09-24 14:02:57 +00:00
|
|
|
// internal signal: pla outputs block 1 (west/left edge of die)
|
2010-09-26 19:55:54 +00:00
|
|
|
// often 130 pla outputs are mentioned - we have 131 here
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-sty/cpy-mem": 1601, // pla0
|
|
|
|
|
"op-T3-ind-y": 60, // pla1
|
|
|
|
|
"op-T2-abs-y": 1512, // pla2
|
|
|
|
|
"op-T0-iny/dey": 382, // pla3
|
|
|
|
|
"x-op-T0-tya": 1173, // pla4
|
|
|
|
|
"op-T0-cpy/iny": 1233, // pla5
|
2010-09-23 19:38:16 +00:00
|
|
|
|
2010-09-24 14:02:57 +00:00
|
|
|
// internal signal: pla outputs block 2
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T2-idx-x-xy": 258, // pla6
|
|
|
|
|
"op-xy": 1562, // pla7
|
|
|
|
|
"op-T2-ind-x": 84, // pla8
|
|
|
|
|
"x-op-T0-txa": 1543, // pla9
|
|
|
|
|
"op-T0-dex": 76, // pla10
|
|
|
|
|
"op-T0-cpx/inx": 1658, // pla11
|
|
|
|
|
"op-from-x": 1540, // pla12
|
|
|
|
|
"op-T0-txs": 245, // pla13
|
|
|
|
|
"op-T0-ldx/tax/tsx": 985, // pla14
|
|
|
|
|
"op-T+-dex": 786, // pla15
|
|
|
|
|
"op-T+-inx": 1664, // pla16
|
|
|
|
|
"op-T0-tsx": 682, // pla17
|
|
|
|
|
"op-T+-iny/dey": 1482, // pla18
|
|
|
|
|
"op-T0-ldy-mem": 665, // pla19
|
|
|
|
|
"op-T0-tay/ldy-not-idx": 286, // pla20
|
2010-09-23 19:38:16 +00:00
|
|
|
|
|
|
|
|
// internal signal: pla outputs block 3
|
2010-09-24 14:02:57 +00:00
|
|
|
// not pla, feed through
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T0-jsr": 271, // pla21
|
|
|
|
|
"op-T5-brk": 370, // pla22
|
|
|
|
|
"op-T0-php/pha": 552, // pla23
|
|
|
|
|
"op-T4-rts": 1612, // pla24
|
|
|
|
|
"op-T3-plp/pla": 1487, // pla25
|
|
|
|
|
"op-T5-rti": 784, // pla26
|
|
|
|
|
"op-ror": 244, // pla27
|
|
|
|
|
"op-T2": 788, // pla28
|
|
|
|
|
"op-T0-eor": 1623, // pla29
|
|
|
|
|
"op-jmp": 764, // pla30
|
|
|
|
|
"op-T2-abs": 1057, // pla31
|
|
|
|
|
"op-T0-ora": 403, // pla32
|
|
|
|
|
"op-T2-ADL/ADD":204, // pla33
|
|
|
|
|
"op-T0":1273, // pla34
|
|
|
|
|
"op-T2-stack":1582, // pla35
|
|
|
|
|
"op-T3-stack/bit/jmp":1031, // pla36
|
2010-09-23 19:38:16 +00:00
|
|
|
|
2010-09-24 14:02:57 +00:00
|
|
|
// internal signal: pla outputs block 4
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T4-brk/jsr":804, // pla37
|
|
|
|
|
"op-T4-rti":1311, // pla38
|
|
|
|
|
"op-T3-ind-x":1428, // pla39
|
|
|
|
|
"op-T4-ind-y":492, // pla40
|
|
|
|
|
"op-T2-ind-y":1204, // pla41
|
|
|
|
|
"op-T3-abs-idx":58, // pla42
|
|
|
|
|
"op-plp/pla":1520, // pla43
|
|
|
|
|
"op-inc/nop":324, // pla44
|
|
|
|
|
"op-T4-ind-x":1259, // pla45
|
|
|
|
|
"x-op-T3-ind-y":342, // pla46
|
|
|
|
|
"op-rti/rts":857, // pla47
|
|
|
|
|
"op-T2-jsr":712, // pla48
|
|
|
|
|
"op-T0-cpx/cpy/inx/iny":1337, // pla49
|
|
|
|
|
"op-T0-cmp":1355, // pla50
|
|
|
|
|
"op-T0-sbc":787, // pla51 // 52:111XXXXX 1 0 T0SBC
|
|
|
|
|
"op-T0-adc/sbc":575, // pla52 // 51:X11XXXXX 1 0 T0ADCSBC
|
|
|
|
|
"op-rol/ror":1466, // pla53
|
2010-09-23 19:38:16 +00:00
|
|
|
|
2010-09-24 14:02:57 +00:00
|
|
|
// internal signal: pla outputs block 5
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T3-jmp":1381, // pla54
|
|
|
|
|
"op-shift":546, // pla55
|
|
|
|
|
"op-T5-jsr":776, // pla56
|
|
|
|
|
"op-T2-stack-access":157, // pla57
|
|
|
|
|
"op-T0-tya":257, // pla58
|
|
|
|
|
"op-T+-ora/and/eor/adc":1243, // pla59
|
|
|
|
|
"op-T+-adc/sbc":822, // pla60
|
|
|
|
|
"op-T+-shift-a":1324, // pla61
|
|
|
|
|
"op-T0-txa":179, // pla62
|
|
|
|
|
"op-T0-pla":131, // pla63
|
|
|
|
|
"op-T0-lda":1420, // pla64
|
|
|
|
|
"op-T0-acc":1342, // pla65
|
|
|
|
|
"op-T0-tay":4, // pla66
|
|
|
|
|
"op-T0-shift-a":1396, // pla67
|
|
|
|
|
"op-T0-tax":167, // pla68
|
|
|
|
|
"op-T0-bit":303, // pla69
|
|
|
|
|
"op-T0-and":1504, // pla70
|
|
|
|
|
"op-T4-abs-idx":354, // pla71
|
|
|
|
|
"op-T5-ind-y":1168, // pla72
|
2010-09-23 19:38:16 +00:00
|
|
|
|
|
|
|
|
// internal signal: pla outputs block 6
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-branch-done":1721, // pla73 // has extra non-pla input
|
|
|
|
|
"op-T2-pha":1086, // pla74
|
|
|
|
|
"op-T0-shift-right-a":1074, // pla75
|
|
|
|
|
"op-shift-right":1246, // pla76
|
|
|
|
|
"op-T2-brk":487, // pla77
|
|
|
|
|
"op-T3-jsr":579, // pla78
|
|
|
|
|
"op-sta/cmp":145, // pla79
|
|
|
|
|
"op-T2-branch":1239, // pla80 // T2BR, 83 for Balazs
|
|
|
|
|
"op-T2-zp/zp-idx":285, // pla81
|
2010-09-24 14:02:57 +00:00
|
|
|
// not pla, feed through
|
|
|
|
|
// not pla, feed through
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T2-ind":1524, // pla82
|
|
|
|
|
"op-T2-abs-access":273, // pla83 // has extra pulldown: pla97
|
|
|
|
|
"op-T5-rts":0, // pla84
|
|
|
|
|
"op-T4":341, // pla85
|
|
|
|
|
"op-T3":120, // pla86
|
|
|
|
|
"op-T0-brk/rti":1478, // pla87
|
|
|
|
|
"op-T0-jmp":594, // pla88
|
|
|
|
|
"op-T5-ind-x":1210, // pla89
|
|
|
|
|
"op-T3-abs/idx/ind":677, // pla90 // has extra pulldown: pla97
|
2010-09-23 19:38:16 +00:00
|
|
|
|
2010-09-24 14:02:57 +00:00
|
|
|
// internal signal: pla outputs block 7
|
2010-10-30 20:23:56 +00:00
|
|
|
"x-op-T4-ind-y":461, // pla91
|
|
|
|
|
"x-op-T3-abs-idx":447, // pla92
|
|
|
|
|
"op-T3-branch":660, // pla93
|
|
|
|
|
"op-brk/rti":1557, // pla94
|
|
|
|
|
"op-jsr":259, // pla95
|
|
|
|
|
"x-op-jmp":1052, // pla96
|
2010-09-24 14:02:57 +00:00
|
|
|
// gap
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-push/pull":791, // pla97 // feeds into pla83 and pla90 (no normal pla output)
|
|
|
|
|
"op-store":517, // pla98
|
|
|
|
|
"op-T4-brk":352, // pla99
|
|
|
|
|
"op-T2-php":750, // pla100
|
|
|
|
|
"op-T2-php/pha":932, // pla101
|
|
|
|
|
"op-T4-jmp":1589, // pla102
|
2010-09-24 14:02:57 +00:00
|
|
|
// gap
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T5-rti/rts":446, // pla103
|
|
|
|
|
"xx-op-T5-jsr":528, // pla104
|
2010-09-23 19:38:16 +00:00
|
|
|
|
2010-09-24 14:02:57 +00:00
|
|
|
// internal signal: pla outputs block 8
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T2-jmp-abs":309, // pla105
|
|
|
|
|
"x-op-T3-plp/pla":1430, // pla106
|
|
|
|
|
"op-lsr/ror/dec/inc":53, // pla107
|
|
|
|
|
"op-asl/rol":691, // pla108
|
|
|
|
|
"op-T0-cli/sei":1292, // pla109
|
2010-09-24 14:02:57 +00:00
|
|
|
// gap
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T+-bit":1646, // pla110
|
|
|
|
|
"op-T0-clc/sec":1114, // pla111
|
|
|
|
|
"op-T3-mem-zp-idx":904, // pla112
|
|
|
|
|
"x-op-T+-adc/sbc":1155, // pla113
|
|
|
|
|
"x-op-T0-bit":1476, // pla114
|
|
|
|
|
"op-T0-plp":1226, // pla115
|
|
|
|
|
"x-op-T4-rti":1569, // pla116
|
|
|
|
|
"op-T+-cmp":301, // pla117
|
|
|
|
|
"op-T+-cpx/cpy-abs":950, // pla118
|
|
|
|
|
"op-T+-asl/rol-a":1665, // pla119
|
2010-09-23 19:38:16 +00:00
|
|
|
|
2010-09-24 14:02:57 +00:00
|
|
|
// internal signal: pla outputs block 9
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T+-cpx/cpy-imm/zp":1710, // pla120
|
|
|
|
|
"x-op-push/pull":1050, // pla121 // feeds into pla130 (no normal pla output)
|
|
|
|
|
"op-T0-cld/sed":1419, // pla122
|
2010-11-01 17:31:48 +00:00
|
|
|
"#op-branch-bit6":840, // pla123 // IR bit6 used only to detect branch type
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-T3-mem-abs":607, // pla124
|
|
|
|
|
"op-T2-mem-zp":219, // pla125
|
|
|
|
|
"op-T5-mem-ind-idx":1385, // pla126
|
|
|
|
|
"op-T4-mem-abs-idx":281, // pla127
|
2010-11-01 17:31:48 +00:00
|
|
|
"#op-branch-bit7":1174, // pla128 // IR bit7 used only to detect branch type
|
2010-10-30 20:23:56 +00:00
|
|
|
"op-clv":1164, // pla129
|
|
|
|
|
"op-implied":1006, // pla130 // has extra pulldowns: pla121 and ir0
|
2010-09-26 19:55:54 +00:00
|
|
|
|
2011-04-01 11:59:22 +00:00
|
|
|
// internal signals: derived from pla outputs
|
|
|
|
|
"#op-branch-done": 1048,
|
|
|
|
|
"#op-T3-branch": 1708,
|
|
|
|
|
"op-ANDS": 1228,
|
|
|
|
|
"op-EORS": 1689,
|
|
|
|
|
"op-ORS": 522,
|
|
|
|
|
"op-SUMS": 1196,
|
|
|
|
|
"op-SRS": 934,
|
|
|
|
|
"#op-store": 925,
|
|
|
|
|
"#WR": 1352,
|
|
|
|
|
"op-rmw": 434,
|
|
|
|
|
"short-circuit-idx-add": 1185,
|
|
|
|
|
"short-circuit-branch-add": 430,
|
|
|
|
|
"#op-set-C": 252,
|
|
|
|
|
|
2010-09-26 19:55:54 +00:00
|
|
|
// internal signals: control signals
|
|
|
|
|
nnT2BR: 967, // doubly inverted
|
2011-04-01 11:59:22 +00:00
|
|
|
BRtaken: 1544, // aka #TAKEN
|
|
|
|
|
|
|
|
|
|
// internal signals and state: interrupt and vector related
|
|
|
|
|
// segher says:
|
|
|
|
|
// "P" are the latched external signals.
|
|
|
|
|
// "G" are the signals that actually trigger the interrupt.
|
|
|
|
|
// "NMIL" is to do the edge detection -- it's pretty much just a delayed NMIG.
|
|
|
|
|
// INTG is IRQ and NMI taken together.
|
|
|
|
|
IRQP: 675,
|
|
|
|
|
"#IRQP": 888,
|
|
|
|
|
NMIP: 1032,
|
|
|
|
|
"#NMIP": 297,
|
|
|
|
|
"#NMIG": 264,
|
|
|
|
|
NMIL: 1374,
|
|
|
|
|
RESP: 67,
|
|
|
|
|
RESG: 926,
|
|
|
|
|
VEC0: 1465,
|
|
|
|
|
VEC1: 1481,
|
|
|
|
|
"#VEC": 1134,
|
|
|
|
|
D1x1: 827, // internal signal: interrupt handler related
|
|
|
|
|
"brk-done": 1382, // internal signal: interrupt handler related
|
|
|
|
|
INTG: 1350, // internal signal: interrupt handler related
|
2010-09-26 19:55:54 +00:00
|
|
|
|
|
|
|
|
// internal state: misc pipeline state clocked by cclk (phi2)
|
2011-04-01 11:59:22 +00:00
|
|
|
"pipe#VEC": 1431, // latched #VEC
|
|
|
|
|
"pipeT-SYNC": 537,
|
|
|
|
|
pipeT2out: 40,
|
|
|
|
|
pipeT3out: 706,
|
|
|
|
|
pipeT4out: 1373,
|
|
|
|
|
pipeT5out: 940,
|
|
|
|
|
pipeIPCrelated: 832,
|
2010-09-26 19:55:54 +00:00
|
|
|
pipeUNK01: 1530,
|
|
|
|
|
pipeUNK02: 974,
|
|
|
|
|
pipeUNK03: 1436,
|
|
|
|
|
pipeUNK04: 99,
|
|
|
|
|
pipeUNK05: 44,
|
|
|
|
|
pipeUNK06: 443,
|
|
|
|
|
pipeUNK07: 215,
|
|
|
|
|
pipeUNK08: 338,
|
|
|
|
|
pipeUNK09: 199,
|
|
|
|
|
pipeUNK10: 215,
|
|
|
|
|
pipeUNK11: 1011,
|
|
|
|
|
pipeUNK12: 1283,
|
|
|
|
|
pipeUNK13: 1442,
|
|
|
|
|
pipeUNK14: 1607,
|
|
|
|
|
pipeUNK15: 1577, // inverse of H1x1, write P onto idb (PHP, interrupt)
|
|
|
|
|
pipeUNK16: 1051,
|
|
|
|
|
pipeUNK17: 1078,
|
|
|
|
|
pipeUNK18: 899,
|
|
|
|
|
pipeUNK19: 832,
|
|
|
|
|
pipeUNK20: 294,
|
|
|
|
|
pipeUNK21: 1176,
|
2010-09-26 21:39:58 +00:00
|
|
|
pipeUNK22: 561, // becomes dpc22
|
2010-09-26 19:55:54 +00:00
|
|
|
pipeUNK23: 596,
|
2010-09-30 19:20:56 +00:00
|
|
|
pipephi2Reset0: 449,
|
|
|
|
|
pipephi2Reset0x: 1036, // a second copy of the same latch
|
2010-09-26 19:55:54 +00:00
|
|
|
pipeUNK26: 1321,
|
|
|
|
|
pipeUNK27: 73,
|
|
|
|
|
pipeUNK28: 685,
|
|
|
|
|
pipeUNK29: 1008,
|
|
|
|
|
pipeUNK30: 1652,
|
|
|
|
|
pipeUNK31: 614,
|
|
|
|
|
pipeUNK32: 960,
|
|
|
|
|
pipeUNK33: 848,
|
|
|
|
|
pipeUNK34: 56,
|
|
|
|
|
pipeUNK35: 1713,
|
|
|
|
|
pipeUNK36: 729,
|
|
|
|
|
pipeUNK37: 197,
|
2011-04-01 11:59:22 +00:00
|
|
|
"pipe#WR.phi2": 1131,
|
2010-09-26 19:55:54 +00:00
|
|
|
pipeUNK39: 151,
|
|
|
|
|
pipeUNK40: 456,
|
|
|
|
|
pipeUNK41: 1438,
|
|
|
|
|
pipeUNK42: 1104,
|
2011-04-01 11:59:22 +00:00
|
|
|
"pipe#T0": 554, // aka #T0.phi2
|
2010-09-26 19:55:54 +00:00
|
|
|
|
|
|
|
|
// internal state: vector address pulldown control
|
|
|
|
|
pipeVectorA0: 357,
|
|
|
|
|
pipeVectorA1: 170,
|
|
|
|
|
pipeVectorA2: 45,
|
|
|
|
|
|
2011-04-01 11:59:22 +00:00
|
|
|
// internal signals: vector address pulldown control
|
|
|
|
|
"0/ADL0": 217,
|
|
|
|
|
"0/ADL1": 686,
|
|
|
|
|
"0/ADL2": 1193,
|
|
|
|
|
|
2010-09-26 19:55:54 +00:00
|
|
|
// internal state: datapath control drivers
|
|
|
|
|
pipedpc28: 683,
|
|
|
|
|
|
2010-09-25 10:30:25 +00:00
|
|
|
// internal signals: alu internal (private) busses
|
|
|
|
|
alua0: 1167,
|
2010-09-27 17:24:42 +00:00
|
|
|
alua1: 1248,
|
|
|
|
|
alua2: 1332,
|
|
|
|
|
alua3: 1680,
|
|
|
|
|
alua4: 1142,
|
|
|
|
|
alua5: 530,
|
|
|
|
|
alua6: 1627,
|
|
|
|
|
alua7: 1522,
|
2010-09-25 10:30:25 +00:00
|
|
|
alub0: 977,
|
2010-09-27 17:24:42 +00:00
|
|
|
alub1: 1432,
|
|
|
|
|
alub2: 704,
|
|
|
|
|
alub3: 96,
|
|
|
|
|
alub4: 1645,
|
|
|
|
|
alub5: 1678,
|
|
|
|
|
alub6: 235,
|
|
|
|
|
alub7: 1535,
|
|
|
|
|
|
2011-04-01 11:59:22 +00:00
|
|
|
// alu carry chain and decimal mode
|
|
|
|
|
C01: 1285,
|
|
|
|
|
C12: 505,
|
|
|
|
|
C23: 1023,
|
|
|
|
|
C34: 78,
|
|
|
|
|
C45: 142,
|
|
|
|
|
C56: 500,
|
|
|
|
|
C67: 1314,
|
|
|
|
|
C78: 808,
|
|
|
|
|
"C78.phi2": 560,
|
|
|
|
|
DC34: 1372, // lower nibble decimal carry
|
|
|
|
|
DC78: 333, // carry for decimal mode
|
|
|
|
|
"DC78.phi2": 164,
|
|
|
|
|
"#C01": 1506,
|
|
|
|
|
"#C12": 1122,
|
|
|
|
|
"#C23": 1003,
|
|
|
|
|
"#C34": 1425,
|
|
|
|
|
"#C45": 1571,
|
|
|
|
|
"#C56": 427,
|
|
|
|
|
"#C67": 592,
|
|
|
|
|
"#C78": 1327,
|
|
|
|
|
"DA-C01": 623,
|
|
|
|
|
"DA-AB2": 216,
|
|
|
|
|
"DA-AxB2": 516,
|
|
|
|
|
"DA-C45": 1144,
|
|
|
|
|
"#DA-ADD1": 901,
|
|
|
|
|
"#DA-ADD2": 699,
|
2010-12-03 12:14:18 +00:00
|
|
|
|
2011-04-01 11:59:22 +00:00
|
|
|
// misc alu internals
|
|
|
|
|
"#(AxBxC)0": 371,
|
|
|
|
|
"#(AxBxC)1": 965,
|
|
|
|
|
"#(AxBxC)2": 22,
|
|
|
|
|
"#(AxBxC)3": 274,
|
|
|
|
|
"#(AxBxC)4": 651,
|
|
|
|
|
"#(AxBxC)5": 486,
|
|
|
|
|
"#(AxBxC)6": 1197,
|
|
|
|
|
"#(AxBxC)7": 532,
|
|
|
|
|
AxB1: 425,
|
|
|
|
|
AxB3: 640,
|
|
|
|
|
AxB5: 1220,
|
|
|
|
|
AxB7: 1241,
|
|
|
|
|
"#(AxB)0": 1525,
|
|
|
|
|
"#(AxB)2": 701,
|
|
|
|
|
"#(AxB)4": 308,
|
|
|
|
|
"#(AxB)6": 1459,
|
|
|
|
|
"(AxB)0.#C0in": 555,
|
|
|
|
|
"(AxB)2.#C12": 193,
|
|
|
|
|
"(AxB)4.#C34": 65,
|
|
|
|
|
"(AxB)6.#C56": 174,
|
|
|
|
|
"#(AxB1).C01": 295,
|
|
|
|
|
"#(AxB3).C23": 860,
|
|
|
|
|
"#(AxB5).C45": 817,
|
|
|
|
|
"#(AxB7).C67": 1217,
|
|
|
|
|
"#A.B0": 1628,
|
|
|
|
|
"#A.B1": 841,
|
|
|
|
|
"#A.B2": 681,
|
|
|
|
|
"#A.B3": 350,
|
|
|
|
|
"#A.B4": 1063,
|
|
|
|
|
"#A.B5": 477,
|
|
|
|
|
"#A.B6": 336,
|
|
|
|
|
"#A.B7": 1318,
|
|
|
|
|
"A+B0": 693,
|
|
|
|
|
"A+B1": 1021,
|
|
|
|
|
"A+B2": 110,
|
|
|
|
|
"A+B3": 1313,
|
|
|
|
|
"A+B4": 918,
|
|
|
|
|
"A+B5": 1236,
|
|
|
|
|
"A+B6": 803,
|
|
|
|
|
"A+B7": 117,
|
|
|
|
|
"#(A+B)0": 143,
|
|
|
|
|
"#(A+B)1": 155,
|
|
|
|
|
"#(A+B)2": 1691,
|
|
|
|
|
"#(A+B)3": 649,
|
|
|
|
|
"#(A+B)4": 404,
|
|
|
|
|
"#(A+B)5": 1632,
|
|
|
|
|
"#(A+B)6": 1084,
|
|
|
|
|
"#(A+B)7": 1398,
|
|
|
|
|
"#(AxB)0": 1525,
|
|
|
|
|
"#(AxB)2": 701,
|
|
|
|
|
"#(AxB)4": 308,
|
|
|
|
|
"#(AxB)6": 1459,
|
|
|
|
|
"#(AxB)1": 953,
|
|
|
|
|
"#(AxB)3": 884,
|
|
|
|
|
"#(AxB)5": 1469,
|
|
|
|
|
"#(AxB)7": 177,
|
|
|
|
|
"#aluresult0": 957, // alu result latch input
|
|
|
|
|
"#aluresult1": 250,
|
|
|
|
|
"#aluresult2": 740,
|
|
|
|
|
"#aluresult3": 1071,
|
|
|
|
|
"#aluresult4": 296,
|
|
|
|
|
"#aluresult5": 277,
|
|
|
|
|
"#aluresult6": 722,
|
|
|
|
|
"#aluresult7": 304,
|
2010-09-25 10:30:25 +00:00
|
|
|
|
|
|
|
|
// internal signals: datapath control signals
|
2011-04-01 11:59:22 +00:00
|
|
|
|
|
|
|
|
"ADL/ABL": 639, // load ABL latches from ADL bus
|
|
|
|
|
"ADH/ABH": 821, // load ABH latches from ADH bus
|
|
|
|
|
|
2010-09-27 17:24:42 +00:00
|
|
|
dpc0_YSB: 801, // drive sb from y
|
|
|
|
|
dpc1_SBY: 325, // load y from sb
|
|
|
|
|
dpc2_XSB: 1263, // drive sb from x
|
|
|
|
|
dpc3_SBX: 1186, // load x from sb
|
|
|
|
|
dpc4_SSB: 1700, // drive sb from stack pointer
|
|
|
|
|
dpc5_SADL: 1468, // drive adl from stack pointer
|
|
|
|
|
dpc6_SBS: 874, // load stack pointer from sb
|
|
|
|
|
dpc7_SS: 654, // recirculate stack pointer
|
|
|
|
|
dpc8_nDBADD: 1068, // alu b side: select not-idb input
|
|
|
|
|
dpc9_DBADD: 859, // alu b side: select idb input
|
|
|
|
|
|
|
|
|
|
dpc10_ADLADD: 437, // alu b side: select adl input
|
|
|
|
|
dpc11_SBADD: 549, // alu a side: select sb
|
|
|
|
|
dpc12_0ADD: 984, // alu a side: select zero
|
|
|
|
|
dpc13_ORS: 59, // alu op: a or b
|
|
|
|
|
dpc14_SRS: 362, // alu op: logical right shift
|
|
|
|
|
dpc15_ANDS: 574, // alu op: a and b
|
|
|
|
|
dpc16_EORS: 1666, // alu op: a xor b (?)
|
|
|
|
|
dpc17_SUMS: 921, // alu op: a plus b (?)
|
2010-09-30 21:07:36 +00:00
|
|
|
alucin: 910, // alu carry in
|
|
|
|
|
notalucin: 1165,
|
2011-04-01 11:59:22 +00:00
|
|
|
"dpc18_#DAA": 1201, // decimal related (inverted)
|
2010-09-27 17:24:42 +00:00
|
|
|
dpc19_ADDSB7: 214, // alu to sb bit 7 only
|
|
|
|
|
|
|
|
|
|
dpc20_ADDSB06: 129, // alu to sb bits 6-0 only
|
|
|
|
|
dpc21_ADDADL: 1015, // alu to adl
|
2010-09-30 21:07:36 +00:00
|
|
|
alurawcout: 808, // alu raw carry out (no decimal adjust)
|
2011-04-01 11:59:22 +00:00
|
|
|
notalucout: 412, // alu carry out (inverted)
|
2010-09-30 21:07:36 +00:00
|
|
|
alucout: 1146, // alu carry out (latched by phi2)
|
2011-02-20 20:06:29 +00:00
|
|
|
"#alucout": 206,
|
|
|
|
|
"##alucout": 465,
|
2010-09-30 21:07:36 +00:00
|
|
|
notaluvout: 1308, // alu overflow out
|
|
|
|
|
aluvout: 938, // alu overflow out (latched by phi2)
|
2011-04-01 11:59:22 +00:00
|
|
|
|
|
|
|
|
"#DBZ": 1268, // internal signal: not (databus is zero)
|
|
|
|
|
DBZ: 744, // internal signal: databus is zero
|
|
|
|
|
DBNeg: 1200, // internal signal: databus is negative (top bit of db) aka P-#DB7in
|
|
|
|
|
|
|
|
|
|
"dpc22_#DSA": 725, // decimal related/SBC only (inverted)
|
2010-09-27 17:24:42 +00:00
|
|
|
dpc23_SBAC: 534, // (optionalls decimal-adjusted) sb to acc
|
|
|
|
|
dpc24_ACSB: 1698, // acc to sb
|
2011-04-01 11:59:22 +00:00
|
|
|
dpc25_SBDB: 1060, // sb pass-connects to idb (bi-directionally)
|
2010-09-27 17:24:42 +00:00
|
|
|
dpc26_ACDB: 1331, // acc to idb
|
2011-04-01 11:59:22 +00:00
|
|
|
dpc27_SBADH: 140, // sb pass-connects to adh (bi-directionally)
|
2010-09-27 17:24:42 +00:00
|
|
|
dpc28_0ADH0: 229, // zero to adh0 bit0 only
|
|
|
|
|
dpc29_0ADH17: 203, // zero to adh bits 7-1 only
|
|
|
|
|
|
|
|
|
|
dpc30_ADHPCH: 48, // load pch from adh
|
|
|
|
|
dpc31_PCHPCH: 741, // load pch from pch incremented
|
|
|
|
|
dpc32_PCHADH: 1235, // drive adh from pch incremented
|
|
|
|
|
dpc33_PCHDB: 247, // drive idb from pch incremented
|
|
|
|
|
dpc34_PCLC: 1704, // pch carry in and pcl FF detect?
|
2011-04-01 11:59:22 +00:00
|
|
|
dpc35_PCHC: 1334, // pcl 0x?F detect - half-carry
|
|
|
|
|
"dpc36_#IPC": 379, // pcl carry in (inverted)
|
2010-09-27 17:24:42 +00:00
|
|
|
dpc37_PCLDB: 283, // drive idb from pcl incremented
|
|
|
|
|
dpc38_PCLADL: 438, // drive adl from pcl incremented
|
|
|
|
|
dpc39_PCLPCL: 898, // load pcl from pcl incremented
|
|
|
|
|
|
|
|
|
|
dpc40_ADLPCL: 414, // load pcl from adl
|
2011-04-01 11:59:22 +00:00
|
|
|
"dpc41_DL/ADL": 1564,// pass-connect adl to mux node driven by idl
|
|
|
|
|
"dpc42_DL/ADH": 41, // pass-connect adh to mux node driven by idl
|
|
|
|
|
"dpc43_DL/DB": 863, // pass-connect idb to mux node driven by idl
|
|
|
|
|
|
2010-09-18 16:56:48 +00:00
|
|
|
}
|
2011-04-01 11:59:22 +00:00
|
|
|
|
|
|
|
|
/* many bus names taken from Donald F. Hanson's block diagram, found
|
|
|
|
|
* http://www.weihenstephan.org/~michaste/pagetable/6502/6502.jpg
|
|
|
|
|
* from his paper "A VHDL conversion tool for logic equations with embedded D latches"
|
|
|
|
|
* http://portal.acm.org/citation.cfm?id=1275143.1275151
|
|
|
|
|
* also available at
|
|
|
|
|
* http://www.ncsu.edu/wcae/WCAE1/hanson.pdf
|
|
|
|
|
*/
|
