import remainder of Segher's 6800 nodename updates and begin process of ordering and commenting
This commit is contained in:
BigEd
parent
a2d35d54ca
commit
79d0c4c445
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@ -168,6 +168,13 @@ addb5: 552,
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addb6: 545,
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addb7: 544,
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addg0: 593,
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addg1: 594,
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addg2: 589,
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addg3: 590,
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addg4: 585,
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addg5: 586,
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addg6: 581,
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addg7: 582,
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addp0: 564,
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addp1: 566,
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addp2: 556,
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@ -258,7 +265,7 @@ obl4: 29,
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obl5: 33,
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obl6: 1073,
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obl7: 35,
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pch0: 1878,
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pch0: 1878, // program counter high register
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pch1: 1882,
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pch2: 1879,
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pch3: 1883,
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@ -266,7 +273,7 @@ pch4: 1880,
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pch5: 1884,
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pch6: 1881,
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pch7: 1885,
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pcl0: 1877,
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pcl0: 1877, // program counter low register
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pcl1: 1873,
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pcl2: 1876,
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pcl3: 1872,
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@ -274,8 +281,10 @@ pcl4: 1875,
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pcl5: 1871,
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pcl6: 1874,
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pcl7: 1870,
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resg: 1512,
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sph0: 1909,
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sph0: 1909, // stack pointer high register
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sph1: 1908,
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sph2: 1907,
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sph3: 1906,
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@ -283,7 +292,7 @@ sph4: 1905,
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sph5: 1904,
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sph6: 1903,
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sph7: 1902,
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spl0: 1894,
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spl0: 1894, // stack pointer low register
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spl1: 1898,
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spl2: 1895,
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spl3: 1899,
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@ -291,7 +300,8 @@ spl4: 1896,
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spl5: 1900,
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spl6: 1897,
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spl7: 1901,
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sum0: 644,
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sum0: 644, // phi2-latched alu partial result
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sum1: 643,
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sum2: 642,
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sum3: 641,
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@ -299,7 +309,8 @@ sum4: 640,
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sum5: 639,
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sum6: 638,
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sum7: 412,
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tmp0: 1893,
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tmp0: 1893, // non-visible temporary register
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tmp1: 1892,
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tmp2: 1891,
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tmp3: 1890,
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@ -307,7 +318,8 @@ tmp4: 1889,
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tmp5: 1888,
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tmp6: 1887,
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tmp7: 1886,
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xi0: 1303,
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xi0: 1303, // half-latch prior to IR
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xi1: 1291,
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xi2: 1294,
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xi3: 1292,
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@ -317,6 +329,7 @@ xi6: 1275,
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xi7: 1276,
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// signals which are not purely alphabetical
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// note that underscore digit represents a logical duplication
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acca0_1: 342,
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acca1_1: 350,
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acca2_1: 344,
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@ -758,6 +771,13 @@ phi2_1: 478,
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"#xaccb/abl1": 460,
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"#xaccb/db": 760,
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"#xaddg0": 571,
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"#xaddg1": 570,
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"#xaddg2": 563,
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"#xaddg3": 562,
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"#xaddg4": 555,
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"#xaddg5": 554,
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"#xaddg6": 547,
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"#xaddg7": 546,
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"#xda/adda": 434,
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"#xdb/acca": 464,
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"#xdb/accb": 430,
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@ -897,4 +917,279 @@ phi2_1: 478,
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"flag0/db4": 309,
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"flag0/db5": 308,
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"ndb/adda": 415,
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// from this point: signals imported from Segher 2011-04-16 and not yet ordered or commented
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carry: 646,
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dbe_1: 1453,
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dec: 163,
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fetch: 849,
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halted: 2,
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int: 1083,
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irq_0: 3,
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irqg: 1183,
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nmi_0: 1477,
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nmig: 1192,
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restart: 1186,
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ta0: 879, // timing state signals also seen earlier with mixed-case names
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ta1: 838,
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ta2: 844,
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td0_0: 981,
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td0_1: 700,
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te1_0: 735,
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te1_1: 967,
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te1_2: 705,
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te1_3: 715,
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te1_4: 865,
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te1_5: 973,
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te1_6: 706,
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tg0: 12,
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tg1: 772,
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tg2: 832,
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tg3: 835,
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tg4: 696,
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tg5: 914,
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tg6: 911,
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tg7: 1081,
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tg8: 891,
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tr3: 823,
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tr4: 825,
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tr5: 828,
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tr6: 894,
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tr7: 694,
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tr8: 697,
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ts: 1309,
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tsc_0: 1508,
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tx0: 850,
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tx1: 851,
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tx2: 860,
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wait: 1234,
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wr: 788,
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writing: 1449,
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// the remainder of the imports need quoting
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"#alu-cin": 592,
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"#alu-cout": 595,
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"#alu-hin": 584,
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"#alu-hout": 1690,
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"#alu-or": 472,
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"#alu-or-xor": 475,
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"#carry16": 733,
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"#dbe_0": 1452,
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"#dbe_2": 1454,
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"#end": 1574,
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"#flagc_1": 942,
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"#i-ts": 1313,
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"#inc": 712,
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"#inch-cin": 78,
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"#next-cyc-fetch": 4,
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"#nmi_1": 1478,
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"#nmip": 1178,
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"#op-00xxxxxx_0": 945,
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"#op-ta0-a-alu": 1019,
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"#ta0-stx": 796,
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"#ta0.2_0": 873,
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"#ta1-0000100x": 798,
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"#ta1-0000100x.2": 799,
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"#ta1_0": 872,
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"#ta1_1": 1095,
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"#ta1_2": 960,
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"#taken": 1039,
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"#te0": 868,
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"#te0.2_0": 867,
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"#tx0_0": 971,
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"#tx0_1": 926,
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"#tx1_0": 727,
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"#xalu-cin": 943,
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"#xalu-or-xor": 479,
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"#xdbi/db": 536,
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"#xsum/db": 535,
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"alu-and": 473,
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"alu-sl": 578,
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"alu-sr/c": 1110,
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"alu-sub/c": 1144,
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"alu-sub/c_0": 1163,
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"alu-vout": 1058,
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"alu-zout": 645,
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"alu/c": 1147,
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"alu/c_0": 1164,
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"alu/h": 782,
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"alu/nz": 1027,
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"alu/v": 1112,
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"alu2/z": 1049,
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"da-c": 379,
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"da-h": 381,
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"db/ccr": 1107,
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"dbi/db": 531,
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"dec-low-adjust": 385,
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"do-alu-cin": 575,
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"force-wait": 1245,
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"inc16/z": 989,
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"incl-cout": 42,
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"insn/c": 1162,
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"insn/c_0": 1131,
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"insn/i": 1000,
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"insn/v": 1570,
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"irq-dis": 990,
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"irq-new": 1215,
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"ix/ab": 833,
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"nmi-done": 1172,
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"nmi-new": 1174,
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"no-address": 1489,
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"shift-vout": 1057,
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"shift/v": 1568,
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"sr-cin": 765,
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"t-before-fetch-simple": 1149,
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"ta0-two-cycle-insn": 965,
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"ta0.2": 878,
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"ta2-0000100x": 1028,
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"ta2-0000100x_0": 748,
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"ta2-0000100x_1": 759,
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"ta2-1xxx11xx": 1045,
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"ta3-0000100x": 1031,
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"te0.2": 866,
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"tsc-high": 1460,
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"tsc-low": 1476,
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"xalu-and": 483,
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// pla outputs (not in physical order)
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"op-0000011x": 1361,
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"op-0000100x": 1332,
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"op-0000100x_0": 1379,
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"op-0000100x_1": 1427,
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"op-0000101x": 1141,
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"op-0000110x": 1130,
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"op-0000xxxx": 1369,
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"op-0000xxxx_0": 1362,
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"op-00010110": 1355,
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"op-0001100x": 1394,
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"op-0001101x": 1346,
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"op-0001xxxx": 1360,
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"op-000x0110": 1391,
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"op-0010xxxx": 1380,
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"op-0010xxxx_0": 1363,
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"op-0010xxxx_1": 1399,
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"op-0010xxxx_2": 1426,
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"op-0011100x": 1381,
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"op-00111011": 1383,
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"op-00xxxxxx": 1342,
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"op-0100xxxx": 1432,
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"op-0101xxxx": 1425,
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"op-011x1101": 1387,
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"op-011x1110": 1398,
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"op-011xxxxx": 1337,
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"op-011xxxxx_0": 1322,
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"op-011xxxxx_1": 1320,
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"op-01xx01xx": 1443,
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"op-01xx01xx_0": 1396,
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"op-01xx0xxx": 1390,
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"op-01xx100x": 1345,
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"op-01xx100x_0": 1094,
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"op-01xx100x_1": 1334,
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"op-01xx1110": 1328,
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"op-01xx1110_0": 1341,
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"op-01xx11x1": 1428,
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"op-01xxx1xx": 1338,
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"op-0x01xxxx": 1343,
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"op-0x0xxxxx_0": 1364,
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"op-0xxxxxxx": 1439,
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"op-0xxxxxxx_0": 1401,
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"op-0xxxxxxx_1": 1437,
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"op-10xx0111": 1339,
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"op-10xx111x": 948,
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"op-10xxxxxx": 1384,
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"op-11xx0111": 1436,
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"op-11xx1110": 1366,
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"op-11xx1111": 1393,
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"op-11xxxxxx": 1327,
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"op-1x001101": 1349,
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"op-1x00xxxx": 1372,
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"op-1x10xxxx": 1350,
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"op-1x11xxxx": 1321,
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"op-1xx01101": 1352,
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"op-1xx0xxxx": 1371,
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"op-1xxx0010": 1354,
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"op-1xxx0111": 1323,
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"op-1xxx10x0": 1438,
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"op-1xxx10x1": 1444,
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"op-1xxx1100": 1378,
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"op-1xxx1100_0": 1442,
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"op-1xxx1101": 1356,
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"op-1xxx1101_0": 1388,
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"op-1xxx1101_1": 1434,
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"op-1xxx1111": 1389,
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"op-1xxx11x0": 1374,
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"op-1xxx11xx": 1431,
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"op-1xxx11xx_0": 1353,
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"op-1xxx11xx_1": 1430,
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"op-1xxx11xx_2": 1392,
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"op-1xxx11xx_3": 1340,
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"op-1xxx11xx_4": 1373,
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"op-1xxxx111": 1435,
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"op-1xxxx111_0": 1348,
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"op-1xxxxxxx": 846,
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"op-1xxxxxxx_0": 1150,
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"op-s-00000110": 1420,
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"op-s-00000111": 1407,
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"op-s-00001001": 1410,
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"op-s-0000100x": 1417,
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"op-s-0000100x_0": 1423,
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"op-s-0000111x": 1001,
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"op-s-00110101": 1411,
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"op-s-00110110": 1413,
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"op-s-00110111": 1414,
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"op-s-0011011x": 1415,
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"op-s-0011x1xx": 1421,
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"op-s-0011xxxx": 1409,
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"op-s-0x0xxxxx": 1419,
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"op-s-0x0xxxxx": 1422,
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"op-s-1x001101": 1412,
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"op-s-1x00xxxx": 1405,
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"op-s-1x01xxxx": 1418,
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"op-s-1x01xxxx_0": 1402,
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"op-s-1x01xxxx_1": 1416,
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"op-s-xx10xxxx": 1408,
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"op-s-xx10xxxx_0": 1403,
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"op-s-xx11xxxx": 1404,
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"op-xx11xxxx": 1357,
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"op-xxx011x": 1375,
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"op-xxx1xxxx": 1336,
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"op-xxxx0000": 1424,
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"op-xxxx000x": 1377,
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"op-xxxx0010": 1344,
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"op-xxxx0011": 1333,
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"op-xxxx001x": 1335,
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"op-xxxx00xx": 1433,
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"op-xxxx00xx_0": 1367,
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"op-xxxx0111": 1330,
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"op-xxxx01xx": 1395,
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"op-xxxx0x01": 1385,
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"op-xxxx0x0x": 1324,
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"op-xxxx0xxx": 1040,
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"op-xxxx0xxx_0": 1351,
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"op-xxxx1001": 1326,
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"op-xxxx100x": 1358,
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"op-xxxx10x1": 1365,
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"op-xxxx10x1_0": 1429,
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"op-xxxx10xx": 1325,
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"op-xxxx1100": 1440,
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"op-xxxx111x": 1359,
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"op-xxxx111x_0": 1400,
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"op-xxxx111x_1": 1368,
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"op-xxxx11xx": 1329,
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"op-xxxx11xx_0": 1382,
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"op-xxxx1xx1": 1386,
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"op-xxxx1xxx": 1397,
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"op-xxxxx11x": 1376,
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"op-xxxxx11x_0": 1441,
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"op-xxxxx1xx": 1370,
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"op-xxxxxx0x": 1041,
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"op-xxxxxx1x": 1446,
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"op-xxxxxxx0": 1138,
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"op-xxxxxxx0_0": 1003,
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"op-xxxxxxx1": 1331,
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"op-xxxxxxx1_0": 11,
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"op-xxxxxxx1_1": 1347,
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"op-xxxxxxx1_2": 1086,
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}
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