Merge branch 'ed' into staging
This commit is contained in:
Barry Silverman
commit
e72f11ee72
29
chipsim.js
29
chipsim.js
|
|
@ -21,6 +21,8 @@
|
|||
*/
|
||||
|
||||
var ctrace = false;
|
||||
var traceTheseNodes = [];
|
||||
var traceTheseTransistors = [];
|
||||
var noGraphics = false;
|
||||
var loglevel = 0;
|
||||
var ridx = 0;
|
||||
|
|
@ -30,7 +32,17 @@ function recalcNodeList(list){
|
|||
var recalclist = new Array();
|
||||
for(var j=0;j<100;j++){ // loop limiter
|
||||
if(list.length==0) return;
|
||||
if(ctrace) console.log(j, list);
|
||||
if(ctrace) {
|
||||
var i;
|
||||
for(i=0;i<traceTheseNodes.length;i++) {
|
||||
if(list.indexOf(traceTheseNodes[i])!=-1) break;
|
||||
}
|
||||
if((traceTheseNodes.length==0)||(list.indexOf(traceTheseNodes[i])==-1)) {
|
||||
console.log('recalcNodeList iteration: ', j, list.length, 'nodes');
|
||||
} else {
|
||||
console.log('recalcNodeList iteration: ', j, list.length, 'nodes', list);
|
||||
}
|
||||
}
|
||||
for(var i in list) recalcNode(list[i], recalclist);
|
||||
list = recalclist;
|
||||
recalclist = new Array();
|
||||
|
|
@ -43,10 +55,12 @@ function recalcNode(node, recalclist){
|
|||
if(node==npwr) return;
|
||||
var group = getNodeGroup(node);
|
||||
var newv = getNodeValue(group);
|
||||
if(ctrace) console.log('recalc', node, group);
|
||||
if(ctrace && (traceTheseNodes.indexOf(node)!=-1))
|
||||
console.log('recalc', node, group);
|
||||
for(var i in group){
|
||||
var n = nodes[group[i]];
|
||||
if(n.state!=newv && ctrace) console.log(group[i], n.state, newv);
|
||||
if(n.state!=newv && ctrace && (traceTheseNodes.indexOf(n)!=-1))
|
||||
console.log(group[i], n.state, newv);
|
||||
n.state = newv;
|
||||
for(var t in n.gates) recalcTransistor(n.gates[t], recalclist);
|
||||
}
|
||||
|
|
@ -60,7 +74,8 @@ function recalcTransistor(tn, recalclist){
|
|||
|
||||
function turnTransistorOn(t, recalclist){
|
||||
if(t.on) return;
|
||||
if(ctrace) console.log(t.name, 'on', t.gate, t.c1, t.c2);
|
||||
if(ctrace && (traceTheseTransistors.indexOf(t.name)!=-1))
|
||||
console.log(t.name, 'on', t.gate, t.c1, t.c2);
|
||||
t.on = true;
|
||||
addRecalcNode(t.c1, recalclist);
|
||||
addRecalcNode(t.c2, recalclist);
|
||||
|
|
@ -68,7 +83,8 @@ function turnTransistorOn(t, recalclist){
|
|||
|
||||
function turnTransistorOff(t, recalclist){
|
||||
if(!t.on) return;
|
||||
if(ctrace) console.log(t.name, 'off', t.gate, t.c1, t.c2);
|
||||
if(ctrace && (traceTheseTransistors.indexOf(t.name)!=-1))
|
||||
console.log(t.name, 'off', t.gate, t.c1, t.c2);
|
||||
t.on = false;
|
||||
floatnode(t.c1);
|
||||
floatnode(t.c2);
|
||||
|
|
@ -84,7 +100,8 @@ function floatnode(nn){
|
|||
if(n.state=='pd') n.state = 'fl';
|
||||
if(n.state=='vcc') n.state = 'fh';
|
||||
if(n.state=='pu') n.state = 'fh';
|
||||
if(ctrace) console.log('floating', nn, 'to', n.state);
|
||||
if(ctrace && (traceTheseNodes.indexOf(nn)!=-1))
|
||||
console.log('floating', nn, 'to', n.state);
|
||||
}
|
||||
|
||||
function addRecalcNode(nn, recalclist){
|
||||
|
|
|
|||
|
|
@ -113,14 +113,14 @@ var logThese=[
|
|||
['sync','irq','nmi'],
|
||||
['ab','db','rw','pc','a','x','y','s','p'],
|
||||
['adl','adh','sb','alu'],
|
||||
['notalucin','alucout','alua','alub','dasb'],
|
||||
['alucin','alua','alub','alucout','aluvout','dasb'],
|
||||
['idb','dor'],
|
||||
['ir','tcstate','pd'],
|
||||
];
|
||||
|
||||
function signalSet(n){
|
||||
var signals=[];
|
||||
for (var i=0; i<=n; i++){
|
||||
for (var i=0; (i<=n)&&(i<logThese.length) ; i++){
|
||||
for (var j=0; j<logThese[i].length; j++){
|
||||
signals.push(logThese[i][j]);
|
||||
}
|
||||
|
|
|
|||
16
nodenames.js
16
nodenames.js
|
|
@ -259,6 +259,10 @@ pd5: 829,
|
|||
pd6: 1669,
|
||||
pd7: 1690,
|
||||
notRdy0: 248, // internal signal: global pipeline control
|
||||
Reset0: 67, // internal signal: retimed reset from pin
|
||||
C1x5Reset: 926, // retimed and pipelined reset in progress
|
||||
notRnWprepad: 187, // internal signal: to pad, yet to be inverted and retimed
|
||||
RnWstretched: 353, // internal signal: control datapad output drivers
|
||||
cp1: 710, // internal signal: clock phase 1
|
||||
cclk: 943, // unbonded pad: internal non-overlappying phi2
|
||||
fetch: 879, // internal signal
|
||||
|
|
@ -451,8 +455,8 @@ pipeUNK20: 294,
|
|||
pipeUNK21: 1176,
|
||||
pipeUNK22: 561, // becomes dpc22
|
||||
pipeUNK23: 596,
|
||||
pipeUNK24: 449,
|
||||
pipeUNK25: 1036,
|
||||
pipephi2Reset0: 449,
|
||||
pipephi2Reset0x: 1036, // a second copy of the same latch
|
||||
pipeUNK26: 1321,
|
||||
pipeUNK27: 73,
|
||||
pipeUNK28: 685,
|
||||
|
|
@ -530,13 +534,17 @@ dpc14_SRS: 362, // alu op: logical right shift
|
|||
dpc15_ANDS: 574, // alu op: a and b
|
||||
dpc16_EORS: 1666, // alu op: a xor b (?)
|
||||
dpc17_SUMS: 921, // alu op: a plus b (?)
|
||||
notalucin: 1165, // alu carry in
|
||||
alucin: 910, // alu carry in
|
||||
notalucin: 1165,
|
||||
dpc18_DAA: 1201, // decimal related
|
||||
dpc19_ADDSB7: 214, // alu to sb bit 7 only
|
||||
|
||||
dpc20_ADDSB06: 129, // alu to sb bits 6-0 only
|
||||
dpc21_ADDADL: 1015, // alu to adl
|
||||
alucout: 938, // alu carry out (latched)
|
||||
alurawcout: 808, // alu raw carry out (no decimal adjust)
|
||||
alucout: 1146, // alu carry out (latched by phi2)
|
||||
notaluvout: 1308, // alu overflow out
|
||||
aluvout: 938, // alu overflow out (latched by phi2)
|
||||
dpc22_DSA: 725, // decimal related/SBC only
|
||||
dpc23_SBAC: 534, // (optionalls decimal-adjusted) sb to acc
|
||||
dpc24_ACSB: 1698, // acc to sb
|
||||
|
|
|
|||
Loading…
Reference in New Issue