nodename adjustments and additions

expertWires.js

@@ -195,17 +195,25 @@ function setupParams(){
 		} else
 		// setup input pin events, breakpoints, watchpoints
 		if(name=="reset0" && parseInt(value)!=NaN){
-			clockTriggers[value]="setLow('res');";
+			clockTriggers[value]=[clockTriggers[value],"setLow('res');"].join("");
 		} else if(name=="reset1" && parseInt(value)!=NaN){
-			clockTriggers[value]="setHigh('res');";
+			clockTriggers[value]=[clockTriggers[value],"setHigh('res');"].join("");
 		} else if(name=="irq0" && parseInt(value)!=NaN){
-			clockTriggers[value]="setLow('irq');";
+			clockTriggers[value]=[clockTriggers[value],"setLow('irq');"].join("");
 		} else if(name=="irq1" && parseInt(value)!=NaN){
-			clockTriggers[value]="setHigh('irq');";
+			clockTriggers[value]=[clockTriggers[value],"setHigh('irq');"].join("");
 		} else if(name=="nmi0" && parseInt(value)!=NaN){
-			clockTriggers[value]="setLow('nmi');";
+			clockTriggers[value]=[clockTriggers[value],"setLow('nmi');"].join("");
 		} else if(name=="nmi1" && parseInt(value)!=NaN){
-			clockTriggers[value]="setHigh('nmi');";
+			clockTriggers[value]=[clockTriggers[value],"setHigh('nmi');"].join("");
+		} else if(name=="rdy0" && parseInt(value)!=NaN){
+			clockTriggers[value]=[clockTriggers[value],"setLow('rdy');"].join("");
+		} else if(name=="rdy1" && parseInt(value)!=NaN){
+			clockTriggers[value]=[clockTriggers[value],"setHigh('rdy');"].join("");
+		} else if(name=="time" && parseInt(value)!=NaN){
+			eventTime=value;
+		} else if(name=="databus" && parseInt(value)!=NaN){
+			clockTriggers[eventTime]=[clockTriggers[eventTime],"writeDataBus(0x"+value+");"].join("");
 		} else
 		// run a test program, and optionally check against a golden checksum
 		if(name=="steps" && parseInt(value)!=NaN){

nodenames.js

@@ -82,7 +82,7 @@ x4: 85,
 x5: 589,
 x6: 448,
 x7: 777,
-pcl0: 1139,     // machine state: program counter low (first storage node)
+pcl0: 1139,     // machine state: program counter low (first storage node output)
 pcl1: 1022,
 pcl2: 655,
 pcl3: 1359,
@@ -90,14 +90,22 @@ pcl4: 900,
 pcl5: 622,
 pcl6: 377,
 pcl7: 1611,
-pclp0: 1227,    // machine state: program counter low (pre-incremented?, second storage node)
+pclp0: 488,    // machine state: program counter low (pre-incremented?, second storage node)
-pclp1: 1102,
+pclp1: 976,
-pclp2: 1079,
+pclp2: 481,
-pclp3: 868,
+pclp3: 723,
-pclp4: 39,
+pclp4: 208,
-pclp5: 1326,
+pclp5: 72,
-pclp6: 731,
+pclp6: 1458,
-pclp7: 536,
+pclp7: 1647,
+"#pclp0": 1227,    // machine state: program counter low (pre-incremented?, inverse second storage node)
+"#pclp1": 1102,
+"#pclp2": 1079,
+"#pclp3": 868,
+"#pclp4": 39,
+"#pclp5": 1326,
+"#pclp6": 731,
+"#pclp7": 536,
 pch0: 1670,     // machine state: program counter high (first storage node)
 pch1: 292,
 pch2: 502,
@@ -106,14 +114,22 @@ pch4: 948,
 pch5: 49,
 pch6: 1551,
 pch7: 205,
-pchp0: 780,     // machine state: program counter high (pre-incremented?, second storage node)
+pchp0: 1722,     // machine state: program counter high (pre-incremented?, second storage node output)
-pchp1: 113,
+pchp1: 209,
-pchp2: 114,
+pchp2: 1496,
-pchp3: 124,
+pchp3: 141,
-pchp4: 820,
+pchp4: 27,
-pchp5: 33,
+pchp5: 1301,
-pchp6: 751,
+pchp6: 652,
-pchp7: 535,
+pchp7: 1206,
+"#pchp0": 780,     // machine state: program counter high (pre-incremented?, inverse second storage node)
+"#pchp1": 113,
+"#pchp2": 114,
+"#pchp3": 124,
+"#pchp4": 820,
+"#pchp5": 33,
+"#pchp6": 751,
+"#pchp7": 535,
                 // machine state: status register (not the storage nodes)
 p0: 32,         // C bit of status register (storage node)
 p1: 627,        // Z bit of status register (storage node)
@@ -311,7 +327,7 @@ abl3: 1250,
 abl4: 1232,
 abl5: 234,
 abl6: 178,
-abl7: 178,
+abl7: 567,
 "#ABL0": 153,   // internal state: address bus low latched data out (storage node, inverted)
 "#ABL1": 107,
 "#ABL2": 707,
@@ -337,7 +353,13 @@ abh7: 489,
 "#ABH6": 289,
 "#ABH7": 429,
 
-notRdy0: 248,   // internal signal: global pipeline control
+"branch-back": 626,           // distinguish forward from backward branches
+"branch-forward.phi1": 1110,  // distinguish forward from backward branches
+"branch-back.phi1": 771,      // distinguish forward from backward branches in IPC logic
+notRdy0: 248,           // internal signal: global pipeline control
+"notRdy0.phi1": 1272,   // delayed pipeline control
+"notRdy0.delay": 770,   // global pipeline control latched by phi1 and then phi2
+"#notRdy0.delay": 559,  // global pipeline control latched by phi1 and then phi2 (storage node)
 Reset0: 67,     // internal signal: retimed reset from pin
 C1x5Reset: 926, // retimed and pipelined reset in progress
 notRnWprepad: 187, // internal signal: to pad, yet to be inverted and retimed
@@ -347,10 +369,7 @@ cp1: 710,       // internal signal: clock phase 1
 cclk: 943,      // unbonded pad: internal non-overlappying phi2
 fetch: 879,     // internal signal
 clearIR: 1077,  // internal signal
-D1x1: 827,      // internal signal: interrupt handler related
 H1x1: 1042,     // internal signal: drive status byte onto databus
-"brk-done": 1382,  // internal signal: interrupt handler related
-INTG: 1350,     // internal signal: interrupt handler related
 
                 // internal signal: pla outputs block 1 (west/left edge of die)
                 // often 130 pla outputs are mentioned - we have 131 here
@@ -510,6 +529,7 @@ INTG: 1350,     // internal signal: interrupt handler related
 
 // internal signals: derived from pla outputs
 "#op-branch-done": 1048,
+"#op-T3-branch": 1708,
 "op-ANDS": 1228,
 "op-EORS": 1689,
 "op-ORS": 522,
@@ -519,17 +539,33 @@ INTG: 1350,     // internal signal: interrupt handler related
 "#WR": 1352,
 "op-rmw": 434,
 "short-circuit-idx-add": 1185,
+"short-circuit-branch-add": 430,
 "#op-set-C": 252,
 
 // internal signals: control signals
 nnT2BR: 967,    // doubly inverted
 BRtaken: 1544,  // aka #TAKEN
 
-// interrupt and vector related
+// internal signals and state: interrupt and vector related
+// segher says:
+//   "P" are the latched external signals.
+//   "G" are the signals that actually trigger the interrupt.
+//   "NMIL" is to do the edge detection -- it's pretty much just a delayed NMIG.
+//   INTG is IRQ and NMI taken together.
+IRQP: 675,
+"#IRQP": 888,
 NMIP: 1032,
+"#NMIP": 297,
+"#NMIG": 264,
+NMIL: 1374,
+RESP: 67,
+RESG: 926,
 VEC0: 1465,
 VEC1: 1481,
 "#VEC": 1134,
+D1x1: 827,         // internal signal: interrupt handler related
+"brk-done": 1382,  // internal signal: interrupt handler related
+INTG: 1350,        // internal signal: interrupt handler related
 
 // internal state: misc pipeline state clocked by cclk (phi2)
 "pipe#VEC": 1431,     // latched #VEC
@@ -538,7 +574,7 @@ pipeT2out: 40,
 pipeT3out: 706,
 pipeT4out: 1373,
 pipeT5out: 940,
-pipeBRtaken: 832,
+pipeIPCrelated: 832,
 pipeUNK01: 1530,
 pipeUNK02: 974,
 pipeUNK03: 1436,
@@ -742,6 +778,8 @@ dpc21_ADDADL: 1015,  // alu to adl
 alurawcout: 808,     // alu raw carry out (no decimal adjust)
 notalucout: 412,     // alu carry out (inverted)
 alucout: 1146,       // alu carry out (latched by phi2)
+"#alucout": 206,
+"##alucout": 465,
 notaluvout: 1308,    // alu overflow out
 aluvout: 938,        // alu overflow out (latched by phi2)
 
@@ -764,7 +802,7 @@ dpc32_PCHADH: 1235,  // drive adh from pch incremented
 dpc33_PCHDB: 247,    // drive idb from pch incremented
 dpc34_PCLC: 1704,    // pch carry in and pcl FF detect?
 dpc35_PCHC: 1334,    // pcl 0x?F detect - half-carry
-dpc36_IPC: 379,      // pcl carry in
+"dpc36_#IPC": 379,   // pcl carry in (inverted)
 dpc37_PCLDB: 283,    // drive idb from pcl incremented
 dpc38_PCLADL: 438,   // drive adl from pcl incremented
 dpc39_PCLPCL: 898,   // load pcl from pcl incremented

wires.js

@@ -29,6 +29,7 @@ var ngnd = nodenames['vss'];
 var npwr = nodenames['vcc'];
 
 var chipLayoutIsVisible = true;  // only modified in expert mode
+var hilited = [];
 
 function setupNodes(){
 	for(var i in segdefs){
@@ -140,6 +141,7 @@ function refresh(){
 	for(i in nodes){
 		if(isNodeHigh(i)) overlayNode(nodes[i].segs);
 	}
+	hiliteNode(hilited);
 }
 
 function overlayNode(w){
@@ -156,6 +158,7 @@ function hiliteNode(n){
 	var ctx = hilite.getContext('2d');
 	ctx.clearRect(0,0,grCanvasSize,grCanvasSize);
 	if(n==-1) return;
+	hilited = n;
 
 	for(var i in n){
 		if(typeof n[i] != "number") {