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https://github.com/trebonian/visual6502.git
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9 Commits
Author | SHA1 | Date | |
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15b25491b9 | |||
6033109dc6 | |||
0e41f0a9a9 | |||
cb29fb4fad | |||
c02d181d5c | |||
51d0e99389 | |||
d11cf44ae9 | |||
2e69d3a7c3 | |||
f098566335 |
@ -195,17 +195,25 @@ function setupParams(){
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} else
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// setup input pin events, breakpoints, watchpoints
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if(name=="reset0" && parseInt(value)!=NaN){
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clockTriggers[value]="setLow('res');";
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clockTriggers[value]=[clockTriggers[value],"setLow('res');"].join("");
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} else if(name=="reset1" && parseInt(value)!=NaN){
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clockTriggers[value]="setHigh('res');";
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clockTriggers[value]=[clockTriggers[value],"setHigh('res');"].join("");
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} else if(name=="irq0" && parseInt(value)!=NaN){
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clockTriggers[value]="setLow('irq');";
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clockTriggers[value]=[clockTriggers[value],"setLow('irq');"].join("");
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} else if(name=="irq1" && parseInt(value)!=NaN){
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clockTriggers[value]="setHigh('irq');";
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clockTriggers[value]=[clockTriggers[value],"setHigh('irq');"].join("");
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} else if(name=="nmi0" && parseInt(value)!=NaN){
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clockTriggers[value]="setLow('nmi');";
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clockTriggers[value]=[clockTriggers[value],"setLow('nmi');"].join("");
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} else if(name=="nmi1" && parseInt(value)!=NaN){
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clockTriggers[value]="setHigh('nmi');";
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clockTriggers[value]=[clockTriggers[value],"setHigh('nmi');"].join("");
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} else if(name=="rdy0" && parseInt(value)!=NaN){
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clockTriggers[value]=[clockTriggers[value],"setLow('rdy');"].join("");
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} else if(name=="rdy1" && parseInt(value)!=NaN){
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clockTriggers[value]=[clockTriggers[value],"setHigh('rdy');"].join("");
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} else if(name=="time" && parseInt(value)!=NaN){
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eventTime=value;
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} else if(name=="databus" && parseInt(value)!=NaN){
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clockTriggers[eventTime]=[clockTriggers[eventTime],"writeDataBus(0x"+value+");"].join("");
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} else
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// run a test program, and optionally check against a golden checksum
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if(name=="steps" && parseInt(value)!=NaN){
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88
nodenames.js
88
nodenames.js
@ -82,7 +82,7 @@ x4: 85,
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x5: 589,
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x6: 448,
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x7: 777,
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pcl0: 1139, // machine state: program counter low (first storage node)
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pcl0: 1139, // machine state: program counter low (first storage node output)
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pcl1: 1022,
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pcl2: 655,
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pcl3: 1359,
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@ -90,14 +90,22 @@ pcl4: 900,
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pcl5: 622,
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pcl6: 377,
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pcl7: 1611,
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pclp0: 1227, // machine state: program counter low (pre-incremented?, second storage node)
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pclp1: 1102,
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pclp2: 1079,
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pclp3: 868,
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pclp4: 39,
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pclp5: 1326,
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pclp6: 731,
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pclp7: 536,
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pclp0: 488, // machine state: program counter low (pre-incremented?, second storage node)
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pclp1: 976,
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pclp2: 481,
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pclp3: 723,
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pclp4: 208,
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pclp5: 72,
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pclp6: 1458,
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pclp7: 1647,
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"#pclp0": 1227, // machine state: program counter low (pre-incremented?, inverse second storage node)
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"#pclp1": 1102,
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"#pclp2": 1079,
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"#pclp3": 868,
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"#pclp4": 39,
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"#pclp5": 1326,
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"#pclp6": 731,
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"#pclp7": 536,
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pch0: 1670, // machine state: program counter high (first storage node)
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pch1: 292,
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pch2: 502,
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@ -106,14 +114,22 @@ pch4: 948,
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pch5: 49,
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pch6: 1551,
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pch7: 205,
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pchp0: 780, // machine state: program counter high (pre-incremented?, second storage node)
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pchp1: 113,
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pchp2: 114,
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pchp3: 124,
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pchp4: 820,
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pchp5: 33,
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pchp6: 751,
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pchp7: 535,
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pchp0: 1722, // machine state: program counter high (pre-incremented?, second storage node output)
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pchp1: 209,
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pchp2: 1496,
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pchp3: 141,
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pchp4: 27,
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pchp5: 1301,
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pchp6: 652,
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pchp7: 1206,
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"#pchp0": 780, // machine state: program counter high (pre-incremented?, inverse second storage node)
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"#pchp1": 113,
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"#pchp2": 114,
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"#pchp3": 124,
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"#pchp4": 820,
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"#pchp5": 33,
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"#pchp6": 751,
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"#pchp7": 535,
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// machine state: status register (not the storage nodes)
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p0: 32, // C bit of status register (storage node)
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p1: 627, // Z bit of status register (storage node)
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@ -311,7 +327,7 @@ abl3: 1250,
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abl4: 1232,
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abl5: 234,
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abl6: 178,
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abl7: 178,
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abl7: 567,
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"#ABL0": 153, // internal state: address bus low latched data out (storage node, inverted)
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"#ABL1": 107,
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"#ABL2": 707,
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@ -337,7 +353,13 @@ abh7: 489,
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"#ABH6": 289,
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"#ABH7": 429,
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notRdy0: 248, // internal signal: global pipeline control
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"branch-back": 626, // distinguish forward from backward branches
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"branch-forward.phi1": 1110, // distinguish forward from backward branches
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"branch-back.phi1": 771, // distinguish forward from backward branches in IPC logic
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notRdy0: 248, // internal signal: global pipeline control
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"notRdy0.phi1": 1272, // delayed pipeline control
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"notRdy0.delay": 770, // global pipeline control latched by phi1 and then phi2
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"#notRdy0.delay": 559, // global pipeline control latched by phi1 and then phi2 (storage node)
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Reset0: 67, // internal signal: retimed reset from pin
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C1x5Reset: 926, // retimed and pipelined reset in progress
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notRnWprepad: 187, // internal signal: to pad, yet to be inverted and retimed
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@ -347,10 +369,7 @@ cp1: 710, // internal signal: clock phase 1
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cclk: 943, // unbonded pad: internal non-overlappying phi2
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fetch: 879, // internal signal
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clearIR: 1077, // internal signal
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D1x1: 827, // internal signal: interrupt handler related
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H1x1: 1042, // internal signal: drive status byte onto databus
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"brk-done": 1382, // internal signal: interrupt handler related
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INTG: 1350, // internal signal: interrupt handler related
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// internal signal: pla outputs block 1 (west/left edge of die)
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// often 130 pla outputs are mentioned - we have 131 here
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@ -510,6 +529,7 @@ INTG: 1350, // internal signal: interrupt handler related
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// internal signals: derived from pla outputs
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"#op-branch-done": 1048,
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"#op-T3-branch": 1708,
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"op-ANDS": 1228,
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"op-EORS": 1689,
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"op-ORS": 522,
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@ -519,17 +539,33 @@ INTG: 1350, // internal signal: interrupt handler related
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"#WR": 1352,
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"op-rmw": 434,
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"short-circuit-idx-add": 1185,
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"short-circuit-branch-add": 430,
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"#op-set-C": 252,
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// internal signals: control signals
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nnT2BR: 967, // doubly inverted
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BRtaken: 1544, // aka #TAKEN
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// interrupt and vector related
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// internal signals and state: interrupt and vector related
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// segher says:
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// "P" are the latched external signals.
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// "G" are the signals that actually trigger the interrupt.
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// "NMIL" is to do the edge detection -- it's pretty much just a delayed NMIG.
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// INTG is IRQ and NMI taken together.
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IRQP: 675,
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"#IRQP": 888,
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NMIP: 1032,
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"#NMIP": 297,
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"#NMIG": 264,
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NMIL: 1374,
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RESP: 67,
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RESG: 926,
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VEC0: 1465,
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VEC1: 1481,
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"#VEC": 1134,
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D1x1: 827, // internal signal: interrupt handler related
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"brk-done": 1382, // internal signal: interrupt handler related
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INTG: 1350, // internal signal: interrupt handler related
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// internal state: misc pipeline state clocked by cclk (phi2)
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"pipe#VEC": 1431, // latched #VEC
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@ -538,7 +574,7 @@ pipeT2out: 40,
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pipeT3out: 706,
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pipeT4out: 1373,
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pipeT5out: 940,
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pipeBRtaken: 832,
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pipeIPCrelated: 832,
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pipeUNK01: 1530,
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pipeUNK02: 974,
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pipeUNK03: 1436,
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@ -742,6 +778,8 @@ dpc21_ADDADL: 1015, // alu to adl
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alurawcout: 808, // alu raw carry out (no decimal adjust)
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notalucout: 412, // alu carry out (inverted)
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alucout: 1146, // alu carry out (latched by phi2)
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"#alucout": 206,
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"##alucout": 465,
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notaluvout: 1308, // alu overflow out
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aluvout: 938, // alu overflow out (latched by phi2)
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@ -764,7 +802,7 @@ dpc32_PCHADH: 1235, // drive adh from pch incremented
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dpc33_PCHDB: 247, // drive idb from pch incremented
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dpc34_PCLC: 1704, // pch carry in and pcl FF detect?
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dpc35_PCHC: 1334, // pcl 0x?F detect - half-carry
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dpc36_IPC: 379, // pcl carry in
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"dpc36_#IPC": 379, // pcl carry in (inverted)
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dpc37_PCLDB: 283, // drive idb from pcl incremented
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dpc38_PCLADL: 438, // drive adl from pcl incremented
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dpc39_PCLPCL: 898, // load pcl from pcl incremented
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3
wires.js
3
wires.js
@ -29,6 +29,7 @@ var ngnd = nodenames['vss'];
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var npwr = nodenames['vcc'];
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var chipLayoutIsVisible = true; // only modified in expert mode
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var hilited = [];
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function setupNodes(){
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for(var i in segdefs){
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@ -140,6 +141,7 @@ function refresh(){
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for(i in nodes){
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if(isNodeHigh(i)) overlayNode(nodes[i].segs);
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}
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hiliteNode(hilited);
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}
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function overlayNode(w){
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@ -156,6 +158,7 @@ function hiliteNode(n){
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var ctx = hilite.getContext('2d');
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ctx.clearRect(0,0,grCanvasSize,grCanvasSize);
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if(n==-1) return;
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hilited = n;
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for(var i in n){
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if(typeof n[i] != "number") {
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Reference in New Issue
Block a user