improve 6800 machine state display

README

@@ -4,6 +4,8 @@ www.visual6502.org/JSSim
 It includes a general purpose transistor-level simulator, layout browser,
 and the data from a 6502 revD chip. 
 
+Recently added: polygon data for the 6800 chip. The simulation is not yet working,
+
 Note the various licenses and Copyright associated with each file.
 
 Enjoy!

chip-6800/nodenames.js

@@ -0,0 +1,868 @@
+/*
+ Copyright (c) 2011 Ijor, Segher Boessenkool, Ed Spittles
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+
+var nodenames ={
+gnd: 663,      // pads: ground
+vcc: 31,       // pads: power
+phi1: 1507,    // pads: phase 1 clock input
+phi2: 1511,    // pads: phase 2 clock input
+reset: 1461,   // pads: reset
+db0: 686,       // pads: data bus
+db1: 683,
+db2: 677,
+db3: 676,
+db4: 669,
+db5: 670,
+db6: 664,
+db7: 691,
+ab0: 1854,       // pads: address bus
+ab1: 1857,
+ab2: 1855,
+ab3: 1858,
+ab4: 1856,
+ab5: 1859,
+ab6: 1860,
+ab7: 1865,
+ab8: 1861,
+ab9: 1863,
+ab10: 1862,
+ab11: 1864,
+ab12: 1948,
+ab13: 1946,
+ab14: 1949,
+ab15: 1947,
+irq: 1496,     // input pads: interrupt request (active low)
+nmi: 1501,     // pads: non maskable interrupt (active low)
+dbe: 1456,     // pads: data bus enable
+halt: 1492,    // pads: halt (active low)
+tsc: 1459,     // pads: tristate control
+rw: 1965,      // output pads: read / not write
+vma: 1971,     // pads: valid memory address
+ba: 1964,      // pads: bus available
+//
+
+// internal state: Instruction Register
+ir0: 1301,
+ir1: 1285,
+ir2: 1286,
+ir3: 1287,
+ir4: 1288,
+ir5: 1289,
+ir6: 1274,
+ir7: 1277,
+
+// internal control signals
+sync: 1528,   // aka #decode_0
+
+// many other internal busses registers and signals
+abh0: 267,
+abh1: 258,
+abh2: 266,
+abh3: 257,
+abh4: 265,
+abh5: 256,
+abh6: 259,
+abh7: 255,
+ablx0: 1683,
+ablx1: 1682,
+ablx2: 1689,
+ablx3: 1687,
+ablx4: 1694,
+ablx5: 1693,
+ablx6: 1698,
+ablx7: 1697,
+abl0: 1670,
+abl1: 1671,
+abl2: 1653,
+abl3: 1667,
+abl4: 1655,
+abl5: 1657,
+abl6: 1656,
+abl7: 1658,
+acca0: 1934,
+acca1: 1688,
+acca2: 1700,
+acca3: 1699,
+acca4: 1701,
+acca5: 1702,
+acca6: 1703,
+acca7: 1784,
+accb0: 1919,
+accb1: 1927,
+accb2: 1921,
+accb3: 1929,
+accb4: 1923,
+accb5: 1931,
+accb6: 1925,
+accb7: 1933,
+adda0: 1680,
+adda1: 1681,
+adda2: 1685,
+adda3: 1686,
+adda4: 1691,
+adda5: 1692,
+adda6: 1695,
+adda7: 1696,
+adda0in: 1938,
+adda1in: 1940,
+adda2in: 1939,
+adda3in: 1942,
+adda4in: 1941,
+adda5in: 1944,
+adda6in: 1943,
+adda7in: 1945,
+addb0: 569,
+addb1: 568,
+addb2: 561,
+addb3: 560,
+addb4: 553,
+addb5: 552,
+addb6: 545,
+addb7: 544,
+idb0: 610,
+idb1: 1593,
+idb2: 387,
+idb3: 386,
+idb4: 311,
+idb5: 310,
+idb6: 393,
+idb7: 1651,
+dbi0: 608,
+dbi1: 599,
+dbi2: 598,
+dbi3: 400,
+dbi4: 405,
+dbi5: 395,
+dbi6: 389,
+dbi7: 650,
+dbo0: 609,
+dbo1: 602,
+dbo2: 601,
+dbo3: 402,
+dbo4: 406,
+dbo5: 397,
+dbo6: 390,
+dbo7: 649,
+decode: 1225,
+i0: 1271,  // pla word lines
+i1: 1269,
+i2: 1268,
+i3: 1267,
+i4: 1265,
+i5: 1264,
+i6: 1263,
+i7: 1261,
+inch0: 198,
+inch1: 199,
+inch2: 200,
+inch3: 201,
+inch4: 202,
+inch5: 203,
+inch6: 204,
+inch7: 205,
+incl0: 154,
+incl1: 143,
+incl2: 144,
+incl3: 147,
+incl4: 148,
+incl5: 151,
+incl6: 152,
+incl7: 156,
+ixh0: 1910,
+ixh1: 1914,
+ixh2: 1911,
+ixh3: 1915,
+ixh4: 1912,
+ixh5: 1916,
+ixh6: 1913,
+ixh7: 1917,
+ixl0: 1918,
+ixl1: 1926,
+ixl2: 1920,
+ixl3: 1928,
+ixl4: 1922,
+ixl5: 1930,
+ixl6: 1924,
+ixl7: 1932,
+ob: 1308,
+obl0: 27,
+obl1: 30,
+obl2: 28,
+obl3: 32,
+obl4: 29,
+obl5: 33,
+obl6: 1073,
+obl7: 35,
+pch0: 1878,
+pch1: 1882,
+pch2: 1879,
+pch3: 1883,
+pch4: 1880,
+pch5: 1884,
+pch6: 1881,
+pch7: 1885,
+pcl0: 1877,
+pcl1: 1873,
+pcl2: 1876,
+pcl3: 1872,
+pcl4: 1875,
+pcl5: 1871,
+pcl6: 1874,
+pcl7: 1870,
+res: 1512,
+sph0: 1909,
+sph1: 1908,
+sph2: 1907,
+sph3: 1906,
+sph4: 1905,
+sph5: 1904,
+sph6: 1903,
+sph7: 1902,
+spl0: 1894,
+spl1: 1898,
+spl2: 1895,
+spl3: 1899,
+spl4: 1896,
+spl5: 1900,
+spl6: 1897,
+spl7: 1901,
+sum0: 644,
+sum1: 643,
+sum2: 642,
+sum3: 641,
+sum4: 640,
+sum5: 639,
+sum6: 638,
+sum7: 412,
+sumab0: 564,
+sumab1: 566,
+sumab2: 556,
+sumab3: 558,
+sumab4: 548,
+sumab5: 550,
+sumab6: 541,
+sumab7: 543,
+tmp0: 1893,
+tmp1: 1892,
+tmp2: 1891,
+tmp3: 1890,
+tmp4: 1889,
+tmp5: 1888,
+tmp6: 1887,
+tmp7: 1886,
+enrwa: 1318,
+flagc: 1160,
+flagh: 785,
+flagi: 1007,
+flagn: 1005,
+flagv: 1124,
+flagz: 1026,
+qaddgen0: 593,
+acca0_1: 342,
+acca1_1: 350,
+acca2_1: 344,
+acca3_1: 352,
+acca4_1: 346,
+acca5_1: 354,
+acca6_1: 348,
+acca7_1: 356,
+accb0_1: 343,
+accb1_1: 351,
+accb2_1: 345,
+accb3_1: 353,
+accb4_1: 347,
+accb5_1: 355,
+accb6_1: 349,
+accb7_1: 357,
+ahd0_0: 237,
+ahd1_0: 240,
+ahd2_0: 236,
+ahd3_0: 239,
+ahd4_0: 235,
+ahd5_0: 238,
+ahd6_0: 234,
+ahd7_0: 252,
+ald0_0: 74,
+ald1_0: 71,
+ald2_0: 68,
+ald3_0: 65,
+ald4_0: 62,
+ald5_0: 34,
+ald6_0: 56,
+ald7_0: 53,
+ba_0: 1228,
+idb0_2: 521,
+idb1_2: 520,
+idb2_2: 517,
+idb3_2: 516,
+idb4_2: 513,
+idb5_2: 512,
+idb6_2: 509,
+idb7_2: 508,
+decode_1: 1304,
+halt_0: 1491,
+inchi0_0: 206,
+inchi1_0: 208,
+inchi2_0: 207,
+inchi4_0: 245,
+inchi5_0: 243,
+inchi6_0: 242,
+incli0_0: 89,
+incli1_0: 90,
+incli2_0: 88,
+incli4_0: 93,
+incli5_0: 91,
+incli6_0: 92,
+ir0_1: 1300,
+ir1_1: 1280,
+ir2_1: 1281,
+ir3_1: 1282,
+ir4_1: 1283,
+ir5_1: 1284,
+ir6_1: 1272,
+ir7_1: 1273,
+ixh0_1: 365,
+ixh1_1: 364,
+ixh2_1: 363,
+ixh3_1: 362,
+ixh4_1: 361,
+ixh5_1: 360,
+ixh6_1: 359,
+ixh7_1: 358,
+ixl0_1: 373,
+ixl1_1: 372,
+ixl2_1: 371,
+ixl3_1: 370,
+ixl4_1: 369,
+ixl5_1: 368,
+ixl6_1: 367,
+ixl7_1: 366,
+pch0_1: 197,
+pch1_1: 193,
+pch2_1: 196,
+pch3_1: 192,
+pch4_1: 195,
+pch5_1: 191,
+pch6_1: 194,
+pch7_1: 190,
+pcl0_1: 153,
+pcl1_1: 141,
+pcl2_1: 142,
+pcl3_1: 145,
+pcl4_1: 146,
+pcl5_1: 149,
+pcl6_1: 150,
+pcl7_1: 155,
+reset_0: 1462,
+sph0_1: 303,
+sph1_1: 302,
+sph2_1: 301,
+sph3_1: 300,
+sph4_1: 299,
+sph5_1: 298,
+sph6_1: 297,
+sph7_1: 296,
+spl0_1: 295,
+spl1_1: 294,
+spl2_1: 293,
+spl3_1: 292,
+spl4_1: 291,
+spl5_1: 290,
+spl6_1: 289,
+spl7_1: 288,
+tmp0_1: 284,
+tmp1_1: 283,
+tmp2_1: 282,
+tmp3_1: 281,
+tmp4_1: 280,
+tmp5_1: 279,
+tmp6_1: 278,
+tmp7_1: 254,
+vma_0: 1498,
+phi2_1: 478,
+"#abh0_0": 1070,
+"#abh0_1": 277,
+"#abh1_0": 818,
+"#abh1_1": 271,
+"#abh2_0": 810,
+"#abh2_1": 276,
+"#abh3_0": 812,
+"#abh3_1": 270,
+"#abh4_0": 816,
+"#abh4_1": 275,
+"#abh5_0": 808,
+"#abh5_1": 269,
+"#abh6_0": 814,
+"#abh6_1": 272,
+"#abh7_0": 572,
+"#abh7_1": 268,
+"#abl0_0": 76,
+"#abl10_0": 500,
+"#abl11_0": 501,
+"#abl12_0": 498,
+"#abl13_0": 499,
+"#abl14_0": 496,
+"#abl15_0": 497,
+"#abl16_0": 494,
+"#abl17_0": 495,
+"#abl1_0": 73,
+"#abl2_0": 70,
+"#abl3_0": 67,
+"#abl4_0": 64,
+"#abl5_0": 61,
+"#abl6_0": 58,
+"#abl7_0": 55,
+"#acca0_0": 1710,
+"#acca1_0": 1718,
+"#acca2_0": 1711,
+"#acca3_0": 1719,
+"#acca4_0": 1723,
+"#acca5_0": 1727,
+"#acca6_0": 1731,
+"#acca7_0": 1783,
+"#accb0_0": 1704,
+"#accb1_0": 1712,
+"#accb2_0": 1705,
+"#accb3_0": 1713,
+"#accb4_0": 1720,
+"#accb5_0": 1724,
+"#accb6_0": 1728,
+"#accb7_0": 1732,
+"#addb0_0": 492,
+"#addb1_0": 493,
+"#addb2_0": 502,
+"#addb3_0": 503,
+"#addb4_0": 504,
+"#addb5_0": 505,
+"#addb6_0": 522,
+"#addb7_0": 523,
+"#addc01": 591,
+"#addc12": 588,
+"#addc23": 587,
+"#addc45": 583,
+"#addc56": 580,
+"#addc67": 579,
+"#ahd0": 264,
+"#ahd1": 274,
+"#ahd2": 263,
+"#ahd3": 273,
+"#ahd4": 262,
+"#ahd5": 261,
+"#ahd6": 260,
+"#ahd7": 1780,
+"#ald0": 1672,
+"#ald1": 1673,
+"#ald2": 1654,
+"#ald3": 1668,
+"#ald4": 1659,
+"#ald5": 1661,
+"#ald6": 1660,
+"#ald7": 1662,
+"#ccr/db": 287,
+"#d0_0": 607,
+"#d1_0": 597,
+"#d2_0": 596,
+"#d3_0": 399,
+"#d4_0": 404,
+"#d5_0": 394,
+"#d6_0": 388,
+"#d7_0": 661,
+"#db0_0": 75,
+"#db0_1": 519,
+"#db1_0": 72,
+"#db1_1": 518,
+"#db2_0": 69,
+"#db2_1": 515,
+"#db3_0": 66,
+"#db3_1": 514,
+"#db4_0": 63,
+"#db4_1": 511,
+"#db5_0": 60,
+"#db5_1": 510,
+"#db6_0": 57,
+"#db6_1": 507,
+"#db7_0": 54,
+"#db7_1": 506,
+"#dbi0_0": 611,
+"#dbi1_0": 605,
+"#dbi2_0": 603,
+"#dbi3_0": 403,
+"#dbi4_0": 407,
+"#dbi5_0": 398,
+"#dbi6_0": 391,
+"#dbi7_0": 654,
+// "#decode_0": 1528,  aka  sync
+"#decode_2": 1259,
+"#i0": 1270,
+"#i1": 1197,
+"#i2": 1198,
+"#i3": 1266,
+"#i4": 1199,
+"#i5": 1200,
+"#i6": 1262,
+"#i7": 1260,
+"#inch0_0": 218,
+"#inch1_0": 214,
+"#inch2_0": 217,
+"#inch3_0": 213,
+"#inch4_0": 216,
+"#inch5_0": 212,
+"#inch6_0": 215,
+"#inch7_0": 211,
+"#inchc01": 1758,
+"#inchc12": 1759,
+"#inchc23": 1763,
+"#inchc34": 1764,
+"#inchc45": 1767,
+"#inchc56": 1768,
+"#inchc67": 1779,
+"#inchcin": 186,
+"#inchi0": 247,
+"#inchi1": 250,
+"#inchi2": 246,
+"#inchi3": 249,
+"#inchi4": 244,
+"#inchi5": 248,
+"#inchi6": 241,
+"#incho0": 225,
+"#incho1": 221,
+"#incho2": 224,
+"#incho3": 220,
+"#incho4": 223,
+"#incho5": 219,
+"#incho6": 222,
+"#incho7": 210,
+"#incl0_0": 119,
+"#incl1_0": 115,
+"#incl2_0": 118,
+"#incl3_0": 114,
+"#incl4_0": 117,
+"#incl5_0": 113,
+"#incl6_0": 116,
+"#incl7_0": 96,
+"#inclc01": 1675,
+"#inclc12": 1652,
+"#inclc23": 1676,
+"#inclc34": 1663,
+"#inclc45": 1665,
+"#inclc56": 1664,
+"#inclc67": 1666,
+"#inclcin": 1674,
+"#incli0": 50,
+"#incli1": 46,
+"#incli2": 49,
+"#incli3": 45,
+"#incli4": 48,
+"#incli5": 44,
+"#incli6": 47,
+"#incli7": 43,
+"#inclo0": 104,
+"#inclo1": 100,
+"#inclo2": 103,
+"#inclo3": 99,
+"#inclo4": 102,
+"#inclo5": 98,
+"#inclo6": 101,
+"#inclo7": 97,
+"#ir0_0": 1302,
+"#ir1_0": 1290,
+"#ir2_0": 1296,
+"#ir3_0": 1297,
+"#ir4_0": 1298,
+"#ir5_0": 1299,
+"#ir6_0": 1278,
+"#ir7_0": 1279,
+"#ixh0_0": 1706,
+"#ixh1_0": 1714,
+"#ixh2_0": 1707,
+"#ixh3_0": 1715,
+"#ixh4_0": 1721,
+"#ixh5_0": 1725,
+"#ixh6_0": 1729,
+"#ixh7_0": 1781,
+"#ixl0_0": 1708,
+"#ixl1_0": 1716,
+"#ixl2_0": 1709,
+"#ixl3_0": 1717,
+"#ixl4_0": 1722,
+"#ixl5_0": 1726,
+"#ixl6_0": 1730,
+"#ixl7_0": 1782,
+"#obh0": 1071,
+"#obh1": 819,
+"#obh2": 811,
+"#obh3": 813,
+"#obh4": 817,
+"#obh5": 809,
+"#obh6": 815,
+"#obh7": 574,
+"#pch0_0": 1760,
+"#pch1_0": 1757,
+"#pch2_0": 1761,
+"#pch3_0": 1762,
+"#pch4_0": 1765,
+"#pch5_0": 1766,
+"#pch6_0": 1769,
+"#pch7_0": 1778,
+"#pcl0_0": 1770,
+"#pcl1_0": 1775,
+"#pcl2_0": 1771,
+"#pcl3_0": 1776,
+"#pcl4_0": 1772,
+"#pcl5_0": 1777,
+"#pcl6_0": 1773,
+"#pcl7_0": 1774,
+"#reset_1": 1463,
+"#sph0_0": 1735,
+"#sph1_0": 1738,
+"#sph2_0": 1741,
+"#sph3_0": 1744,
+"#sph4_0": 1747,
+"#sph5_0": 1750,
+"#sph6_0": 1753,
+"#sph7_0": 1756,
+"#spl0_0": 1734,
+"#spl1_0": 1737,
+"#spl2_0": 1740,
+"#spl3_0": 1743,
+"#spl4_0": 1746,
+"#spl5_0": 1749,
+"#spl6_0": 1752,
+"#spl7_0": 1755,
+"#sum0_0": 616,
+"#sum1_0": 632,
+"#sum2_0": 615,
+"#sum3_0": 627,
+"#sum4_0": 614,
+"#sum5_0": 622,
+"#sum6_0": 613,
+"#sum7_0": 617,
+"#sumo0": 634,
+"#sumo1": 633,
+"#sumo2": 629,
+"#sumo3": 628,
+"#sumo4": 624,
+"#sumo5": 623,
+"#sumo6": 619,
+"#sumo7": 618,
+"#tmp0_0": 1733,
+"#tmp1_0": 1736,
+"#tmp2_0": 1739,
+"#tmp3_0": 1742,
+"#tmp4_0": 1745,
+"#tmp5_0": 1748,
+"#tmp6_0": 1751,
+"#tmp7_0": 1754,
+"#ena": 1646,
+"#enrw": 1168,
+"#flagc_0": 1129,
+"#flagcx": 1128,
+"#flagh_0": 787,
+"#flaghx": 781,
+"#flagi_0": 1576,
+"#flagix": 1006,
+"#flagn_0": 997,
+"#flagnx": 996,
+"#flagv_0": 1103,
+"#flagvx": 1566,
+"#flagz_0": 1579,
+"#flagzx": 1024,
+"#n0n-0": 1250,
+"#n0n-1": 1251,
+"#n0n-2": 1252,
+"#n0n-3": 1253,
+"#n0n-4": 1254,
+"#n0n-5": 1247,
+"#n0n-6": 1243,
+"#n0n-7": 1244,
+"#n0n.2-0": 1249,
+"#n0n.2-1": 1255,
+"#n0n.2-2": 1256,
+"#n0n.2-3": 1257,
+"#n0n.2-4": 1258,
+"#n0n.2-5": 1248,
+"#n0n.2-6": 1241,
+"#n0n.2-7": 1242,
+"#phi2_0": 477,
+"#phi2_2": 576,
+"#qand0": 571,
+"#x0/abh": 979,
+"#x0/abl1": 438,
+"#x0/db0": 127,
+"#x0/db1": 129,
+"#x0/db2": 132,
+"#xab/ix": 456,
+"#xab/sp": 167,
+"#xabl/abl1": 426,
+"#xabl/ald": 82,
+"#xacca/abl1": 428,
+"#xacca/db": 466,
+"#xaccb/abl1": 460,
+"#xaccb/db": 760,
+"#xda/adda": 434,
+"#xdb/acca": 464,
+"#xdb/accb": 430,
+"#xdb/adda": 436,
+"#xdb/ald": 84,
+"#xdb/ixh": 454,
+"#xdb/ixl": 458,
+"#xdb/sph": 739,
+"#xdb/spl": 445,
+"#xdb/tmp": 448,
+"#xinc/ab": 121,
+"#xinc/pc": 701,
+"#xixh/abh": 421,
+"#xixh/abl1": 757,
+"#xixh/db": 424,
+"#xixl/abl1": 462,
+"#xixl/db": 432,
+"#xpc/ab": 123,
+"#xpch/db": 157,
+"#xpcl/db": 125,
+"#xsp/ab": 745,
+"#xsph/db": 452,
+"#xspl/db": 738,
+"#xsr/adda": 468,
+"#xtmp/abh": 443,
+"#xtmp/db": 450,
+"#xndb/adda": 471,
+"0/abh": 181,
+"0/abl1": 316,
+"0/db0": 136,
+"0/db1": 135,
+"0/db2": 134,
+"a0-high": 13,
+"a0-low": 21,
+"a1-high": 16,
+"a1-low": 24,
+"a10-high": 803,
+"a10-low": 39,
+"a11-high": 804,
+"a11-low": 41,
+"a12-high": 806,
+"a12-low": 689,
+"a13-high": 802,
+"a13-low": 687,
+"a14-high": 805,
+"a14-low": 690,
+"a15-high": 801,
+"a15-low": 688,
+"a2-high": 14,
+"a2-low": 22,
+"a3-high": 17,
+"a3-low": 25,
+"a4-high": 15,
+"a4-low": 23,
+"a5-high": 18,
+"a5-low": 26,
+"a6-high": 19,
+"a6-low": 20,
+"a7-high": 37,
+"a7-low": 36,
+"a8-high": 1072,
+"a8-low": 38,
+"a9-high": 807,
+"a9-low": 40,
+"ab/ix": 329,
+"ab/ob": 1647,
+"ab/sp": 171,
+"abh/ahd": 176,
+"abl/abl1": 326,
+"abl/ald": 6,
+"acca/abl1": 325,
+"acca/db": 314,
+"accb/abl1": 318,
+"accb/db": 324,
+"ba-high": 1237,
+"ba-low": 1227,
+"d0-high": 681,
+"d0-low": 684,
+"d1-high": 682,
+"d1-low": 685,
+"d2-high": 674,
+"d2-low": 679,
+"d3-high": 675,
+"d3-low": 680,
+"d4-high": 666,
+"d4-low": 671,
+"d5-high": 667,
+"d5-low": 672,
+"d6-high": 662,
+"d6-low": 665,
+"d7-high": 653,
+"d7-low": 652,
+"da/adda": 418,
+"db/acca": 315,
+"db/accb": 323,
+"db/adda": 417,
+"db/ald": 7,
+"db/ixh": 285,
+"db/ixl": 320,
+"db/sph": 180,
+"db/spl": 177,
+"db/tmp": 174,
+"dbi0-fb": 612,
+"dbi1-fb": 600,
+"dbi2-fb": 606,
+"dbi3-fb": 401,
+"dbi4-fb": 408,
+"dbi5-fb": 396,
+"dbi6-fb": 392,
+"dbi7-fb": 651,
+"inc/ab": 140,
+"inc/pc": 138,
+"ixh/abh": 327,
+"ixh/abl1": 319,
+"ixh/db": 328,
+"ixl/abl1": 317,
+"ixl/db": 322,
+"pch/abh": 161,
+"pch/db": 162,
+"pcl/abl": 139,
+"pcl/db": 137,
+"rw-high": 1306,
+"rw-low": 1307,
+"sph/abh": 286,
+"sph/db": 172,
+"spl/abl": 178,
+"spl/db": 175,
+"sr/adda": 416,
+"sum/db": 532,
+"tmp/abh": 179,
+"tmp/db": 173,
+"vma-high": 1500,
+"vma-low": 1499,
+"flag0/db1": 321,
+"flag0/db2": 375,
+"flag0/db3": 376,
+"flag0/db4": 309,
+"flag0/db5": 308,
+"n1n-0": 1303,
+"n1n-1": 1291,
+"n1n-2": 1294,
+"n1n-3": 1292,
+"n1n-4": 1295,
+"n1n-5": 1293,
+"n1n-6": 1275,
+"ndb/adda": 415,
+"nin-7": 1276,
+}

chip-6800/support.js

@@ -0,0 +1,457 @@
+// chip-specific support functions
+//
+// may override function definitions made previously
+
+chipname='6800';
+
+grChipSize=7000;
+
+ngnd = nodenames['gnd'];
+npwr = nodenames['vcc'];
+
+nodenamereset = 'reset';
+
+presetLogLists=[
+                ['cycle','phi1','phi2'],
+                ['ab','db','rw','vma','Fetch','pc','acca','accb','ix','sp','p'],
+                ['ir','sync','Execute'],    // instruction fetch and execution control
+                ['dbi','dbo','tmp'],        // internal state
+                ['idb','abh','abl','ablx'], // internal busses
+                ['irq','nmi',nodenamereset,'tsc','dbe','halt','ba'], // other pins
+        ];
+
+function setupTransistors(){
+	for(i in transdefs){
+		var tdef = transdefs[i];
+		var name = tdef[0];
+		var gate = tdef[1];
+		var c1 = tdef[2];
+		var c2 = tdef[3];
+		var bb = tdef[4];
+		if(tdef[6])
+			// just ignore all the 'weak' transistors for now
+			continue;
+		if(c1==ngnd) {c1=c2;c2=ngnd;}
+		if(c1==npwr) {c1=c2;c2=npwr;}
+		var trans = {name: name, on: false, gate: gate, c1: c1, c2: c2, bb: bb};
+		nodes[gate].gates.push(trans);
+		nodes[c1].c1c2s.push(trans);
+		nodes[c2].c1c2s.push(trans);
+		transistors[name] = trans;
+	}
+}
+
+// simulate a single clock phase with no update to graphics or trace
+function halfStep(){
+	var clk = isNodeHigh(nodenames['phi2']);
+	eval(clockTriggers[cycle]);
+	if (clk) {setLow('phi2'); setLow('dbe'); setHigh('phi1'); handleBusRead(); }
+	else {setHigh('phi1'); setLow('phi1'); setHigh('phi2'); setHigh('dbe'); handleBusWrite();}
+}
+
+function goUntilSyncOrWrite(){
+	halfStep();
+	cycle++;
+	while(
+		!isNodeHigh(nodenames['phi2']) ||
+		( !isNodeHigh(nodenames['sync']) && isNodeHigh(nodenames['rw']) )
+	) {
+		halfStep();
+		cycle++;
+	}
+	chipStatus();
+}
+
+function initChip(){
+        var start = now();
+	for(var nn in nodes) {
+		nodes[nn].state = false;
+		nodes[nn].float = true;
+	}
+
+	nodes[ngnd].state = false;
+	nodes[ngnd].float = false;
+	nodes[npwr].state = true;
+	nodes[npwr].float = false;
+	for(var tn in transistors) transistors[tn].on = false;
+	setLow(nodenamereset);
+	setHigh('phi1'); setLow('phi2'); setLow('dbe');
+	setHigh('dbe'); setLow('tsc'); setHigh('halt');
+	setHigh('irq'); setHigh('nmi');
+	recalcNodeList(allNodes()); 
+	for(var i=0;i<8;i++){
+		setLow('phi1');
+		setHigh('phi2'); setHigh('dbe');
+		setLow('phi2'); setLow('dbe');
+		setHigh('phi1');
+	}
+	setHigh(nodenamereset);
+	for(var i=0;i<18;i++){halfStep();} // avoid updating graphics and trace buffer before user code
+	refresh();
+	cycle = 0;
+	trace = Array();
+	if(typeof expertMode != "undefined")
+		updateLogList();
+	chipStatus();
+	if(ctrace)console.log('initChip done after', now()-start);
+}
+
+function handleBusRead(){
+	if(isNodeHigh(nodenames['rw'])){
+		var a = readAddressBus();
+		var d = eval(readTriggers[a]);
+		if(d == undefined)
+			d = mRead(readAddressBus());
+		if(isNodeHigh(nodenames['sync']))
+			eval(fetchTriggers[d]);
+		writeDataBus(d);
+	}
+}
+
+function readAccA(){return readBits('acca', 8);}
+function readAccB(){return readBits('accb', 8);}
+function readIX(){return (readBits('ixh', 8)<<8) + readBits('ixl', 8);}
+function readSP(){return (readBits('sph', 8)<<8) + readBits('spl', 8);}
+function readPstring(){
+   var result;
+   result = '&#8209' +  // non-breaking hyphen
+            '&#8209' +  // non-breaking hyphen
+            (isNodeHigh(nodenames['flagh'])?'H':'h') +
+            (isNodeHigh(nodenames['flagi'])?'I':'i') +
+            (isNodeHigh(nodenames['flagn'])?'N':'n') +
+            (isNodeHigh(nodenames['flagz'])?'Z':'z') +
+            (isNodeHigh(nodenames['flagv'])?'V':'v') +
+            (isNodeHigh(nodenames['flagc'])?'C':'c');
+   return result;
+}
+
+function busToString(busname){
+	// takes a signal name or prefix
+	// returns an appropriate string representation
+	// some 'signal names' are CPU-specific aliases to user-friendly string output
+	if(busname=='cycle')
+		return cycle>>1;
+	if(busname=='pc')
+		return busToHex('pch') + busToHex('pcl');
+	if(busname=='sp')
+		return busToHex('sph') + busToHex('spl');
+	if(busname=='ix')
+		return busToHex('ixh') + busToHex('ixl');
+	if(busname=='p')
+		return readPstring();
+	if(busname=='State')
+		return listActiveTCStates();
+	if(busname=='Execute')
+		return disassemblytoHTML(readBits('ir',8));
+	if(busname=='Fetch')
+		return isNodeHigh(nodenames['sync'])?disassemblytoHTML(readDataBus()):"";
+	if(busname=='plaOutputs')
+		// PLA outputs are mostly ^op- but some have a prefix too
+		//    - we'll allow the x and xx prefix but ignore the #
+		return listActiveSignals('^([x]?x-)?op-');
+	if(busname=='DPControl')
+		return listActiveSignals('^dpc[0-9]+_');
+	if(busname[0]=="-"){
+		// invert the value of the bus for display
+		var value=busToHex(busname.slice(1))
+		if(typeof value != "undefined")
+			return value.replace(/./g,function(x){return (15-parseInt(x,16)).toString(16)});
+		else
+			return undefined;;
+	} else {
+		return busToHex(busname);
+	}
+}
+
+function chipStatus(){
+	var ab = readAddressBus();
+	var machine1 =
+	        ' halfcyc:' + cycle +
+	        ' phi0:' + readBit('phi2') +
+                ' AB:' + hexWord(ab) +
+	        ' D:' + hexByte(readDataBus()) +
+	        ' RnW:' + readBit('rw') +
+	        ' VMA:' + readBit('vma');
+	var machine2 =
+	        ' PC:' + hexWord(readPC()) +
+	        ' A:' + hexByte(readAccA()) +
+	        ' B:' + hexByte(readAccB()) +
+	        ' IX:' + hexWord(readIX()) +
+	        ' SP:' + hexWord(readSP()) +
+	        ' ' + readPstring();
+	var machine3 = 
+		'Hz: ' + estimatedHz().toFixed(1);
+	if(typeof expertMode != "undefined") {
+		machine3 += ' Exec: ' + busToString('Execute'); // no T-state info for 6800 yet
+		if(isNodeHigh(nodenames['sync']))
+			machine3 += ' (Fetch: ' + busToString('Fetch') + ')';
+		if(goldenChecksum != undefined)
+			machine3 += " Chk:" + traceChecksum + ((traceChecksum==goldenChecksum)?" OK":" no match");
+	}
+
+	setStatus(machine1, machine2, machine3);
+	if (loglevel>0) {
+		updateLogbox(logThese);
+	}
+	selectCell(ab);
+}
+
+// javascript derived from http://segher.ircgeeks.net/6800/OPS
+var disassembly={
+0x00: "!",
+0x01: "nop",
+0x02: "!",
+0x03: "!",
+0x04: "!",
+0x05: "!",
+0x06: "tap",
+0x07: "tpa",
+0x10: "sba",
+0x11: "cba",
+0x12: "!",
+0x13: "!",
+0x14: "!nba",
+0x15: "!",
+0x16: "tab",
+0x17: "tba",
+0x20: "bra N",
+0x21: "!",
+0x22: "bhi N",
+0x23: "bls N",
+0x24: "bcc N",
+0x25: "bcs N",
+0x26: "bne N",
+0x27: "beq N",
+0x30: "tsx",
+0x31: "ins",
+0x32: "pul a",
+0x33: "pul b",
+0x34: "des",
+0x35: "txs",
+0x36: "psh a",
+0x37: "psh b",
+0x40: "neg a",
+0x41: "!",
+0x42: "!",
+0x43: "com a",
+0x44: "lsr a",
+0x45: "!",
+0x46: "ror a",
+0x47: "asr a",
+0x50: "neg b",
+0x51: "!",
+0x52: "!",
+0x53: "com b",
+0x54: "lsr b",
+0x55: "!",
+0x56: "ror b",
+0x57: "asr b",
+0x60: "neg Nx",
+0x61: "!",
+0x62: "!",
+0x63: "com Nx",
+0x64: "lsr Nx",
+0x65: "!",
+0x66: "ror Nx",
+0x67: "asr Nx",
+0x70: "neg NN",
+0x71: "!",
+0x72: "!",
+0x73: "com NN",
+0x74: "lsr NN",
+0x75: "!",
+0x76: "ror NN",
+0x77: "asr NN",
+0x80: "sub a #",
+0x81: "cmp a #",
+0x82: "sbc a #",
+0x83: "!",
+0x84: "and a #",
+0x85: "bit a #",
+0x86: "lda a #",
+0x87: "!",
+0x90: "sub a N",
+0x91: "cmp a N",
+0x92: "sbc a N",
+0x93: "!",
+0x94: "and a N",
+0x95: "bit a N",
+0x96: "lda a N",
+0x97: "sta a N",
+0xa0: "sub a Nx",
+0xa1: "cmp a Nx",
+0xa2: "sbc a Nx",
+0xa3: "!",
+0xa4: "and a Nx",
+0xa5: "bit a Nx",
+0xa6: "lda a Nx",
+0xa7: "sta a Nx",
+0xb0: "sub a NN",
+0xb1: "cmp a NN",
+0xb2: "sbc a NN",
+0xb3: "!",
+0xb4: "and a NN",
+0xb5: "bit a NN",
+0xb6: "lda a NN",
+0xb7: "sta a NN",
+0xc0: "sub b #",
+0xc1: "cmp b #",
+0xc2: "sbc b #",
+0xc3: "!",
+0xc4: "and b #",
+0xc5: "bit b #",
+0xc6: "lda b #",
+0xc7: "!",
+0xd0: "sub b N",
+0xd1: "cmp b N",
+0xd2: "sbc b N",
+0xd3: "!",
+0xd4: "and b N",
+0xd5: "bit b N",
+0xd6: "lda b N",
+0xd7: "sta b N",
+0xe0: "sub b Nx",
+0xe1: "cmp b Nx",
+0xe2: "sbc b Nx",
+0xe3: "!",
+0xe4: "and b Nx",
+0xe5: "bit b Nx",
+0xe6: "lda b Nx",
+0xe7: "sta b Nx",
+0xf0: "sub b NN",
+0xf1: "cmp b NN",
+0xf2: "sbc b NN",
+0xf3: "!",
+0xf4: "and b NN",
+0xf5: "bit b NN",
+0xf6: "lda b NN",
+0xf7: "sta b NN",
+0x08: "inx",
+0x09: "dex",
+0x0a: "clv",
+0x0b: "sev",
+0x0c: "clc",
+0x0d: "sec",
+0x0e: "cli",
+0x0f: "sei",
+0x18: "!",
+0x19: "daa",
+0x1a: "!",
+0x1b: "aba",
+0x1c: "!",
+0x1d: "!",
+0x1e: "!",
+0x1f: "!",
+0x28: "bvc N",
+0x29: "bvs N",
+0x2a: "bpl N",
+0x2b: "bmi N",
+0x2c: "bge N",
+0x2d: "blt N",
+0x2e: "bgt N",
+0x2f: "ble N",
+0x38: "!",
+0x39: "rts",
+0x3a: "!",
+0x3b: "rti",
+0x3c: "!",
+0x3d: "!",
+0x3e: "wai",
+0x3f: "swi",
+0x48: "asl a",
+0x49: "rol a",
+0x4a: "dec a",
+0x4b: "!",
+0x4c: "inc a",
+0x4d: "tst a",
+0x4e: "!",
+0x4f: "clr a",
+0x58: "asl b",
+0x59: "rol b",
+0x5a: "dec b",
+0x5b: "!",
+0x5c: "inc b",
+0x5d: "tst b",
+0x5e: "!",
+0x5f: "clr b",
+0x68: "asl Nx",
+0x69: "rol Nx",
+0x6a: "dec Nx",
+0x6b: "!",
+0x6c: "inc Nx",
+0x6d: "tst Nx",
+0x6e: "jmp Nx",
+0x6f: "clr Nx",
+0x78: "asl NN",
+0x79: "rol NN",
+0x7a: "dec NN",
+0x7b: "!",
+0x7c: "inc NN",
+0x7d: "tst NN",
+0x7e: "jmp NN",
+0x7f: "clr NN",
+0x88: "eor a #",
+0x89: "adc a #",
+0x8a: "ora a #",
+0x8b: "add a #",
+0x8c: "cpx ##",
+0x8d: "bsr N",
+0x8e: "lds ##",
+0x8f: "!",
+0x98: "eor a N",
+0x99: "adc a N",
+0x9a: "ora a N",
+0x9b: "add a N",
+0x9c: "cpx N",
+0x9d: "!hcf",
+0x9e: "lds N",
+0x9f: "sts N",
+0xa8: "eor a Nx",
+0xa9: "adc a Nx",
+0xaa: "ora a Nx",
+0xab: "add a Nx",
+0xac: "cpx Nx",
+0xad: "jsr Nx",
+0xae: "lds Nx",
+0xaf: "sts Nx",
+0xb8: "eor a NN",
+0xb9: "adc a NN",
+0xba: "ora a NN",
+0xbb: "add a NN",
+0xbc: "cpx NN",
+0xbd: "jsr NN",
+0xbe: "lds NN",
+0xbf: "sts NN",
+0xc8: "eor b #",
+0xc9: "adc b #",
+0xca: "ora b #",
+0xcb: "add b #",
+0xcc: "!",
+0xcd: "!",
+0xce: "ldx ##",
+0xcf: "!",
+0xd8: "eor b N",
+0xd9: "adc b N",
+0xda: "ora b N",
+0xdb: "add b N",
+0xdc: "!",
+0xdd: "!hcf",
+0xde: "ldx N",
+0xdf: "stx N",
+0xe8: "eor b Nx",
+0xe9: "adc b Nx",
+0xea: "ora b Nx",
+0xeb: "add b Nx",
+0xec: "!",
+0xed: "!",
+0xee: "ldx Nx",
+0xef: "stx Nx",
+0xf8: "eor b NN",
+0xf9: "adc b NN",
+0xfa: "ora b NN",
+0xfb: "add b NN",
+0xfc: "!",
+0xfd: "!",
+0xfe: "ldx NN",
+0xff: "stx NN",
+};

chip-6800/testprogram.js

@@ -0,0 +1,25 @@
+// This file testprogram.js can be substituted by one of several tests
+testprogramAddress=0x0000;
+
+// we want to auto-clear the console if any output is sent by the program
+var consoleboxStream="";
+
+// for opcodes, see ftp://ftp.comlab.ox.ac.uk/pub/Cards/txt/6800.txt
+
+testprogram = [
+  0x01,              // NOP
+  0x01,              // NOP
+  0x01,              // NOP
+  0xce, 0x43, 0x21,  // LDX #4321
+  0x35,              // TXS
+  0xc6, 0x00,        // LDAA #$00
+  0xbd, 0x00, 0x10,  // JSR $0010
+  0x7e, 0x00, 0x02,  // JMP $0002
+  0x01,              // NOP
+  0x08,              // INX
+  0x5a,              // DECB
+  0x7c, 0x00, 0x0f,  // INC $0F
+  0x0d,              // SEC
+  0xc9, 0x02,        // ADCA #$02
+  0x39,              // RTS
+]

expert-6800.html

@@ -0,0 +1,153 @@
+<!DOCTYPE html>
+
+<head>
+<title>Visual 6800 in JavaScript</title>
+<style type="text/css">@import "expert.css";</style>
+<script src="chip-6800/segdefs.js"></script>
+<script src="chip-6800/transdefs.js"></script>
+<script src="chip-6800/nodenames.js"></script>
+<script src="wires.js"></script>
+<script src="expertWires.js"></script>
+<script src="chipsim.js"></script>
+<script src="memtable.js"></script>
+<script src="macros.js"></script>
+<script src="chip-6800/support.js"></script>
+<script src="chip-6800/testprogram.js"></script>
+<script src="3rdparty/jquery-1.3.2.min.js"></script>
+<script src="3rdparty/jquery.cookie.js"></script>
+<script src="3rdparty/splitter.js"></script>
+
+<script type="text/javascript">
+function handleOnload() {
+	/MSIE (\d+\.\d+);/.test(navigator.appVersion);
+	IEVersion=Number(RegExp.$1);
+	if((navigator.appName == 'Microsoft Internet Explorer') && (IEVersion<9)){
+		document.getElementById('browsertrouble').innerHTML=
+			'<p>Sorry, '+navigator.appName+' not supported - showing you a picture instead!</p>';
+		document.getElementById('frame').innerHTML='<a href="browsertrouble.html"><img src="images/jssim2.png" style="border:10px"></a>';
+	}else{
+		setTimeout(setup,200);
+	}
+};
+
+// initialise splitter (built on jquery)
+$().ready(function(){
+	$("#frame").splitter({
+		type: "v",
+		outline: true,
+		minLeft: 20,
+		sizeLeft: 810,
+		resizeToWidth: true,
+		anchorToWindow: true,
+	});
+	$("#rightcolumn").splitter({
+		type: "h",
+		outline: true,
+		sizeBottom: 180,
+		minTop: 100,
+	});
+});
+</script>
+
+</head>
+
+<body onload="handleOnload();">
+<span id="plain">
+<a href="http://www.visual6502.org/faq.html">FAQ</a>&nbsp;
+<a href="http://blog.visual6502.org">Blog</a>&nbsp;
+<a href="http://www.visual6502.org/links.html">Links</a>&nbsp;
+<a href="http://github.com/trebonian/visual6502">Source</a>&nbsp;
+<a href="ftp://ftp.comlab.ox.ac.uk/pub/Cards/txt/6800.txt">6800 instruction card</a>&nbsp;
+<a href="http://www.sbprojects.com/sbasm/6800.htm#model">programming model</a>&nbsp;
+</span>
+<div class="frame" id="frame">
+<div class="leftcolumn" id="leftcolumn">
+<div id="chipsurround" tabindex="1">
+<div class="chip" id="chip">
+<span id="waiting">Please wait, graphics initialising...</span>
+<canvas class="chip" id="chipbg"></canvas>
+<canvas class="chip" id="overlay"></canvas>
+<canvas class="chip" id="hilite"></canvas>
+<canvas class="chip" id="hitbuffer"></canvas>
+</div>
+</div> <!-- chipsurround -->
+<div class="nochip" id="nochip">
+  <form>
+  <input type="button" value="Show chip layout" onclick="updateChipLayoutVisibility(true)" />
+  </form>
+</div>
+<div id="layoutControlPanel">
+  Use 'z' or '>' to zoom in, 'x' or '<' to zoom out, click to probe signals and drag to pan.
+  <form id="updateShow"> Show:
+  <input type="checkbox" name="1" id="updateShow1" onchange="updateShow(this.name,this.checked)" />(diffusion)
+  <input type="checkbox" name="3" id="updateShow3" onchange="updateShow(this.name,this.checked)" />(grounded diffusion)
+  <input type="checkbox" name="4" id="updateShow4" onchange="updateShow(this.name,this.checked)" />(powered diffusion)
+  <input type="checkbox" name="5" id="updateShow5" onchange="updateShow(this.name,this.checked)" />(polysilicon)
+  <input type="checkbox" name="0" id="updateShow0" onchange="updateShow(this.name,this.checked)" />(metal)
+  <input type="checkbox" name="2" id="updateShow2" onchange="updateShow(this.name,this.checked)" />(protection)
+  </form>
+  <form action="javascript:hiliteNodeList();">
+  <input type="button" value="Find:" onclick="hiliteNodeList();" />
+  <input type="text" id="HighlightThese" name="HighlightThese" value="" />
+  <input type="button" value="Clear Highlighting" onclick="clearHighlight();" />
+  <span class="animatebox">
+    Animate during simulation:
+    <input type="checkbox" id="animateModeCheckbox" onchange="updateChipLayoutAnimation(this.checked)" 
+    /></span>
+  </form>
+  <form>
+  <input type="button" value="Hide Chip Layout" onclick="updateChipLayoutVisibility(false)" />
+  <a href="" id="linkHere" >Link to this location</a>
+  </form>
+</div>
+</div> <!-- closing leftcolumn -->
+<div class="rightcolumn" id="rightcolumn">
+<div id="righttopdiv">
+<div class = "buttons">
+  <div class="twobuttons">
+    <a href ="javascript:stopChip()" id="stop"><img class="navstop" src="images/stop.png" title="stop"></a>
+    <a href ="javascript:runChip()"  id="start"><img class="navplay" src="images/play.png" title="run"></a>
+  </div>
+  <div class="morebuttons">
+    <a href ="javascript:resetChip()"><img class="navbutton" src="images/up.png" title="reset"></a>
+    <a href ="javascript:stepBack()"><img class="navbutton" src="images/prev.png" title="back"></a>
+    <a href ="javascript:stepForward()"><img class="navbutton" src="images/next.png" title="forward"></a>
+    <a href ="javascript:goUntilSyncOrWrite()"><img class="navbutton" src="images/singlestep.png" title="step"></a>
+    <a href ="javascript:goFor()"><img class="navbutton" src="images/fastforward.png" title="fastforward"></a>
+  </div>
+  <div style="float:right;">
+    <a href="http://visual6502.org/wiki/index.php?title=JssimUserHelp" target="_blank">User Guide</a>
+    &nbsp;
+  </div>
+</div>  <!-- buttons -->
+<div class="status" id="status"><p>x: 0<br>y: 0</p>
+</div> <!-- status -->
+
+   <div id="memtablediv">
+	<table class="memtable" id="memtable" tabindex="2"></table>
+   </div>
+</div> <!-- righttopdiv -->
+
+   <div id="tracingdiv">
+        <textarea id="consolebox">
+click here and type if your program handles input
+        </textarea>
+	<div id="expertControlPanel" tabindex="3">
+	  <form action="javascript:updateLogList()">
+	  <input type="button" value="Trace more" onclick="updateLoglevel(++loglevel)" />
+	  <input type="button" value="Trace less" onclick="updateLoglevel(--loglevel)" />
+	  <input type="button" value="Trace these too:" onclick="updateLogList()" />
+            <input type="text" id="LogThese" name="LogThese" value="" />
+	  <input type="button" value="Log Up/Down" onclick="updateLogDirection();" />
+	  <input type="button" value="Clear Log" onclick="updateLoglevel(loglevel)" />
+	  </form>
+	  <br />
+	</div>
+	<div id="logstreamscroller">
+	       <table class="logstream" id="logstream"></table>
+	</div>
+   </div>
+</div> <!-- closing rightcolumn -->
+</div> <!-- closing 'frame' div -->
+</body>
+</html>

expertWires.js

@@ -96,7 +96,7 @@ function setup_part3(){
 		// which saves a lot of memory and allows us to run on small systems
 		updateChipLayoutVisibility(true);
 	}
-	setStatus('resetting 6502...');
+	setStatus('resetting ' + chipname + '...');
 	setTimeout(setup_part4, 0);
 }
 
@@ -195,17 +195,25 @@ function setupParams(){
 		} else
 		// setup input pin events, breakpoints, watchpoints
 		if(name=="reset0" && parseInt(value)!=NaN){
-			clockTriggers[value]="setLow('res');";
+			clockTriggers[value]=[clockTriggers[value],"setLow(nodenamereset);"].join("");
 		} else if(name=="reset1" && parseInt(value)!=NaN){
-			clockTriggers[value]="setHigh('res');";
+			clockTriggers[value]=[clockTriggers[value],"setHigh(nodenamereset);"].join("");
 		} else if(name=="irq0" && parseInt(value)!=NaN){
-			clockTriggers[value]="setLow('irq');";
+			clockTriggers[value]=[clockTriggers[value],"setLow('irq');"].join("");
 		} else if(name=="irq1" && parseInt(value)!=NaN){
-			clockTriggers[value]="setHigh('irq');";
+			clockTriggers[value]=[clockTriggers[value],"setHigh('irq');"].join("");
 		} else if(name=="nmi0" && parseInt(value)!=NaN){
-			clockTriggers[value]="setLow('nmi');";
+			clockTriggers[value]=[clockTriggers[value],"setLow('nmi');"].join("");
 		} else if(name=="nmi1" && parseInt(value)!=NaN){
-			clockTriggers[value]="setHigh('nmi');";
+			clockTriggers[value]=[clockTriggers[value],"setHigh('nmi');"].join("");
+		} else if(name=="rdy0" && parseInt(value)!=NaN){
+			clockTriggers[value]=[clockTriggers[value],"setLow('rdy');"].join("");
+		} else if(name=="rdy1" && parseInt(value)!=NaN){
+			clockTriggers[value]=[clockTriggers[value],"setHigh('rdy');"].join("");
+		} else if(name=="time" && parseInt(value)!=NaN){
+			eventTime=value;
+		} else if(name=="databus" && parseInt(value)!=NaN){
+			clockTriggers[eventTime]=[clockTriggers[eventTime],"writeDataBus(0x"+value+");"].join("");
 		} else
 		// run a test program, and optionally check against a golden checksum
 		if(name=="steps" && parseInt(value)!=NaN){

macros.js

@@ -26,6 +26,8 @@ var trace = Array();
 var logstream = Array();
 var running = false;
 var logThese=[];
+var chipname='6502';
+var nodenamereset='res';
 var presetLogLists=[
 		['cycle'],
 		['ab','db','rw','Fetch','pc','a','x','y','s','p'],
@@ -35,7 +37,7 @@ var presetLogLists=[
 		['alucin','alua','alub','alucout','aluvout','dasb'],
 		['plaOutputs','DPControl'],
 		['idb','dor'],
-		['irq','nmi','res'],
+		['irq','nmi',nodenamereset],
 	];
 
 function loadProgram(){
@@ -147,13 +149,13 @@ function initChip(){
 	nodes[npwr].state = true;
 	nodes[npwr].float = false;
 	for(var tn in transistors) transistors[tn].on = false;
-	setLow('res');
+	setLow(nodenamereset);
 	setLow('clk0');
 	setHigh('rdy'); setLow('so');
 	setHigh('irq'); setHigh('nmi');
 	recalcNodeList(allNodes()); 
 	for(var i=0;i<8;i++){setHigh('clk0'), setLow('clk0');}
-	setHigh('res');
+	setHigh(nodenamereset);
 	for(var i=0;i<18;i++){halfStep();} // avoid updating graphics and trace buffer before user code
 	refresh();
 	cycle = 0;
@@ -328,9 +330,9 @@ function busToString(busname){
 	if(busname=='State')
 		return listActiveTCStates();
 	if(busname=='Execute')
-		return dis6502toHTML(readBits('ir',8));
+		return disassemblytoHTML(readBits('ir',8));
 	if(busname=='Fetch')
-		return isNodeHigh(nodenames['sync'])?dis6502toHTML(readDataBus()):"";
+		return isNodeHigh(nodenames['sync'])?disassemblytoHTML(readDataBus()):"";
 	if(busname=='plaOutputs')
 		// PLA outputs are mostly ^op- but some have a prefix too
 		//    - we'll allow the x and xx prefix but ignore the #
@@ -424,7 +426,7 @@ function stopChip(){
 
 function resetChip(){
 	stopChip();
-        setStatus('resetting 6502...');                          
+        setStatus('resetting ' + chipname + '...');
 	setTimeout(initChip,0);
 }
 
@@ -623,8 +625,8 @@ function adler32(x){
 }
 
 // sanitised opcode for HTML output
-function dis6502toHTML(byte){
-	var opcode=dis6502[byte];
+function disassemblytoHTML(byte){
+	var opcode=disassembly[byte];
 	if(typeof opcode == "undefined")
 		return "unknown"
 	return opcode.replace(/ /,'&nbsp;');
@@ -632,7 +634,7 @@ function dis6502toHTML(byte){
 
 // opcode lookup for 6502 - not quite a disassembly
 //   javascript derived from Debugger.java by Achim Breidenbach
-var dis6502={
+var disassembly={
 0x00:"BRK",
 0x01:"ORA (zp,X)",
 0x05:"ORA zp",

nodenames.js

@@ -82,7 +82,7 @@ x4: 85,
 x5: 589,
 x6: 448,
 x7: 777,
-pcl0: 1139,     // machine state: program counter low (first storage node)
+pcl0: 1139,     // machine state: program counter low (first storage node output)
 pcl1: 1022,
 pcl2: 655,
 pcl3: 1359,
@@ -90,14 +90,22 @@ pcl4: 900,
 pcl5: 622,
 pcl6: 377,
 pcl7: 1611,
-pclp0: 1227,    // machine state: program counter low (pre-incremented?, second storage node)
-pclp1: 1102,
-pclp2: 1079,
-pclp3: 868,
-pclp4: 39,
-pclp5: 1326,
-pclp6: 731,
-pclp7: 536,
+pclp0: 488,    // machine state: program counter low (pre-incremented?, second storage node)
+pclp1: 976,
+pclp2: 481,
+pclp3: 723,
+pclp4: 208,
+pclp5: 72,
+pclp6: 1458,
+pclp7: 1647,
+"#pclp0": 1227,    // machine state: program counter low (pre-incremented?, inverse second storage node)
+"#pclp1": 1102,
+"#pclp2": 1079,
+"#pclp3": 868,
+"#pclp4": 39,
+"#pclp5": 1326,
+"#pclp6": 731,
+"#pclp7": 536,
 pch0: 1670,     // machine state: program counter high (first storage node)
 pch1: 292,
 pch2: 502,
@@ -106,14 +114,22 @@ pch4: 948,
 pch5: 49,
 pch6: 1551,
 pch7: 205,
-pchp0: 780,     // machine state: program counter high (pre-incremented?, second storage node)
-pchp1: 113,
-pchp2: 114,
-pchp3: 124,
-pchp4: 820,
-pchp5: 33,
-pchp6: 751,
-pchp7: 535,
+pchp0: 1722,     // machine state: program counter high (pre-incremented?, second storage node output)
+pchp1: 209,
+pchp2: 1496,
+pchp3: 141,
+pchp4: 27,
+pchp5: 1301,
+pchp6: 652,
+pchp7: 1206,
+"#pchp0": 780,     // machine state: program counter high (pre-incremented?, inverse second storage node)
+"#pchp1": 113,
+"#pchp2": 114,
+"#pchp3": 124,
+"#pchp4": 820,
+"#pchp5": 33,
+"#pchp6": 751,
+"#pchp7": 535,
                 // machine state: status register (not the storage nodes)
 p0: 32,         // C bit of status register (storage node)
 p1: 627,        // Z bit of status register (storage node)
@@ -311,7 +327,7 @@ abl3: 1250,
 abl4: 1232,
 abl5: 234,
 abl6: 178,
-abl7: 178,
+abl7: 567,
 "#ABL0": 153,   // internal state: address bus low latched data out (storage node, inverted)
 "#ABL1": 107,
 "#ABL2": 707,
@@ -337,7 +353,13 @@ abh7: 489,
 "#ABH6": 289,
 "#ABH7": 429,
 
-notRdy0: 248,   // internal signal: global pipeline control
+"branch-back": 626,           // distinguish forward from backward branches
+"branch-forward.phi1": 1110,  // distinguish forward from backward branches
+"branch-back.phi1": 771,      // distinguish forward from backward branches in IPC logic
+notRdy0: 248,           // internal signal: global pipeline control
+"notRdy0.phi1": 1272,   // delayed pipeline control
+"notRdy0.delay": 770,   // global pipeline control latched by phi1 and then phi2
+"#notRdy0.delay": 559,  // global pipeline control latched by phi1 and then phi2 (storage node)
 Reset0: 67,     // internal signal: retimed reset from pin
 C1x5Reset: 926, // retimed and pipelined reset in progress
 notRnWprepad: 187, // internal signal: to pad, yet to be inverted and retimed
@@ -347,10 +369,7 @@ cp1: 710,       // internal signal: clock phase 1
 cclk: 943,      // unbonded pad: internal non-overlappying phi2
 fetch: 879,     // internal signal
 clearIR: 1077,  // internal signal
-D1x1: 827,      // internal signal: interrupt handler related
 H1x1: 1042,     // internal signal: drive status byte onto databus
-"brk-done": 1382,  // internal signal: interrupt handler related
-INTG: 1350,     // internal signal: interrupt handler related
 
                 // internal signal: pla outputs block 1 (west/left edge of die)
                 // often 130 pla outputs are mentioned - we have 131 here
@@ -510,6 +529,7 @@ INTG: 1350,     // internal signal: interrupt handler related
 
 // internal signals: derived from pla outputs
 "#op-branch-done": 1048,
+"#op-T3-branch": 1708,
 "op-ANDS": 1228,
 "op-EORS": 1689,
 "op-ORS": 522,
@@ -519,17 +539,33 @@ INTG: 1350,     // internal signal: interrupt handler related
 "#WR": 1352,
 "op-rmw": 434,
 "short-circuit-idx-add": 1185,
+"short-circuit-branch-add": 430,
 "#op-set-C": 252,
 
 // internal signals: control signals
 nnT2BR: 967,    // doubly inverted
 BRtaken: 1544,  // aka #TAKEN
 
-// interrupt and vector related
+// internal signals and state: interrupt and vector related
+// segher says:
+//   "P" are the latched external signals.
+//   "G" are the signals that actually trigger the interrupt.
+//   "NMIL" is to do the edge detection -- it's pretty much just a delayed NMIG.
+//   INTG is IRQ and NMI taken together.
+IRQP: 675,
+"#IRQP": 888,
 NMIP: 1032,
+"#NMIP": 297,
+"#NMIG": 264,
+NMIL: 1374,
+RESP: 67,
+RESG: 926,
 VEC0: 1465,
 VEC1: 1481,
 "#VEC": 1134,
+D1x1: 827,         // internal signal: interrupt handler related
+"brk-done": 1382,  // internal signal: interrupt handler related
+INTG: 1350,        // internal signal: interrupt handler related
 
 // internal state: misc pipeline state clocked by cclk (phi2)
 "pipe#VEC": 1431,     // latched #VEC
@@ -538,7 +574,7 @@ pipeT2out: 40,
 pipeT3out: 706,
 pipeT4out: 1373,
 pipeT5out: 940,
-pipeBRtaken: 832,
+pipeIPCrelated: 832,
 pipeUNK01: 1530,
 pipeUNK02: 974,
 pipeUNK03: 1436,
@@ -742,6 +778,8 @@ dpc21_ADDADL: 1015,  // alu to adl
 alurawcout: 808,     // alu raw carry out (no decimal adjust)
 notalucout: 412,     // alu carry out (inverted)
 alucout: 1146,       // alu carry out (latched by phi2)
+"#alucout": 206,
+"##alucout": 465,
 notaluvout: 1308,    // alu overflow out
 aluvout: 938,        // alu overflow out (latched by phi2)
 
@@ -764,7 +802,7 @@ dpc32_PCHADH: 1235,  // drive adh from pch incremented
 dpc33_PCHDB: 247,    // drive idb from pch incremented
 dpc34_PCLC: 1704,    // pch carry in and pcl FF detect?
 dpc35_PCHC: 1334,    // pcl 0x?F detect - half-carry
-dpc36_IPC: 379,      // pcl carry in
+"dpc36_#IPC": 379,   // pcl carry in (inverted)
 dpc37_PCLDB: 283,    // drive idb from pcl incremented
 dpc38_PCLADL: 438,   // drive adl from pcl incremented
 dpc39_PCLPCL: 898,   // load pcl from pcl incremented

wires.js

@@ -29,6 +29,7 @@ var ngnd = nodenames['vss'];
 var npwr = nodenames['vcc'];
 
 var chipLayoutIsVisible = true;  // only modified in expert mode
+var hilited = [];
 
 function setupNodes(){
 	for(var i in segdefs){
@@ -140,6 +141,7 @@ function refresh(){
 	for(i in nodes){
 		if(isNodeHigh(i)) overlayNode(nodes[i].segs);
 	}
+	hiliteNode(hilited);
 }
 
 function overlayNode(w){
@@ -156,6 +158,7 @@ function hiliteNode(n){
 	var ctx = hilite.getContext('2d');
 	ctx.clearRect(0,0,grCanvasSize,grCanvasSize);
 	if(n==-1) return;
+	hilited = n;
 
 	for(var i in n){
 		if(typeof n[i] != "number") {