6 Commits

Author SHA1 Message Date
BigEd
6c138a4f6b add 6800 timing state to tabulation 2011-04-11 14:07:51 +00:00
BigEd
658d40646c add 6800 timing state signals 2011-04-11 13:51:37 +00:00
BigEd
67e15e68c1 fixup comment in transdefs about geometry 2011-04-09 10:33:18 +00:00
BigEd
a316831100 update comments at head of transdefs 2011-04-09 10:12:53 +00:00
ijor
acd7b0310e Edited chip-6800/transdefs.js via GitHub 2011-04-09 17:57:45 +08:00
BigEd
9331be20fe allow tabulations with loglevel 0 (with only additional signals) 2011-04-06 18:13:04 +00:00
4 changed files with 3663 additions and 3596 deletions

View File

@@ -73,6 +73,34 @@ ir7: 1277,
// internal control signals // internal control signals
sync: 1528, // aka #decode_0 sync: 1528, // aka #decode_0
// timing state signals
Ts: 1309,
Ta0: 879,
Td0_0: 981,
"#Te0": 868,
"Te0.2": 866,
Tg0: 12,
Tx0: 850,
Ta1: 838,
Te1_0: 735,
Tg1: 772,
Tx1: 851,
Ta2: 844,
Tg2: 832,
Tx2: 860,
Tg3: 835,
Tr3: 823,
Tg4: 696,
Tr4: 825,
Tg5: 914,
Tr5: 828,
Tg6: 911,
Tr6: 894,
Tr7: 694,
Tg7: 1081,
Tg8: 891,
Tr8: 697,
// many other internal busses registers and signals // many other internal busses registers and signals
abh0: 267, abh0: 267,
abh1: 258, abh1: 258,

View File

@@ -14,8 +14,8 @@ nodenamereset = 'reset';
presetLogLists=[ presetLogLists=[
['cycle',], ['cycle',],
['ab','db','rw','vma','Fetch','pc','acca','accb','ix','sp','p'], ['ab','db','rw','vma','Fetch','pc','acca','accb','ix','sp','p'],
['ir','sync','Execute'], // instruction fetch and execution control ['ir','sync','Execute','State'], // instruction fetch and execution control
['dbi','dbo','tmp'], // internal state ['dbi','dbo','tmp'], // internal register-sized state
['idb','abh','abl','ablx'], // internal busses ['idb','abh','abl','ablx'], // internal busses
['irq','nmi',nodenamereset,'tsc','dbe','halt','ba'], // other pins ['irq','nmi',nodenamereset,'tsc','dbe','halt','ba'], // other pins
]; ];
@@ -125,6 +125,33 @@ function readPstring(){
return result; return result;
} }
// The 6800 state control is something like a branching shift register
// ... but not quite like that
TCStates=[
"Ts",
"Tx0", "Tx1", "Tx2",
"Ta0", "Ta1", "Ta2",
"Td0_0",
"#Te0", "Te1_0",
"Tg0", "Tg1", "Tg2", "Tg3", "Tg4", "Tg5", "Tg6", "Tg7", "Tg8",
"Tr3", "Tr4", "Tr5", "Tr6", "Tr7", "Tr8",
];
function listActiveTCStates() {
var s=[];
for(var i=0;i<TCStates.length;i++){
var t=TCStates[i];
// remove a leading hash, but invert the signal
// in any case, remove any trailing suffix
if(t[0]=="#"){
if(!isNodeHigh(nodenames[t])) s.push(t.slice(1,4));
} else {
if(isNodeHigh(nodenames[t])) s.push(t.slice(0,3));
}
}
return s.join("+");
}
function busToString(busname){ function busToString(busname){
// takes a signal name or prefix // takes a signal name or prefix
// returns an appropriate string representation // returns an appropriate string representation
@@ -190,7 +217,7 @@ function chipStatus(){
} }
setStatus(machine1, machine2, machine3); setStatus(machine1, machine2, machine3);
if (loglevel>0) { if (logThese.length>1) {
updateLogbox(logThese); updateLogbox(logThese);
} }
selectCell(ab); selectCell(ab);

File diff suppressed because it is too large Load Diff

View File

@@ -471,7 +471,7 @@ function chipStatus(){
machine3 += " Chk:" + traceChecksum + ((traceChecksum==goldenChecksum)?" OK":" no match"); machine3 += " Chk:" + traceChecksum + ((traceChecksum==goldenChecksum)?" OK":" no match");
} }
setStatus(machine1, machine2, machine3); setStatus(machine1, machine2, machine3);
if (loglevel>0) { if (logThese.length>1) {
updateLogbox(logThese); updateLogbox(logThese);
} }
selectCell(ab); selectCell(ab);