489 lines
10 KiB
JavaScript
489 lines
10 KiB
JavaScript
// chip-specific support functions
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//
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// may override function definitions made previously
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chipname='6800';
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grChipSize=6600;
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grChipOffsetX=25
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grChipOffsetY=-200;
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ngnd = nodenames['gnd'];
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npwr = nodenames['vcc'];
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nodenamereset = 'reset';
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presetLogLists=[
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['cycle',],
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['ab','db','rw','vma','Fetch','pc','acca','accb','ix','sp','p'],
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['ir','sync','Execute','State'], // instruction fetch and execution control
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['dbi','dbo','tmp','sum','inc'], // internal register-sized state
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['idb','abh','abl','ablx'], // internal datapath busses
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['irq','nmi',nodenamereset,'tsc','dbe','halt','ba'], // other pins
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];
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function setupTransistors(){
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for(i in transdefs){
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var tdef = transdefs[i];
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var name = tdef[0];
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var gate = tdef[1];
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var c1 = tdef[2];
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var c2 = tdef[3];
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var bb = tdef[4];
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if(tdef[6])
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// just ignore all the 'weak' transistors for now
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continue;
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if(c1==ngnd) {c1=c2;c2=ngnd;}
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if(c1==npwr) {c1=c2;c2=npwr;}
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var trans = {name: name, on: false, gate: gate, c1: c1, c2: c2, bb: bb};
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nodes[gate].gates.push(trans);
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nodes[c1].c1c2s.push(trans);
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nodes[c2].c1c2s.push(trans);
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transistors[name] = trans;
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}
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}
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// simulate a single clock phase with no update to graphics or trace
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function halfStep(){
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var clk = isNodeHigh(nodenames['phi2']);
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eval(clockTriggers[cycle]);
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if (clk) {setLow('phi2'); setLow('dbe'); setHigh('phi1'); handleBusRead(); }
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else {setHigh('phi1'); setLow('phi1'); setHigh('phi2'); setHigh('dbe'); handleBusWrite();}
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}
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function goUntilSyncOrWrite(){
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halfStep();
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cycle++;
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while(
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!isNodeHigh(nodenames['phi2']) ||
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( !isNodeHigh(nodenames['sync']) && isNodeHigh(nodenames['rw']) )
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) {
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halfStep();
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cycle++;
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}
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chipStatus();
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}
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function initChip(){
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var start = now();
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for(var nn in nodes) {
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nodes[nn].state = false;
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nodes[nn].float = true;
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}
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nodes[ngnd].state = false;
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nodes[ngnd].float = false;
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nodes[npwr].state = true;
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nodes[npwr].float = false;
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for(var tn in transistors) transistors[tn].on = false;
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setLow(nodenamereset);
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setHigh('phi1'); setLow('phi2'); setLow('dbe');
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setHigh('dbe'); setLow('tsc'); setHigh('halt');
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setHigh('irq'); setHigh('nmi');
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recalcNodeList(allNodes());
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for(var i=0;i<8;i++){
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setLow('phi1');
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setHigh('phi2'); setHigh('dbe');
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setLow('phi2'); setLow('dbe');
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setHigh('phi1');
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}
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setHigh(nodenamereset);
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for(var i=0;i<6;i++){halfStep();} // avoid updating graphics and trace buffer before user code
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refresh();
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cycle = 0;
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trace = Array();
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if(typeof expertMode != "undefined")
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updateLogList();
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chipStatus();
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if(ctrace)console.log('initChip done after', now()-start);
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}
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function handleBusRead(){
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if(isNodeHigh(nodenames['rw'])){
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var a = readAddressBus();
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var d = eval(readTriggers[a]);
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if(d == undefined)
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d = mRead(readAddressBus());
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if(isNodeHigh(nodenames['sync']))
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eval(fetchTriggers[d]);
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writeDataBus(d);
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}
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}
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function readAccA(){return readBits('acca', 8);}
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function readAccB(){return readBits('accb', 8);}
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function readIX(){return (readBits('ixh', 8)<<8) + readBits('ixl', 8);}
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function readSP(){return (readBits('sph', 8)<<8) + readBits('spl', 8);}
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function readPstring(){
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var result;
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result = '‑' + // non-breaking hyphen
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'‑' + // non-breaking hyphen
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(isNodeHigh(nodenames['flagh'])?'H':'h') +
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(isNodeHigh(nodenames['flagi'])?'I':'i') +
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(isNodeHigh(nodenames['flagn'])?'N':'n') +
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(isNodeHigh(nodenames['flagz'])?'Z':'z') +
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(isNodeHigh(nodenames['flagv'])?'V':'v') +
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(isNodeHigh(nodenames['flagc'])?'C':'c');
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return result;
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}
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// The 6800 state control is something like a branching shift register
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// ... but not quite like that
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TCStates=[
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"Ts", "Tf",
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"Tx0", "Tx1", "Tx2",
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"Ta0", "Ta1", "Ta2",
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"Td0_0",
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"#Te0", "Te1_0",
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"Tg0", "Tg1", "Tg2", "Tg3", "Tg4", "Tg5", "Tg6", "Tg7", "Tg8",
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"Tr3", "Tr4", "Tr5", "Tr6", "Tr7", "Tr8",
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];
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function listActiveTCStates() {
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var s=[];
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for(var i=0;i<TCStates.length;i++){
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var t=TCStates[i];
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// remove a leading hash, but invert the signal
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// in any case, remove any trailing suffix
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if(t[0]=="#"){
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if(!isNodeHigh(nodenames[t])) s.push(t.slice(1,4));
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} else {
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if(isNodeHigh(nodenames[t])) s.push(t.slice(0,3));
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}
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}
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return s.join("+");
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}
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function busToString(busname){
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// takes a signal name or prefix
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// returns an appropriate string representation
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// some 'signal names' are CPU-specific aliases to user-friendly string output
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if(busname=='cycle')
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return cycle>>1;
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if(busname=='pc')
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return busToHex('pch') + busToHex('pcl');
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if(busname=='sp')
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return busToHex('sph') + busToHex('spl');
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if(busname=='ix')
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return busToHex('ixh') + busToHex('ixl');
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if(busname=='inc')
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return busToHex('inch') + busToHex('incl');
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if(busname=='p')
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return readPstring();
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if(busname=='State')
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return listActiveTCStates();
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if(busname=='Execute')
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return disassemblytoHTML(readBits('ir',8));
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if(busname=='Fetch')
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return isNodeHigh(nodenames['sync'])?disassemblytoHTML(readDataBus()):"";
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if(busname=='plaOutputs')
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// PLA outputs are mostly ^op- but some have a prefix too
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// - we'll allow the x and xx prefix but ignore the #
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return listActiveSignals('^([x]?x-)?op-');
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if(busname=='DPControl')
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return listActiveSignals('^dpc[0-9]+_');
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if(busname[0]=="-"){
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// invert the value of the bus for display
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var value=busToHex(busname.slice(1))
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if(typeof value != "undefined")
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return value.replace(/./g,function(x){return (15-parseInt(x,16)).toString(16)});
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else
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return undefined;;
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} else {
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return busToHex(busname);
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}
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}
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function chipStatus(){
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var ab = readAddressBus();
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var machine1 =
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' halfcyc:' + cycle +
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' phi0:' + readBit('phi2') +
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' AB:' + hexWord(ab) +
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' D:' + hexByte(readDataBus()) +
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' RnW:' + readBit('rw') +
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' VMA:' + readBit('vma');
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var machine2 =
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' PC:' + hexWord(readPC()) +
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' A:' + hexByte(readAccA()) +
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' B:' + hexByte(readAccB()) +
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' IX:' + hexWord(readIX()) +
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' SP:' + hexWord(readSP()) +
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' ' + readPstring();
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var machine3 =
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'Hz: ' + estimatedHz().toFixed(1);
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if(typeof expertMode != "undefined") {
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machine3 += ' Exec: ' + busToString('Execute'); // no T-state info for 6800 yet
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if(isNodeHigh(nodenames['sync']))
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machine3 += ' (Fetch: ' + busToString('Fetch') + ')';
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if(goldenChecksum != undefined)
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machine3 += " Chk:" + traceChecksum + ((traceChecksum==goldenChecksum)?" OK":" no match");
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}
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setStatus(machine1, machine2, machine3);
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if (logThese.length>1) {
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updateLogbox(logThese);
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}
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selectCell(ab);
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}
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// javascript derived from http://segher.ircgeeks.net/6800/OPS
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var disassembly={
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0x00: "!",
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0x01: "nop",
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0x02: "!",
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0x03: "!",
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0x04: "!",
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0x05: "!",
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0x06: "tap",
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0x07: "tpa",
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0x10: "sba",
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0x11: "cba",
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0x12: "!",
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0x13: "!",
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0x14: "!nba",
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0x15: "!",
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0x16: "tab",
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0x17: "tba",
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0x20: "bra N",
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0x21: "!",
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0x22: "bhi N",
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0x23: "bls N",
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0x24: "bcc N",
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0x25: "bcs N",
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0x26: "bne N",
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0x27: "beq N",
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0x30: "tsx",
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0x31: "ins",
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0x32: "pul a",
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0x33: "pul b",
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0x34: "des",
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0x35: "txs",
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0x36: "psh a",
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0x37: "psh b",
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0x40: "neg a",
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0x41: "!",
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0x42: "!",
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0x43: "com a",
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0x44: "lsr a",
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0x45: "!",
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0x46: "ror a",
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0x47: "asr a",
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0x50: "neg b",
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0x51: "!",
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0x52: "!",
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0x53: "com b",
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0x54: "lsr b",
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0x55: "!",
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0x56: "ror b",
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0x57: "asr b",
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0x60: "neg Nx",
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0x61: "!",
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0x62: "!",
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0x63: "com Nx",
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0x64: "lsr Nx",
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0x65: "!",
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0x66: "ror Nx",
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0x67: "asr Nx",
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0x70: "neg NN",
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0x71: "!",
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0x72: "!",
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0x73: "com NN",
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0x74: "lsr NN",
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0x75: "!",
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0x76: "ror NN",
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0x77: "asr NN",
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0x80: "sub a #",
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0x81: "cmp a #",
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0x82: "sbc a #",
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0x83: "!",
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0x84: "and a #",
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0x85: "bit a #",
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0x86: "lda a #",
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0x87: "!",
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0x90: "sub a N",
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0x91: "cmp a N",
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0x92: "sbc a N",
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0x93: "!",
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0x94: "and a N",
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0x95: "bit a N",
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0x96: "lda a N",
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0x97: "sta a N",
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0xa0: "sub a Nx",
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0xa1: "cmp a Nx",
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0xa2: "sbc a Nx",
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0xa3: "!",
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0xa4: "and a Nx",
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0xa5: "bit a Nx",
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0xa6: "lda a Nx",
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0xa7: "sta a Nx",
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0xb0: "sub a NN",
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0xb1: "cmp a NN",
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0xb2: "sbc a NN",
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0xb3: "!",
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0xb4: "and a NN",
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0xb5: "bit a NN",
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0xb6: "lda a NN",
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0xb7: "sta a NN",
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0xc0: "sub b #",
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0xc1: "cmp b #",
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0xc2: "sbc b #",
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0xc3: "!",
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0xc4: "and b #",
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0xc5: "bit b #",
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0xc6: "lda b #",
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0xc7: "!",
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0xd0: "sub b N",
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0xd1: "cmp b N",
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0xd2: "sbc b N",
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0xd3: "!",
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0xd4: "and b N",
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0xd5: "bit b N",
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0xd6: "lda b N",
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0xd7: "sta b N",
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0xe0: "sub b Nx",
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0xe1: "cmp b Nx",
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0xe2: "sbc b Nx",
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0xe3: "!",
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0xe4: "and b Nx",
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0xe5: "bit b Nx",
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0xe6: "lda b Nx",
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0xe7: "sta b Nx",
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0xf0: "sub b NN",
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0xf1: "cmp b NN",
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0xf2: "sbc b NN",
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0xf3: "!",
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0xf4: "and b NN",
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0xf5: "bit b NN",
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0xf6: "lda b NN",
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0xf7: "sta b NN",
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0x08: "inx",
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0x09: "dex",
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0x0a: "clv",
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0x0b: "sev",
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0x0c: "clc",
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0x0d: "sec",
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0x0e: "cli",
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0x0f: "sei",
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0x18: "!",
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0x19: "daa",
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0x1a: "!",
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0x1b: "aba",
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0x1c: "!",
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0x1d: "!",
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0x1e: "!",
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0x1f: "!",
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0x28: "bvc N",
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0x29: "bvs N",
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0x2a: "bpl N",
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0x2b: "bmi N",
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0x2c: "bge N",
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0x2d: "blt N",
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0x2e: "bgt N",
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0x2f: "ble N",
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0x38: "!",
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0x39: "rts",
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0x3a: "!",
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0x3b: "rti",
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0x3c: "!",
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0x3d: "!",
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0x3e: "wai",
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0x3f: "swi",
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0x48: "asl a",
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0x49: "rol a",
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0x4a: "dec a",
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0x4b: "!",
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0x4c: "inc a",
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0x4d: "tst a",
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0x4e: "!",
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0x4f: "clr a",
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0x58: "asl b",
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0x59: "rol b",
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0x5a: "dec b",
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0x5b: "!",
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0x5c: "inc b",
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0x5d: "tst b",
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0x5e: "!",
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0x5f: "clr b",
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0x68: "asl Nx",
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0x69: "rol Nx",
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0x6a: "dec Nx",
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0x6b: "!",
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0x6c: "inc Nx",
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0x6d: "tst Nx",
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0x6e: "jmp Nx",
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0x6f: "clr Nx",
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0x78: "asl NN",
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0x79: "rol NN",
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0x7a: "dec NN",
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0x7b: "!",
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0x7c: "inc NN",
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0x7d: "tst NN",
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0x7e: "jmp NN",
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0x7f: "clr NN",
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0x88: "eor a #",
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0x89: "adc a #",
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0x8a: "ora a #",
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0x8b: "add a #",
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0x8c: "cpx ##",
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0x8d: "bsr N",
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0x8e: "lds ##",
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0x8f: "!",
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0x98: "eor a N",
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0x99: "adc a N",
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0x9a: "ora a N",
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0x9b: "add a N",
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0x9c: "cpx N",
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0x9d: "!hcf",
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0x9e: "lds N",
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0x9f: "sts N",
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0xa8: "eor a Nx",
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0xa9: "adc a Nx",
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0xaa: "ora a Nx",
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0xab: "add a Nx",
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0xac: "cpx Nx",
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0xad: "jsr Nx",
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0xae: "lds Nx",
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0xaf: "sts Nx",
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0xb8: "eor a NN",
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0xb9: "adc a NN",
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0xba: "ora a NN",
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0xbb: "add a NN",
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0xbc: "cpx NN",
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0xbd: "jsr NN",
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0xbe: "lds NN",
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0xbf: "sts NN",
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0xc8: "eor b #",
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0xc9: "adc b #",
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0xca: "ora b #",
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0xcb: "add b #",
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0xcc: "!",
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0xcd: "!",
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0xce: "ldx ##",
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0xcf: "!",
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0xd8: "eor b N",
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0xd9: "adc b N",
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0xda: "ora b N",
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0xdb: "add b N",
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0xdc: "!",
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0xdd: "!hcf",
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0xde: "ldx N",
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0xdf: "stx N",
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0xe8: "eor b Nx",
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0xe9: "adc b Nx",
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0xea: "ora b Nx",
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0xeb: "add b Nx",
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0xec: "!",
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0xed: "!",
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0xee: "ldx Nx",
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0xef: "stx Nx",
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0xf8: "eor b NN",
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0xf9: "adc b NN",
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0xfa: "ora b NN",
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0xfb: "add b NN",
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0xfc: "!",
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0xfd: "!",
|
|
0xfe: "ldx NN",
|
|
0xff: "stx NN",
|
|
};
|