65C02 Opcode matrix:

imm = #$00
zp = $00
zpx = $00,X
zpy = $00,Y
izp = ($00)
izx = ($00,X)
izy = ($00),Y
abs = $0000
abx = $0000,X
aby = $0000,Y
ind = ($0000)
iax = ($0000,X)
rel = $0000 (PC-relative)

| x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF
0x | BRK 7 | ORA izx 6 | NOP imm 2 | NOP | TSB zp 5 | ORA zp 3 | ASL zp 5 | RMB0 zp 5 | PHP 3 | ORA imm 2 | ASL 2 | NOP | TSB abs 6 | ORA abs 4 | ASL abs 6 | BBR0 rel 2*
1x | BPL rel 2* | ORA izy 5* | ORA izp 5 | NOP | TRB zp 5 | ORA zpx 4 | ASL zpx 6 | RMB1 zp 5 | CLC 2 | ORA aby 4* | INC 2 | NOP | TRB abs 6 | ORA abx 4* | ASL abx 6* | BBR1 rel 2*
2x | JSR abs 6 | AND izx 6 | NOP imm 2 | NOP | BIT zp 3 | AND zp 3 | ROL zp 5 | RMB2 zp 5 | PLP 4 | AND imm 2 | ROL 2 | NOP | BIT abs 4 | AND abs 4 | ROL abs 6 | BBR2 rel 2*
3x | BMI rel 2* | AND izy 5* | AND izp 5 | NOP | BIT zpx 4 | AND zpx 4 | ROL zpx 6 | RMB3 zp 5 | SEC 2 | AND aby 4* | DEC 2 | NOP | BIT abx 4* | AND abx 4* | ROL abx 6* | BBR3 rel 2*
4x | RTI 6 | EOR izx 6 | NOP imm 2 | NOP | NOP zp 3 | EOR zp 3 | LSR zp 5 | RMB4 zp 5 | PHA 3 | EOR imm 2 | LSR 2 | NOP | JMP abs 3 | EOR abs 4 | LSR abs 6 | BBR4 rel 2*
5x | BVC rel 2* | EOR izy 5* | EOR izp 5 | NOP | NOP zpx 4 | EOR zpx 4 | LSR zpx 6 | RMB5 zp 5 | CLI 2 | EOR aby 4* | PHY 3 | NOP | NOP | EOR abx 4* | LSR abx 6* | BBR5 rel 2*
6x | RTS 6 | ADC izx 6 | NOP imm 2 | NOP | STZ zp 3 | ADC zp 3 | ROR zp 5 | RMB6 zp 5 | PLA 4 | ADC imm 2 | ROR 2 | NOP | JMP ind 6 | ADC abs 4 | ROR abs 6 | BBR6 rel 2*
7x | BVS rel 2* | ADC izy 5* | ADC izp 5 | NOP | STZ zpx 4 | ADC zpx 4 | ROR zpx 6 | RMB7 zp 5 | SEI 2 | ADC aby 4* | PLY 4 | NOP | JMP iax 6 | ADC abx 4* | ROR abx 6* | BBR7 rel 2*
8x | BRA rel 3* | STA izx 6 | NOP imm 2 | NOP | STY zp 3 | STA zp 3 | STX zp 3 | SMB0 zp 5 | DEY 2 | BIT imm 2 | TXA 2 | NOP | STY abs 4 | STA abs 4 | STX abs 4 | BBS0 rel 2*
9x | BCC rel 2* | STA izy 6 | STA izp 5 | NOP | STY zpx 4 | STA zpx 4 | STX zpy 4 | SMB1 zp 5 | TYA 2 | STA aby 5 | TXS 2 | NOP | STZ abs 4 | STA abx 5 | STZ abx 5 | BBS1 rel 2*
Ax | LDY imm 2 | LDA izx 6 | LDX imm 2 | NOP | LDY zp 3 | LDA zp 3 | LDX zp 3 | SMB2 zp 5 | TAY 2 | LDA imm 2 | TAX 2 | NOP | LDY abs 4 | LDA abs 4 | LDX abs 4 | BBS2 rel 2*
Bx | BCS rel 2* | LDA izy 5* | LDA izp 5 | NOP | LDY zpx 4 | LDA zpx 4 | LDX zpy 4 | SMB3 zp 5 | CLV 2 | LDA aby 4* | TSX 2 | NOP | LDY abx 4* | LDA abx 4* | LDX aby 4* | BBS3 rel 2*
Cx | CPY imm 2 | CMP izx 6 | NOP imm 2 | NOP | CPY zp 3 | CMP zp 3 | DEC zp 5 | SMB4 zp 5 | INY 2 | CMP imm 2 | DEX 2 | STP ¹ 3 | CPY abs 4 | CMP abs 4 | DEC abs 6 | BBS4 rel 2*
Dx | BNE rel 2* | CMP izy 5* | CMP izp 5 | NOP | NOP zpx 4 | CMP zpx 4 | DEC zpx 6 | SMB5 zp 5 | CLD 2 | CMP aby 4* | PHX 3 | WAI ¹ 3 | NOP | CMP abx 4* | DEC abx 6* | BBS5 rel 2*
Ex | CPX imm 2 | SBC izx 6 | NOP imm 2 | NOP | CPX zp 3 | SBC zp 3 | INC zp 5 | SMB6 zp 5 | INX 2 | SBC imm 2 | NOP 2 | NOP | CPX abs 4 | SBC abs 4 | INC abs 6 | BBS6 rel 2*
Fx | BEQ rel 2* | SBC izy 5* | SBC izp 5 | NOP | NOP zpx 4 | SBC zpx 4 | INC zpx 6 | SMB7 zp 5 | SED 2 | SBC aby 4* | PLX 4 | NOP | NOP | SBC abx 4* | INC abx 6* | BBS7 rel 2*

¹ - Only available on WDC 65C02
"*" : add 1 cycle if page boundary is crossed.
add 1 cycle if direct page register is non zero on direct page adressing modes.
add 1 cycle on conditional branches if taken.
add 1 cycle on these commands if D=1: ADC, SBC
`A = Akkumulator
X = X-Register
Y = Y-Register
S = Stack-Pointer
P = Status-Register
+(S) = Stack-Pointer relative with pre-increment
(S)- = Stack-Pointer relative with post-decrement`
These things have changed from 6502 to 65C02:
- new instructions.
- new adressing modes for a few instrucions.
- one adressing mode for fetch-modify-write instructions has been optimized, so it takes 1 less cycle in some cases.
- flags now work correctly in BCD mode (takes 1 additional cycle).
- absolute-indirect adressing mode now also works on a page boundary (also 1 additional cycle).
- BRK also affects the decimal flag now.
- illegal opcodes perform a NOP.
65C02 opcodes:

Opcode | imp | imm | zp | zpx | zpy | izx | izy | abs | abx | aby | ind | rel | Function | N | V | B | D | I | Z | C
BRA |  |  |  |  |  |  |  |  |  |  |  | $80 | branch always |  |  |  |  |  |  |
PHX | $DA |  |  |  |  |  |  |  |  |  |  |  | (S)-:=X |  |  |  |  |  |  |
PHY | $5A |  |  |  |  |  |  |  |  |  |  |  | (S)-:=Y |  |  |  |  |  |  |
PLX | $FA |  |  |  |  |  |  |  |  |  |  |  | X:=+(S) | * |  |  |  |  | * |
PLY | $7A |  |  |  |  |  |  |  |  |  |  |  | Y:=+(S) | * |  |  |  |  | * |
STZ |  |  | $64 | $74 |  |  |  | $9C | $9E |  |  |  | {adr}:=0 |  |  |  |  |  |  |
TRB |  |  | $14 |  |  |  |  | $1C |  |  |  |  | {adr}:={adr} nand A |  |  |  |  |  | * |
TSB |  |  | $04 |  |  |  |  | $0C |  |  |  |  | {adr}:={adr} or A |  |  |  |  |  | * |
BBRn |  |  |  |  |  |  |  |  |  |  |  | $xF | branch on bit n reset |  |  |  |  |  |  |
BBSn |  |  |  |  |  |  |  |  |  |  |  | $xF | branch on bit n set |  |  |  |  |  |  |
RMBn |  |  | $x7 |  |  |  |  |  |  |  |  |  | {adr}:={adr} nand 2^n |  |  |  |  |  | * |
SMBn |  |  | $x7 |  |  |  |  |  |  |  |  |  | {adr}:={adr} or 2^n |  |  |  |  |  | * |

The WDC 65C02 also includes the STP and WAI instructions known from the 65816.
Another version of this processor, called 65SC02, doesn't have the single-bit instructions BBR/BBS/RMB/SMB.
Changes on instructions of the 6502 instruction set:
INC and DEC now have implied adressing modes.
All major instructions (ORA, ADC, STA...) now also feature the indirect-zeropage adressing mode without index.
JMP features a new absolute-indirect-indexed adressing mode.
BIT now works with a few more adressing modes.
© 2009-2010 Graham. Last change on 17.12.2010.