6502/wudsn-ide
1
0
Fork 0
mirror of https://github.com/peterdell/wudsn-ide.git synced 2024-12-23 00:29:47 +00:00
Code Issues Projects Releases Wiki Activity

Change "CPU" to more general "Target"

Browse Source
This commit is contained in:
peterdell 2021-09-23 21:32:33 +02:00
parent 9ecff51871
commit abdbb3234d
73 changed files with 1794 additions and 1550 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
com.wudsn.ide.asm.compilers.test/.project
View File

@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>com.wudsn.ide.lng.asm.test</name>
<name>com.wudsn.ide.lng.asm.compiler.test</name>
<comment></comment>
<projects>
</projects>

2
com.wudsn.ide.asm.compilers.test/META-INF/MANIFEST.MF
View File

@ -1,7 +1,7 @@
Manifest-Version: 1.0
Bundle-ManifestVersion: 2
Bundle-Name: WUDSN IDE Assembler Test Compilers Plug-in
Bundle-SymbolicName: com.wudsn.ide.lng.asm.test;singleton:=true
Bundle-SymbolicName: com.wudsn.ide.lng.asm.compiler.test;singleton:=true
Bundle-Version: 1.7.2.qualifier
Bundle-Vendor: Peter Dell
Bundle-RequiredExecutionEnvironment: JavaSE-11

6
com.wudsn.ide.asm.compilers.test/OSGI-INF/l10n/bundle.properties
View File

@ -1,8 +1,8 @@
com.wudsn.ide.asm.preferences.test.AssemblerPreferencesTestCompilersPage.name=Test Compilers
com.wudsn.ide.lng.asm.preferences.AssemblerPreferencesTestCompilersPage.name=Test Compilers
com.wudsn.ide.asm.compiler.test.TestCompiler.name=TEST
com.wudsn.ide.lng.asm.compiler.test.TestCompiler.name=TEST
com.wudsn.ide.asm.editor.test.TestEditor.name=Test Editor
com.wudsn.ide.lng.asm.compiler.test.TestEditor.name=Test Editor
com.wudsn.ide.asm.editor.test.TestSourceFile.name=Test Source File

6
com.wudsn.ide.asm.compilers.test/OSGI-INF/l10n/bundle_de_DE.properties
View File

@ -1,8 +1,8 @@
com.wudsn.ide.asm.preferences.test.AssemblerPreferencesTestCompilersPage.name=Test Kompiler
com.wudsn.ide.lng.asm.preferences.AssemblerPreferencesTestCompilersPage.name=Test Kompiler
com.wudsn.ide.asm.compiler.test.TestCompiler.name=TEST
com.wudsn.ide.lng.asm.compiler.test.TestCompiler.name=TEST
com.wudsn.ide.asm.editor.test.TestEditor.name=Test Editor
com.wudsn.ide.lng.asm.compiler.test.TestEditor.name=Test Editor
com.wudsn.ide.asm.editor.test.TestSourceFile.name=Test Quell-Datei

20
com.wudsn.ide.asm.compilers.test/plugin.xml
View File

@ -5,26 +5,26 @@
point="org.eclipse.ui.preferencePages">
<page
category="com.wudsn.ide.lng.preferences.AssemblerPreferencesPage"
class="com.wudsn.ide.asm.preferences.test.AssemblerPreferencesTestCompilersPage"
class="com.wudsn.ide.lng.asm.preferences.AssemblerPreferencesTestCompilersPage"
id="com.wudsn.ide.asm.preferences.test.AssemblerPreferencesTestCompilersPage"
name="%com.wudsn.ide.asm.preferences.test.AssemblerPreferencesTestCompilersPage.name">
</page>
</extension>
<extension point="com.wudsn.ide.lng.compilers">
<compiler
class="com.wudsn.ide.asm.compiler.test.TestCompiler"
class="com.wudsn.ide.lng.asm.test.TestCompiler"
defaultParameters="-o${outputFilePath} ${sourceFilePath}"
defaultHardware="TEST"
homePageURL="https://www.wudsn.com"
id="test"
name="%com.wudsn.ide.asm.compiler.test.TestCompiler.name"
name="%com.wudsn.ide.lng.asm.test.TestCompiler.name"
version="none">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedCPU
cpu="MOS6502_ILLEGAL">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
<supportedTarget
target="MOS6502_ILLEGAL">
</supportedTarget>
</compiler>
</extension>
@ -37,7 +37,7 @@
</extension>
<extension point="org.eclipse.ui.editors">
<editor class="com.wudsn.ide.asm.editor.test.TestEditor"
<editor class="com.wudsn.ide.lng.asm.compiler.test.TestEditor"
contributorClass="org.eclipse.ui.editors.text.TextEditorActionContributor"
default="false" extensions="asm" icon="icons/editor-test-16x16.gif"
id="com.wudsn.ide.lng.editor.test.TestEditor" name="%com.wudsn.ide.asm.editor.test.TestEditor.name">

362
com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/asm/compiler/test/TestCompiler.xml
View File

@ -1,362 +0,0 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<instructionset
completionProposalAutoActivationCharacters="."
singleLineCommentDelimiters=";"
multipleLinesCommentDelimiters=""
stringDelimiterCharacters="&quot;"
blockDefinitionCharacters=""
identifiersCaseSensitive="false"
identifierStartCharacters="?@_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789"
identifierPartCharacters="_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789"
identifierSeparatorCharacter="."
labelDefinitionSuffixCharacter=""
macroUsagePrefixCharacter=""
instructionsCaseSensitive="false"
sourceIncludeDefaultExtension="">
<directive
cpus="*"
name=".AND"
title="Logical _a_n_d"
type="DIRECTIVE"
proposal=".AND _"/>
<directive
cpus="*"
name=".BANK"
title="Start a new _b_a_n_k"
type="DIRECTIVE"
proposal=".BANK_"/>
<directive
cpus="*"
name=".BANKNUM"
title="Current _b_a_n_k _n_u_mber"
type="DIRECTIVE"
proposal=".BANKNUM_"/>
<directive
cpus="*"
name=".BYTE"
title="Define _b_y_t_es"
type="DIRECTIVE"
proposal=".BYTE _"/>
<directive
cpus="*"
name=".CBYTE"
title="Define _character _b_y_t_es"
type="DIRECTIVE"
proposal=".CBYTE _"/>
<directive
cpus="*"
name=".DBYTE"
title="Define _double _b_y_t_es"
type="DIRECTIVE"
proposal=".DBYTE _"/>
<directive
cpus="*"
name=".DEF"
title="Determine if label is _d_e_fined"
type="DIRECTIVE"
proposal=".DEF _"/>
<directive
cpus="*"
name=".DC"
title="_Define _constant storage"
type="DIRECTIVE"
proposal=".DC _"/>
<directive
cpus="*"
name=".DS"
title="_Define _storage"
type="DIRECTIVE"
proposal=".DS _"/>
<directive
cpus="*"
name=".ELSE"
title="_E_l_s_e"
type="DIRECTIVE"
proposal=".ELSE_"/>
<directive
cpus="*"
name=".END"
title="_E_n_d assembly"
type="DIRECTIVE"
proposal=".END_"/>
<directive
cpus="*"
name=".ENDIF"
title="_E_n_d of _I_F"
type="END_FOLDING_BLOCK_DIRECTIVE"
proposal=".ENDIF_"/>
<directive
cpus="*"
name=".ENDM"
title="_E_n_d of _macro"
type="END_SECTION_DIRECTIVE"
proposal=".ENDM_"/>
<directive
cpus="*"
name=".ENDR"
title="_E_n_d of _repeat block"
type="END_SECTION_DIRECTIVE"
proposal=".ENDR_"/>
<directive
cpus="*"
name=".ERROR"
title="Generate _e_r_r_o_r"
type="DIRECTIVE"
proposal=".ERROR &quot;_&quot; _"/>
<directive
cpus="*"
name=".FLOAT"
title="Define _f_l_o_a_ting point number"
type="DIRECTIVE"
proposal=".FLOAT _"/>
<directive
cpus="*"
name=".IF"
title="_I_f"
type="BEGIN_FOLDING_BLOCK_DIRECTIVE"
proposal=".IF _\n.ENDIF"/>
<directive
cpus="*"
name=".INCBIN"
title="_I_n_clude _b_i_nary file"
type="BINARY_INCLUDE_DIRECTIVE"
proposal=".INCBIN &quot;_&quot;"/>
<directive
cpus="*"
name=".INCLUDE"
title="_I_n_c_l_u_d_e source file"
type="SOURCE_INCLUDE_DIRECTIVE"
proposal=".INCLUDE &quot;_&quot;"/>
<directive
cpus="*"
name=".LOCAL"
title="Start new _l_o_c_a_l label region"
type="DIRECTIVE"
proposal=".LOCAL_"/>
<directive
cpus="*"
name=".MACRO"
title="Define _m_a_c_r_o"
type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE"
proposal=".MACRO _\n.ENDM _"/>
/>
<directive
cpus="*"
name=".NOT"
title="Logical _n_o_t"
type="DIRECTIVE"
proposal=".NOT _"/>
<directive
cpus="*"
name=".OPT"
title="Set or clear compiler _o_p_tions"
type="DIRECTIVE"
proposal=".OPT _"/>
<directive
cpus="*"
name=".OR"
title="Logical _o_r"
type="DIRECTIVE"
proposal=".OR _"/>
<directive
cpus="*"
name=".PAGE"
title="Set _p_a_g_e options"
type="DIRECTIVE"
proposal=".PAGE _"/>
<directive
cpus="*"
name=".REF"
title="Determine if label has been _r_e_ferenced"
type="DIRECTIVE"
proposal=".REF _"/>
<directive
cpus="*"
name=".REPT"
title="Begin _R_e_pea_t block"
type="BEGIN_REPEAT_SECTION_DIRECTIVE"
proposal=".REPT _\n.ENDR"/>
<directive
cpus="*"
name=".SBYTE"
title="Define _screen _b_y_t_es"
type="DIRECTIVE"
proposal=".SBYTE _"/>
<directive
cpus="*"
name=".SET"
title="_S_e_t compiler offset"
type="DIRECTIVE"
proposal=".SET _"/>
<directive
cpus="*"
name=".TAB"
title="Set _t_a_b size"
type="DIRECTIVE"
proposal=".TAB _"/>
<directive
cpus="*"
name=".TITLE"
title="Set page _t_i_t_l_e"
type="DIRECTIVE"
proposal=".TITLE _"/>
<directive
cpus="*"
name=".WARN"
title="Generate _w_a_r_ning"
type="DIRECTIVE"
proposal=".WARN &quot;_&quot;"/>
<directive
cpus="*"
name=".WORD"
title="Define _w_o_r_ds"
type="DIRECTIVE"
proposal=".WORD _"/>
<pseudoopcode
cpus="*"
name="BGE"
title="_Branch _greater than or _equal"
proposal="BGE _"/>
<pseudoopcode
cpus="*"
name="BLT"
title="_Branch _less _than"
proposal="BLT _"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="ANC"
title="_A_nd byte with accumulator and set _carry"
proposal="ANC _"
flags="N,Z,C"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="ARR"
title="_And byte with accumulator then _rotate one bit _right in accumulator"
proposal="ARR _"
flags="N,V,Z,C"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="ATX"
title="_And byte with accumulator, then _transfer accumulator to _X register"
proposal="ATX _"
flags="N,Z"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="AXS"
title="_And _X register with accumulator and store result in X register, then _subtract byte from X register (without borrow)"
proposal="AXS _"
flags="N,Z,C"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="AX7"
title="_And _X register with accumulator then and result with _7 and store in memory"
proposal="AX7 _"
flags="-"
addressing="Absolute,Y ;(Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="AXE"
title="_And _X register with accumulator but _exact operation unknown"
proposal="AXE _"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="DCP"
title="_De_crement memory by one and com_pare with memory"
proposal="DCP _"
flags="C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="ISB"
title="_Increase memory by one, then _subtract memory from accumulator (with _borrow)"
proposal="ISB _"
flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="JAM"
title="_J_a_m processor, i.e. stop program counter"
proposal="JAM_"
flags="-"
addressing="Implied"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="LAS"
title="_Load _accumulator, X register and _stack pointer with with memory anded stack pointer"
proposal="LAS _"
flags="N,Z"
addressing="Absolute,Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="LAX"
title="_Load _accumulator and _X register with memory"
proposal="LAX _"
flags="N,Z"
addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="RLA"
title="_Rotate one bit _left in memory, then and _accumulator with memory"
proposal="RLA _"
flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="RRA"
title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)"
proposal="RRA _"
flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="SAX"
title="_Store _accumulator anded with _X register"
proposal="SAX _"
flags="N,Z"
addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="SLO"
title="_Shift _left one bit in memory, then _or accumulator with memory"
proposal="SLO _"
flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="SRE"
title="_Shift _right one bit in memory, then _eor accumulator with memory"
proposal="SRE _"
flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="SXA"
title="_Store _X register _anded with high byte of the target address of the argument +1"
proposal="SXA _"
flags="-"
addressing="Absolute,Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="SYA"
title="_Store _Y register _anded with high byte of the target address of the argument +1"
proposal="SYA _"
flags="-"
addressing="Absolute,x"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
name="XAS"
title="Transfer _X register anded with _accumulator in stack pointer, then and stack pointer with the high byte of the target address of the argument +1. _Store result in memory."
proposal="XAS _"
flags="-"
addressing="Absolute,Y"/>
</instructionset>

2
com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/asm/compiler/test/TestCompiler.java → com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/lng/asm/compiler/test/TestCompiler.java
View File

@ -17,7 +17,7 @@
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.asm.compiler.test;
package com.wudsn.ide.lng.asm.compiler.test;
import com.wudsn.ide.lng.compiler.Compiler;
import com.wudsn.ide.lng.compiler.CompilerProcessLogParser;

167
com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/lng/asm/compiler/test/TestCompiler.xml Normal file
View File

@ -0,0 +1,167 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<instructionset
completionProposalAutoActivationCharacters="."
singleLineCommentDelimiters=";" multipleLinesCommentDelimiters=""
stringDelimiterCharacters="&quot;" blockDefinitionCharacters=""
identifiersCaseSensitive="false"
identifierStartCharacters="?@_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789"
identifierPartCharacters="_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789"
identifierSeparatorCharacter="." labelDefinitionSuffixCharacter=""
macroUsagePrefixCharacter="" instructionsCaseSensitive="false"
sourceIncludeDefaultExtension="">
<directive targets="*" name=".AND" title="Logical _a_n_d"
type="DIRECTIVE" proposal=".AND _" />
<directive targets="*" name=".BANK"
title="Start a new _b_a_n_k" type="DIRECTIVE" proposal=".BANK_" />
<directive targets="*" name=".BANKNUM"
title="Current _b_a_n_k _n_u_mber" type="DIRECTIVE"
proposal=".BANKNUM_" />
<directive targets="*" name=".BYTE" title="Define _b_y_t_es"
type="DIRECTIVE" proposal=".BYTE _" />
<directive targets="*" name=".CBYTE"
title="Define _character _b_y_t_es" type="DIRECTIVE"
proposal=".CBYTE _" />
<directive targets="*" name=".DBYTE"
title="Define _double _b_y_t_es" type="DIRECTIVE" proposal=".DBYTE _" />
<directive targets="*" name=".DEF"
title="Determine if label is _d_e_fined" type="DIRECTIVE"
proposal=".DEF _" />
<directive targets="*" name=".DC"
title="_Define _constant storage" type="DIRECTIVE" proposal=".DC _" />
<directive targets="*" name=".DS" title="_Define _storage"
type="DIRECTIVE" proposal=".DS _" />
<directive targets="*" name=".ELSE" title="_E_l_s_e"
type="DIRECTIVE" proposal=".ELSE_" />
<directive targets="*" name=".END" title="_E_n_d assembly"
type="DIRECTIVE" proposal=".END_" />
<directive targets="*" name=".ENDIF" title="_E_n_d of _I_F"
type="END_FOLDING_BLOCK_DIRECTIVE" proposal=".ENDIF_" />
<directive targets="*" name=".ENDM" title="_E_n_d of _macro"
type="END_SECTION_DIRECTIVE" proposal=".ENDM_" />
<directive targets="*" name=".ENDR"
title="_E_n_d of _repeat block" type="END_SECTION_DIRECTIVE"
proposal=".ENDR_" />
<directive targets="*" name=".ERROR"
title="Generate _e_r_r_o_r" type="DIRECTIVE"
proposal=".ERROR &quot;_&quot; _" />
<directive targets="*" name=".FLOAT"
title="Define _f_l_o_a_ting point number" type="DIRECTIVE"
proposal=".FLOAT _" />
<directive targets="*" name=".IF" title="_I_f"
type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal=".IF _\n.ENDIF" />
<directive targets="*" name=".INCBIN"
title="_I_n_clude _b_i_nary file" type="BINARY_INCLUDE_DIRECTIVE"
proposal=".INCBIN &quot;_&quot;" />
<directive targets="*" name=".INCLUDE"
title="_I_n_c_l_u_d_e source file" type="SOURCE_INCLUDE_DIRECTIVE"
proposal=".INCLUDE &quot;_&quot;" />
<directive targets="*" name=".LOCAL"
title="Start new _l_o_c_a_l label region" type="DIRECTIVE"
proposal=".LOCAL_" />
<directive targets="*" name=".MACRO"
title="Define _m_a_c_r_o"
type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE"
proposal=".MACRO _\n.ENDM _" />
/>
<directive targets="*" name=".NOT" title="Logical _n_o_t"
type="DIRECTIVE" proposal=".NOT _" />
<directive targets="*" name=".OPT"
title="Set or clear compiler _o_p_tions" type="DIRECTIVE"
proposal=".OPT _" />
<directive targets="*" name=".OR" title="Logical _o_r"
type="DIRECTIVE" proposal=".OR _" />
<directive targets="*" name=".PAGE"
title="Set _p_a_g_e options" type="DIRECTIVE" proposal=".PAGE _" />
<directive targets="*" name=".REF"
title="Determine if label has been _r_e_ferenced" type="DIRECTIVE"
proposal=".REF _" />
<directive targets="*" name=".REPT"
title="Begin _R_e_pea_t block" type="BEGIN_REPEAT_SECTION_DIRECTIVE"
proposal=".REPT _\n.ENDR" />
<directive targets="*" name=".SBYTE"
title="Define _screen _b_y_t_es" type="DIRECTIVE" proposal=".SBYTE _" />
<directive targets="*" name=".SET"
title="_S_e_t compiler offset" type="DIRECTIVE" proposal=".SET _" />
<directive targets="*" name=".TAB" title="Set _t_a_b size"
type="DIRECTIVE" proposal=".TAB _" />
<directive targets="*" name=".TITLE"
title="Set page _t_i_t_l_e" type="DIRECTIVE" proposal=".TITLE _" />
<directive targets="*" name=".WARN"
title="Generate _w_a_r_ning" type="DIRECTIVE"
proposal=".WARN &quot;_&quot;" />
<directive targets="*" name=".WORD" title="Define _w_o_r_ds"
type="DIRECTIVE" proposal=".WORD _" />
<pseudoopcode targets="*" name="BGE"
title="_Branch _greater than or _equal" proposal="BGE _" />
<pseudoopcode targets="*" name="BLT"
title="_Branch _less _than" proposal="BLT _" />
<illegalopcode targets="MOS6502_ILLEGAL" name="ANC"
title="_A_nd byte with accumulator and set _carry" proposal="ANC _"
flags="N,Z,C" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="ARR"
title="_And byte with accumulator then _rotate one bit _right in accumulator"
proposal="ARR _" flags="N,V,Z,C" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="ATX"
title="_And byte with accumulator, then _transfer accumulator to _X register"
proposal="ATX _" flags="N,Z" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="AXS"
title="_And _X register with accumulator and store result in X register, then _subtract byte from X register (without borrow)"
proposal="AXS _" flags="N,Z,C" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="AX7"
title="_And _X register with accumulator then and result with _7 and store in memory"
proposal="AX7 _" flags="-" addressing="Absolute,Y ;(Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="AXE"
title="_And _X register with accumulator but _exact operation unknown"
proposal="AXE _" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="DCP"
title="_De_crement memory by one and com_pare with memory"
proposal="DCP _" flags="C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="ISB"
title="_Increase memory by one, then _subtract memory from accumulator (with _borrow)"
proposal="ISB _" flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="JAM"
title="_J_a_m processor, i.e. stop program counter" proposal="JAM_"
flags="-" addressing="Implied" />
<illegalopcode targets="MOS6502_ILLEGAL" name="LAS"
title="_Load _accumulator, X register and _stack pointer with with memory anded stack pointer"
proposal="LAS _" flags="N,Z" addressing="Absolute,Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="LAX"
title="_Load _accumulator and _X register with memory"
proposal="LAX _" flags="N,Z"
addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="RLA"
title="_Rotate one bit _left in memory, then and _accumulator with memory"
proposal="RLA _" flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="RRA"
title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)"
proposal="RRA _" flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SAX"
title="_Store _accumulator anded with _X register" proposal="SAX _"
flags="N,Z" addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SLO"
title="_Shift _left one bit in memory, then _or accumulator with memory"
proposal="SLO _" flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SRE"
title="_Shift _right one bit in memory, then _eor accumulator with memory"
proposal="SRE _" flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X);(Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SXA"
title="_Store _X register _anded with high byte of the target address of the argument +1"
proposal="SXA _" flags="-" addressing="Absolute,Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SYA"
title="_Store _Y register _anded with high byte of the target address of the argument +1"
proposal="SYA _" flags="-" addressing="Absolute,x" />
<illegalopcode targets="MOS6502_ILLEGAL" name="XAS"
title="Transfer _X register anded with _accumulator in stack pointer, then and stack pointer with the high byte of the target address of the argument +1. _Store result in memory."
proposal="XAS _" flags="-" addressing="Absolute,Y" />
</instructionset>

2
com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/asm/compiler/test/TestCompilerProcessLogParser.java → com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/lng/asm/compiler/test/TestCompilerProcessLogParser.java
View File

@ -17,7 +17,7 @@
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.asm.compiler.test;
package com.wudsn.ide.lng.asm.compiler.test;
import java.util.List;
import java.util.StringTokenizer;

2
com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/asm/compiler/test/TestCompilerSourceParser.java → com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/lng/asm/compiler/test/TestCompilerSourceParser.java
View File

@ -17,7 +17,7 @@
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.asm.compiler.test;
package com.wudsn.ide.lng.asm.compiler.test;
import com.wudsn.ide.lng.compiler.parser.CompilerSourceParser;

2
com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/asm/editor/test/TestEditor.java → com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/lng/asm/compiler/test/TestEditor.java
View File

@ -1,4 +1,4 @@
package com.wudsn.ide.asm.editor.test;
package com.wudsn.ide.lng.asm.compiler.test;
import com.wudsn.ide.lng.editor.AssemblerEditor;

9
com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/asm/preferences/test/AssemblerPreferencesTestCompilersPage.java → com.wudsn.ide.asm.compilers.test/src/com/wudsn/ide/lng/asm/preferences/AssemblerPreferencesTestCompilersPage.java
View File

@ -16,10 +16,11 @@
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.asm.preferences.test;
package com.wudsn.ide.lng.asm.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding arbitrary
@ -28,13 +29,13 @@ import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
* @author Peter Dell
*
*/
public final class AssemblerPreferencesTestCompilersPage extends AssemblerPreferencesCompilersPage {
public final class AssemblerPreferencesTestCompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public AssemblerPreferencesTestCompilersPage() {
super(Hardware.TEST);
super(Language.ASM,Hardware.TEST);
}

138
com.wudsn.ide.asm.compilers/plugin.xml
View File

@ -50,18 +50,18 @@
id="acme"
name="%com.wudsn.ide.lng.asm.compiler.acme.AcmeCompiler.name"
version="0.90 (preview)">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedCPU
cpu="MOS65C02">
</supportedCPU>
<supportedCPU
cpu="MOS6502_ILLEGAL">
</supportedCPU>
<supportedCPU
cpu="MOS65816">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
<supportedTarget
target="MOS65C02">
</supportedTarget>
<supportedTarget
target="MOS6502_ILLEGAL">
</supportedTarget>
<supportedTarget
target="MOS65816">
</supportedTarget>
</compiler>
<compiler
@ -73,12 +73,12 @@
id="asm6"
name="%com.wudsn.ide.lng.asm.compiler.asm6.Asm6Compiler.name"
version="1.6">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedCPU
cpu="MOS6502_ILLEGAL">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
<supportedTarget
target="MOS6502_ILLEGAL">
</supportedTarget>
</compiler>
<compiler
class="com.wudsn.ide.lng.asm.compiler.atasm.AtasmCompiler"
@ -89,12 +89,12 @@
id="atasm"
name="%com.wudsn.ide.lng.asm.compiler.atasm.AtasmCompiler.name"
version="1.07">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedCPU
cpu="MOS6502_ILLEGAL">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
<supportedTarget
target="MOS6502_ILLEGAL">
</supportedTarget>
</compiler>
<compiler
class="com.wudsn.ide.lng.asm.compiler.dasm.DasmCompiler"
@ -105,12 +105,12 @@
id="dasm"
name="%com.wudsn.ide.lng.asm.compiler.dasm.DasmCompiler.name"
version="2.20.10 (preview)">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedCPU
cpu="MOS6502_ILLEGAL">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
<supportedTarget
target="MOS6502_ILLEGAL">
</supportedTarget>
</compiler>
<compiler
class="com.wudsn.ide.lng.asm.compiler.kickass.KickAssCompiler"
@ -121,15 +121,15 @@
id="kickass"
name="%com.wudsn.ide.lng.asm.compiler.kickass.KickAssCompiler.name"
version="V3.21 (preview)">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedCPU
cpu="MOS6502_ILLEGAL">
</supportedCPU>
<supportedCPU
cpu="MOS6502_DTV">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
<supportedTarget
target="MOS6502_ILLEGAL">
</supportedTarget>
<supportedTarget
target="MOS6502_DTV">
</supportedTarget>
</compiler>
<compiler
class="com.wudsn.ide.lng.asm.compiler.mads.MadsCompiler"
@ -140,15 +140,15 @@
id="mads"
name="%com.wudsn.ide.lng.asm.compiler.mads.MadsCompiler.name"
version="1.9.0">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedCPU
cpu="MOS6502_ILLEGAL">
</supportedCPU>
<supportedCPU
cpu="MOS65816">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
<supportedTarget
target="MOS6502_ILLEGAL">
</supportedTarget>
<supportedTarget
target="MOS65816">
</supportedTarget>
</compiler>
<compiler
class="com.wudsn.ide.lng.asm.compiler.merlin32.Merlin32Compiler"
@ -159,15 +159,15 @@
id="merlin32"
name="%com.wudsn.ide.lng.asm.compiler.merlin32.Merlin32Compiler.name"
version="1.0">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedCPU
cpu="MOS65C02">
</supportedCPU>
<supportedCPU
cpu="MOS65816">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
<supportedTarget
target="MOS65C02">
</supportedTarget>
<supportedTarget
target="MOS65816">
</supportedTarget>
</compiler>
<compiler
class="com.wudsn.ide.lng.asm.compiler.tass.TassCompiler"
@ -178,15 +178,15 @@
id="tass"
name="%com.wudsn.ide.lng.asm.compiler.tass.TassCompiler.name"
version="1.46 r38 (preview)">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedCPU
cpu="MOS6502_ILLEGAL">
</supportedCPU>
<supportedCPU
cpu="MOS65C02">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
<supportedTarget
target="MOS6502_ILLEGAL">
</supportedTarget>
<supportedTarget
target="MOS65C02">
</supportedTarget>
</compiler>
<compiler
@ -198,9 +198,9 @@
id="xasm"
name="%com.wudsn.ide.lng.asm.compiler.xasm.XasmCompiler.name"
version="3.0.2">
<supportedCPU
cpu="MOS6502">
</supportedCPU>
<supportedTarget
target="MOS6502">
</supportedTarget>
</compiler>
</extension>

126
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/compiler/acme/AcmeCompiler.xml
View File

@ -8,88 +8,88 @@
<!-- The following directives/pseudo opcodes are described in the file "ACME/docs/AllPOs.txt" -->
<!-- Section: How to insert values -->
<directive cpus="*" name="!8" title="Insert _8-bit values" type="DIRECTIVE" proposal="!8 _"/>
<directive cpus="*" name="!BY" title="Insert _b_yte values" type="DIRECTIVE" proposal="!BY _"/>
<directive cpus="*" name="!BYTE" title="Insert _b_y_t_e values" type="DIRECTIVE" proposal="!BYTE _"/>
<directive cpus="*" name="!16" title="Insert _1_6-bit values" type="DIRECTIVE" proposal="!16 _"/>
<directive cpus="*" name="!WO" title="Insert _w_ord values" type="DIRECTIVE" proposal="!WO _"/>
<directive cpus="*" name="!WORD" title="Insert _w_o_r_d values" type="DIRECTIVE" proposal="!WORD _"/>
<directive cpus="*" name="!24" title="Insert _2_4-bit values" type="DIRECTIVE" proposal="!24 _"/>
<directive cpus="*" name="!32" title="Insert _3_2-bit values" type="DIRECTIVE" proposal="!32 _"/>
<directive cpus="*" name="!FILL" title="_F_i_l_l amount of memory with value" type="DIRECTIVE" proposal="!FILL _"/>
<directive cpus="*" name="!FI" title="_F_ill amount of memory with value" type="DIRECTIVE" proposal="!FILL _"/>
<directive cpus="*" name="!ALIGN" title="_A_l_i_g_n program counter" type="DIRECTIVE" proposal="!ALIGN _"/>
<directive targets="*" name="!8" title="Insert _8-bit values" type="DIRECTIVE" proposal="!8 _"/>
<directive targets="*" name="!BY" title="Insert _b_yte values" type="DIRECTIVE" proposal="!BY _"/>
<directive targets="*" name="!BYTE" title="Insert _b_y_t_e values" type="DIRECTIVE" proposal="!BYTE _"/>
<directive targets="*" name="!16" title="Insert _1_6-bit values" type="DIRECTIVE" proposal="!16 _"/>
<directive targets="*" name="!WO" title="Insert _w_ord values" type="DIRECTIVE" proposal="!WO _"/>
<directive targets="*" name="!WORD" title="Insert _w_o_r_d values" type="DIRECTIVE" proposal="!WORD _"/>
<directive targets="*" name="!24" title="Insert _2_4-bit values" type="DIRECTIVE" proposal="!24 _"/>
<directive targets="*" name="!32" title="Insert _3_2-bit values" type="DIRECTIVE" proposal="!32 _"/>
<directive targets="*" name="!FILL" title="_F_i_l_l amount of memory with value" type="DIRECTIVE" proposal="!FILL _"/>
<directive targets="*" name="!FI" title="_F_ill amount of memory with value" type="DIRECTIVE" proposal="!FILL _"/>
<directive targets="*" name="!ALIGN" title="_A_l_i_g_n program counter" type="DIRECTIVE" proposal="!ALIGN _"/>
<!-- Section: How to insert text -->
<directive cpus="*" name="!CONVTAB" title="Set text _c_o_n_version _t_a_ble" type="BINARY_INCLUDE_DIRECTIVE" proposal="!CONVTAB _"/>
<directive cpus="*" name="!TEXT" title="Output _t_e_x_t" type="DIRECTIVE" proposal="!TEXT _"/>
<directive cpus="*" name="!TX" title="Output _te_xt using current conversion table" type="DIRECTIVE" proposal="!TX _"/>
<directive cpus="*" name="!PET" title="Output text using _P_e_tSCII characters" type="DIRECTIVE" proposal="!PET _"/>
<directive cpus="*" name="!RAW" title="Output text as _r_a_w without conversion" type="DIRECTIVE" proposal="!RAW _"/>
<directive cpus="*" name="!SCR" title="Ouput text using _s_c_reen conversion table" type="DIRECTIVE" proposal="!SCR _"/>
<directive cpus="*" name="!SCRXOR" title="Output text using _s_c_reen conversion table and _X_O_R " type="DIRECTIVE" proposal="!SCRXOR _"/>
<directive targets="*" name="!CONVTAB" title="Set text _c_o_n_version _t_a_ble" type="BINARY_INCLUDE_DIRECTIVE" proposal="!CONVTAB _"/>
<directive targets="*" name="!TEXT" title="Output _t_e_x_t" type="DIRECTIVE" proposal="!TEXT _"/>
<directive targets="*" name="!TX" title="Output _te_xt using current conversion table" type="DIRECTIVE" proposal="!TX _"/>
<directive targets="*" name="!PET" title="Output text using _P_e_tSCII characters" type="DIRECTIVE" proposal="!PET _"/>
<directive targets="*" name="!RAW" title="Output text as _r_a_w without conversion" type="DIRECTIVE" proposal="!RAW _"/>
<directive targets="*" name="!SCR" title="Ouput text using _s_c_reen conversion table" type="DIRECTIVE" proposal="!SCR _"/>
<directive targets="*" name="!SCRXOR" title="Output text using _s_c_reen conversion table and _X_O_R " type="DIRECTIVE" proposal="!SCRXOR _"/>
<!-- Section: File stuff -->
<directive cpus="*" name="!TO" title="Define output file to compile _t_o" type="BINARY_OUTPUT_DIRECTIVE" proposal="!TO &quot;_&quot;"/>
<directive cpus="*" name="!SOURCE" title="Assemble another _s_o_u_r_c_e file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="!SOURCE &quot;_&quot;"/>
<directive cpus="*" name="!SRC" title="Assemble another _sou_r_ce file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="!SRC &quot;_&quot;"/>
<directive cpus="*" name="!BINARY" title="Insert _b_i_n_a_r_y file" type="BINARY_INCLUDE_DIRECTIVE" proposal="!BINARY &quot;_&quot;"/>
<directive cpus="*" name="!BIN" title="Insert _b_i_nary file" type="BINARY_INCLUDE_DIRECTIVE" proposal="!BIN &quot;_&quot;"/>
<directive targets="*" name="!TO" title="Define output file to compile _t_o" type="BINARY_OUTPUT_DIRECTIVE" proposal="!TO &quot;_&quot;"/>
<directive targets="*" name="!SOURCE" title="Assemble another _s_o_u_r_c_e file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="!SOURCE &quot;_&quot;"/>
<directive targets="*" name="!SRC" title="Assemble another _sou_r_ce file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="!SRC &quot;_&quot;"/>
<directive targets="*" name="!BINARY" title="Insert _b_i_n_a_r_y file" type="BINARY_INCLUDE_DIRECTIVE" proposal="!BINARY &quot;_&quot;"/>
<directive targets="*" name="!BIN" title="Insert _b_i_nary file" type="BINARY_INCLUDE_DIRECTIVE" proposal="!BIN &quot;_&quot;"/>
<!-- Section: Labels -->
<directive cpus="*" name="!ZONE" title="Begin new _z_o_n_e of local labels" type="DIRECTIVE" proposal="!ZONE_"/>
<directive cpus="*" name="!ZN" title="Begin new _zo_ne of local labels" type="DIRECTIVE" proposal="!ZN_"/>
<directive cpus="*" name="!SL" title="_Save _labels" type="BINARY_INCLUDE_DIRECTIVE" proposal="!SL &quot;_&quot;"/>
<directive targets="*" name="!ZONE" title="Begin new _z_o_n_e of local labels" type="DIRECTIVE" proposal="!ZONE_"/>
<directive targets="*" name="!ZN" title="Begin new _zo_ne of local labels" type="DIRECTIVE" proposal="!ZN_"/>
<directive targets="*" name="!SL" title="_Save _labels" type="BINARY_INCLUDE_DIRECTIVE" proposal="!SL &quot;_&quot;"/>
<!-- Section: Flow control -->
<directive cpus="*" name="!IF" title="_I_f" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!IF _ {\n}"/>
<directive cpus="*" name="}" title="End section" type="END_SECTION_DIRECTIVE" proposal="}_"/>
<directive cpus="*" name="!IFDEF" title="_I_f label _d_e_fined" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!IFDEF _ {\n}"/>
<directive cpus="*" name="!FOR" title="_F_o_r loop" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!FOR _ {\n}"/>
<directive cpus="*" name="!SET" title="_S_e_t label value" type="DIRECTIVE" proposal="!SET _"/>
<directive cpus="*" name="!DO" title="_D_o loop" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!DO _ {\n}"/>
<directive cpus="*" name="!WHILE" title="_W_h_i_l_e condition of a DO loop" type="DIRECTIVE" proposal="!WHILE _ {\n}"/>
<directive cpus="*" name="!UNTIL" title="_U_n_t_i_l condition of a DO loop" type="DIRECTIVE" proposal="!UNTIL _ {\n}"/>
<directive cpus="*" name="!ENDOFFILE" title="_E_n_d _o_f source _f_i_l_e" type="DIRECTIVE" proposal="!ENDOFFILE_"/>
<directive cpus="*" name="!EOF" title="_End _of source _file" type="DIRECTIVE" proposal="!EOF_"/>
<directive targets="*" name="!IF" title="_I_f" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!IF _ {\n}"/>
<directive targets="*" name="}" title="End section" type="END_SECTION_DIRECTIVE" proposal="}_"/>
<directive targets="*" name="!IFDEF" title="_I_f label _d_e_fined" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!IFDEF _ {\n}"/>
<directive targets="*" name="!FOR" title="_F_o_r loop" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!FOR _ {\n}"/>
<directive targets="*" name="!SET" title="_S_e_t label value" type="DIRECTIVE" proposal="!SET _"/>
<directive targets="*" name="!DO" title="_D_o loop" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!DO _ {\n}"/>
<directive targets="*" name="!WHILE" title="_W_h_i_l_e condition of a DO loop" type="DIRECTIVE" proposal="!WHILE _ {\n}"/>
<directive targets="*" name="!UNTIL" title="_U_n_t_i_l condition of a DO loop" type="DIRECTIVE" proposal="!UNTIL _ {\n}"/>
<directive targets="*" name="!ENDOFFILE" title="_E_n_d _o_f source _f_i_l_e" type="DIRECTIVE" proposal="!ENDOFFILE_"/>
<directive targets="*" name="!EOF" title="_End _of source _file" type="DIRECTIVE" proposal="!EOF_"/>
<!-- Section: Macro usage -->
<directive cpus="*" name="!MACRO" title="Define _m_a_c_r_o" type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE" proposal="!MACRO _ {\n}"/>
<directive targets="*" name="!MACRO" title="Define _m_a_c_r_o" type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE" proposal="!MACRO _ {\n}"/>
<!-- Section: Segment assembly -->
<directive cpus="*" name="!INITMEM" title="_I_n_i_tialize _m_e_mory" type="DIRECTIVE" proposal="!INITMEM_"/>
<directive targets="*" name="!INITMEM" title="_I_n_i_tialize _m_e_mory" type="DIRECTIVE" proposal="!INITMEM_"/>
<!-- Section: Offset assembly -->
<directive cpus="*" name="!PSEUDOPC" title="Set _p_s_e_u_d_o _program _counter" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!PSEUDOPC _ {\n}"/>
<directive targets="*" name="!PSEUDOPC" title="Set _p_s_e_u_d_o _program _counter" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!PSEUDOPC _ {\n}"/>
<!-- Section: CPU support pseudo opcodes (especially 65816 support) -->
<directive cpus="*" name="!CPU" title="Set _C_P_U type" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!CPU _"/>
<pseudoopcode cpus="MOS65816" name="!AL" title="Set _accumulator _long mode" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!AL_"/>
<pseudoopcode cpus="MOS65816" name="!AS" title="Set _accumulator _short mode" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!AS_"/>
<pseudoopcode cpus="MOS65816" name="!RL" title="Set _register _long mode" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!RL_"/>
<pseudoopcode cpus="MOS65816" name="!RS" title="Set _register _short mode" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!RS_"/>
<!-- Section: Target support pseudo opcodes (especially 65816 support) -->
<directive targets="*" name="!CPU" title="Set _C_P_U type" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!CPU _"/>
<pseudoopcode targets="MOS65816" name="!AL" title="Set _accumulator _long mode" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!AL_"/>
<pseudoopcode targets="MOS65816" name="!AS" title="Set _accumulator _short mode" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!AS_"/>
<pseudoopcode targets="MOS65816" name="!RL" title="Set _register _long mode" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!RL_"/>
<pseudoopcode targets="MOS65816" name="!RS" title="Set _register _short mode" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!RS_"/>
<!-- Section: Deprecated pseudo opcodes (they still work at the moment) -->
<directive cpus="*" name="!CBM" title="Set text conversion table to _C_B_M (deprecated)" type="DIRECTIVE" proposal="!CBM_"/>
<directive cpus="*" name="!SUBZONE" title="Begin new _s_u_b _z_o_n_e of local labels (deprecated)" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!SUBZONE _ {\n}"/>
<directive cpus="*" name="!REALPC" title="Restore _r_e_a_l _program _counter (deprecated)" type="DIRECTIVE" proposal="!REALPC_"/>
<directive targets="*" name="!CBM" title="Set text conversion table to _C_B_M (deprecated)" type="DIRECTIVE" proposal="!CBM_"/>
<directive targets="*" name="!SUBZONE" title="Begin new _s_u_b _z_o_n_e of local labels (deprecated)" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="!SUBZONE _ {\n}"/>
<directive targets="*" name="!REALPC" title="Restore _r_e_a_l _program _counter (deprecated)" type="DIRECTIVE" proposal="!REALPC_"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="ANC" title="_A_nd byte with accumulator and set _carry" proposal="ANC _" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="ARR" title="_And byte with accumulator then _rotate one bit _right in accumulator" proposal="ARR _" flags="N,V,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="ASR" title="_And byte with accumulator then logical _shift _right in accumulator" proposal="ASR _" flags="N,V,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="DCP" title="_De_crement memory by one and com_pare with memory" proposal="DCP _" flags="C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="DOP" title="_Double N_O_P" proposal="DOP_" flags="-" addressing="Implied; Immediate; Zero Page; Zero Page,X"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="ISC" title="_Increase memory by one, then _subtract memory from accumulator (with _carry)" proposal="ISC _" flags="N,V,Z,C"
<illegalopcode targets="MOS6502_ILLEGAL" name="ANC" title="_A_nd byte with accumulator and set _carry" proposal="ANC _" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="ARR" title="_And byte with accumulator then _rotate one bit _right in accumulator" proposal="ARR _" flags="N,V,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="ASR" title="_And byte with accumulator then logical _shift _right in accumulator" proposal="ASR _" flags="N,V,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="DCP" title="_De_crement memory by one and com_pare with memory" proposal="DCP _" flags="C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="DOP" title="_Double N_O_P" proposal="DOP_" flags="-" addressing="Implied; Immediate; Zero Page; Zero Page,X"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="ISC" title="_Increase memory by one, then _subtract memory from accumulator (with _carry)" proposal="ISC _" flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="JAM" title="_J_a_m processor, i.e. stop program counter" proposal="JAM_" flags="-" addressing="Implied"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="LAX" title="_Load _accumulator and _X register with memory" proposal="LAX _" flags="N,Z" addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="RLA" title="_Rotate one bit _left in memory, then and _accumulator with memory" proposal="RLA _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="RRA" title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)" proposal="RRA _" flags="N,V,Z,C"
<illegalopcode targets="MOS6502_ILLEGAL" name="JAM" title="_J_a_m processor, i.e. stop program counter" proposal="JAM_" flags="-" addressing="Implied"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="LAX" title="_Load _accumulator and _X register with memory" proposal="LAX _" flags="N,Z" addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="RLA" title="_Rotate one bit _left in memory, then and _accumulator with memory" proposal="RLA _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="RRA" title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)" proposal="RRA _" flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="SAX" title="_Store _accumulator anded with _X register" proposal="SAX _" flags="N,Z" addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="SBX" title="_Su_btract byte from _X register (without borrow) after anding X register with accumulator" proposal="SBX _" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="SLO" title="_Shift _left one bit in memory, then _or accumulator with memory" proposal="SLO _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="SRE" title="_Shift _right one bit in memory, then _eor accumulator with memory" proposal="SRE _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="TOP" title="_Triple N_O_P" proposal="TOP_" flags="-" addressing="Implied; Absolute; Absolute,X"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="SAX" title="_Store _accumulator anded with _X register" proposal="SAX _" flags="N,Z" addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="SBX" title="_Su_btract byte from _X register (without borrow) after anding X register with accumulator" proposal="SBX _" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="SLO" title="_Shift _left one bit in memory, then _or accumulator with memory" proposal="SLO _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="SRE" title="_Shift _right one bit in memory, then _eor accumulator with memory" proposal="SRE _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="TOP" title="_Triple N_O_P" proposal="TOP_" flags="-" addressing="Implied; Absolute; Absolute,X"/>
</instructionset>

108
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/compiler/asm6/Asm6Compiler.xml
View File

@ -15,60 +15,60 @@
instructionsCaseSensitive="false"
sourceIncludeDefaultExtension="">
<directive cpus="*" name="ALIGN" title="_A_l_i_g_n program counter" type="DIRECTIVE" proposal="ALIGN _"/>
<directive cpus="*" name="BASE" title="Set the _B_a_s_e program address" type="DIRECTIVE" proposal="BASE _"/>
<directive cpus="*" name="BIN" title="Include _b_i_nary file" type="BINARY_INCLUDE_DIRECTIVE" proposal="BIN &quot;_&quot;"/>
<directive cpus="*" name="BYTE" title="Declare constant as _b_y_t_e" type="DIRECTIVE" proposal="BYTE _"/>
<directive cpus="*" name="DC.B" title="_Declare _constant as _byte" type="DIRECTIVE" proposal="DC.B _"/>
<directive cpus="*" name="DC.W" title="_Declare _constant as _word" type="DIRECTIVE" proposal="DC.W _"/>
<directive cpus="*" name="DB" title="_Declare constant as _byte" type="DIRECTIVE" proposal="DB _"/>
<directive cpus="*" name="DW" title="_Declare constant as _word" type="DIRECTIVE" proposal="DW _"/>
<directive cpus="*" name="DL" title="_Declare only _lower byte of a 16-bit word" type="DIRECTIVE" proposal="DL _"/>
<directive cpus="*" name="DH" title="_Declare only _higher byte of a 16-bit word" type="DIRECTIVE" proposal="DH _"/>
<directive cpus="*" name="DS.B" title="_Declare _space in _bytes" type="DIRECTIVE" proposal="DS.B _"/>
<directive cpus="*" name="DSB" title="_Declare _space in _bytes" type="DIRECTIVE" proposal="DSB _"/>
<directive cpus="*" name="DS.W" title="_Declare _space in _words" type="DIRECTIVE" proposal="DS.W _"/>
<directive cpus="*" name="DSW" title="_Declare _space in _words" type="DIRECTIVE" proposal="DSW _"/>
<directive cpus="*" name="ELSE" title="_E_l_s_e" type="DIRECTIVE" proposal="ELSE_"/>
<directive cpus="*" name="ELSEIF" title="_E_l_s_e _I_f" type="DIRECTIVE" proposal="ELSEIF _"/>
<directive cpus="*" name="ENDIF" title="_E_n_d of _I_F" type="END_FOLDING_BLOCK_DIRECTIVE" proposal="ENDIF_"/>
<directive cpus="*" name="ENDM" title="_E_n_d of _macro" type="END_SECTION_DIRECTIVE" proposal="ENDM_"/>
<directive cpus="*" name="ENDE" title="_E_n_d _enumeration definition" type="END_SECTION_DIRECTIVE" proposal="ENDE_"/>
<directive cpus="*" name="ENUM" title="Define _e_n_u_meration" type="BEGIN_ENUM_DEFINITION_SECTION_DIRECTIVE" proposal="ENUM _\nENDE"/>
<directive cpus="*" name="EQU" title="Set _e_q_uate" type="DIRECTIVE" proposal="EQU _"/>
<directive cpus="*" name="ERROR" title="End assmbly with _e_r_r_o_r" type="DIRECTIVE" proposal="ERROR _"/>
<directive cpus="*" name="FILLVALUE" title="Change the default _f_i_l_l _v_a_l_u_e for PAD and ALIGN" type="DIRECTIVE" proposal="FILLVALUE _"/>
<directive cpus="*" name="HEX" title="Declare raw _h_e_x data" type="DIRECTIVE" proposal="HEX _"/>
<directive cpus="*" name="IF" title="_I_f" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="IF _\nENDIF"/>
<directive cpus="*" name="IFDEF" title="_I_f _d_e_fined" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="IFDEF _\nENDIF"/>
<directive cpus="*" name="IFNDEF" title="_I_f _not _d_e_fined" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="IFNDEF _\nENDIF"/>
<directive cpus="*" name="INCBIN" title="_I_n_clude _b_i_nary file" type="BINARY_INCLUDE_DIRECTIVE" proposal="INCBIN &quot;_&quot;"/>
<directive cpus="*" name="INCLUDE" title="_I_n_c_l_u_d_e source file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="INCLUDE &quot;_&quot;"/>
<directive cpus="*" name="INCSRC" title="_I_n_clude _sou_r_ce file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="INCSRC &quot;_&quot;"/>
<directive cpus="*" name="MACRO" title="Define _m_a_c_r_o" type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE" proposal="MACRO _\nENDM _"/>
<directive cpus="*" name="ORG" title="Set _o_ri_gin if it hasn't been assigned yet, otherwise will function like PAD" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal="ORG _"/>
<directive cpus="*" name="PAD" title="_P_a_d memory from current address to the specified address with FILLVALUE" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal="PAD _"/>
<directive cpus="*" name="REPT" title="Begin _r_e_pea_t block" type="BEGIN_REPEAT_SECTION_DIRECTIVE" proposal="REPT _\nENDR"/>
<directive cpus="*" name="ENDR" title="_E_n_d _repeat block" type="END_SECTION_DIRECTIVE" proposal="ENDR_"/>
<directive cpus="*" name="WORD" title="Declare constant as _w_o_r_d" type="DIRECTIVE" proposal="WORD _"/>
<directive targets="*" name="ALIGN" title="_A_l_i_g_n program counter" type="DIRECTIVE" proposal="ALIGN _"/>
<directive targets="*" name="BASE" title="Set the _B_a_s_e program address" type="DIRECTIVE" proposal="BASE _"/>
<directive targets="*" name="BIN" title="Include _b_i_nary file" type="BINARY_INCLUDE_DIRECTIVE" proposal="BIN &quot;_&quot;"/>
<directive targets="*" name="BYTE" title="Declare constant as _b_y_t_e" type="DIRECTIVE" proposal="BYTE _"/>
<directive targets="*" name="DC.B" title="_Declare _constant as _byte" type="DIRECTIVE" proposal="DC.B _"/>
<directive targets="*" name="DC.W" title="_Declare _constant as _word" type="DIRECTIVE" proposal="DC.W _"/>
<directive targets="*" name="DB" title="_Declare constant as _byte" type="DIRECTIVE" proposal="DB _"/>
<directive targets="*" name="DW" title="_Declare constant as _word" type="DIRECTIVE" proposal="DW _"/>
<directive targets="*" name="DL" title="_Declare only _lower byte of a 16-bit word" type="DIRECTIVE" proposal="DL _"/>
<directive targets="*" name="DH" title="_Declare only _higher byte of a 16-bit word" type="DIRECTIVE" proposal="DH _"/>
<directive targets="*" name="DS.B" title="_Declare _space in _bytes" type="DIRECTIVE" proposal="DS.B _"/>
<directive targets="*" name="DSB" title="_Declare _space in _bytes" type="DIRECTIVE" proposal="DSB _"/>
<directive targets="*" name="DS.W" title="_Declare _space in _words" type="DIRECTIVE" proposal="DS.W _"/>
<directive targets="*" name="DSW" title="_Declare _space in _words" type="DIRECTIVE" proposal="DSW _"/>
<directive targets="*" name="ELSE" title="_E_l_s_e" type="DIRECTIVE" proposal="ELSE_"/>
<directive targets="*" name="ELSEIF" title="_E_l_s_e _I_f" type="DIRECTIVE" proposal="ELSEIF _"/>
<directive targets="*" name="ENDIF" title="_E_n_d of _I_F" type="END_FOLDING_BLOCK_DIRECTIVE" proposal="ENDIF_"/>
<directive targets="*" name="ENDM" title="_E_n_d of _macro" type="END_SECTION_DIRECTIVE" proposal="ENDM_"/>
<directive targets="*" name="ENDE" title="_E_n_d _enumeration definition" type="END_SECTION_DIRECTIVE" proposal="ENDE_"/>
<directive targets="*" name="ENUM" title="Define _e_n_u_meration" type="BEGIN_ENUM_DEFINITION_SECTION_DIRECTIVE" proposal="ENUM _\nENDE"/>
<directive targets="*" name="EQU" title="Set _e_q_uate" type="DIRECTIVE" proposal="EQU _"/>
<directive targets="*" name="ERROR" title="End assmbly with _e_r_r_o_r" type="DIRECTIVE" proposal="ERROR _"/>
<directive targets="*" name="FILLVALUE" title="Change the default _f_i_l_l _v_a_l_u_e for PAD and ALIGN" type="DIRECTIVE" proposal="FILLVALUE _"/>
<directive targets="*" name="HEX" title="Declare raw _h_e_x data" type="DIRECTIVE" proposal="HEX _"/>
<directive targets="*" name="IF" title="_I_f" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="IF _\nENDIF"/>
<directive targets="*" name="IFDEF" title="_I_f _d_e_fined" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="IFDEF _\nENDIF"/>
<directive targets="*" name="IFNDEF" title="_I_f _not _d_e_fined" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="IFNDEF _\nENDIF"/>
<directive targets="*" name="INCBIN" title="_I_n_clude _b_i_nary file" type="BINARY_INCLUDE_DIRECTIVE" proposal="INCBIN &quot;_&quot;"/>
<directive targets="*" name="INCLUDE" title="_I_n_c_l_u_d_e source file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="INCLUDE &quot;_&quot;"/>
<directive targets="*" name="INCSRC" title="_I_n_clude _sou_r_ce file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="INCSRC &quot;_&quot;"/>
<directive targets="*" name="MACRO" title="Define _m_a_c_r_o" type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE" proposal="MACRO _\nENDM _"/>
<directive targets="*" name="ORG" title="Set _o_ri_gin if it hasn't been assigned yet, otherwise will function like PAD" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal="ORG _"/>
<directive targets="*" name="PAD" title="_P_a_d memory from current address to the specified address with FILLVALUE" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal="PAD _"/>
<directive targets="*" name="REPT" title="Begin _r_e_pea_t block" type="BEGIN_REPEAT_SECTION_DIRECTIVE" proposal="REPT _\nENDR"/>
<directive targets="*" name="ENDR" title="_E_n_d _repeat block" type="END_SECTION_DIRECTIVE" proposal="ENDR_"/>
<directive targets="*" name="WORD" title="Declare constant as _w_o_r_d" type="DIRECTIVE" proposal="WORD _"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="ANC" title="_A_nd byte with accumulator and set _carry" proposal="ANC _" flags="N,Z,C" addressing="Immediate" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="ANE" title="_A_nd X register with accumulator but _exact operation unknown" proposal="ANE _" addressing="Immediate" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="ARR" title="_And byte with accumulator then _rotate one bit _right in accumulator" proposal="ARR _" flags="N,V,Z,C" addressing="Immediate" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="DCP" title="_De_crement memory by one and com_pare with memory" proposal="DCP _" flags="C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="ISB" title="_Increase memory by one, then _subtract memory from accumulator (with _borrow)" proposal="ISB _" flags="N,V,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="LAS" title="_Load _accumulator, X register and _stack pointer with with memory anded stack pointer" proposal="LAS _" flags="N,Z" addressing="Absolute,Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="LAX" title="_Load _accumulator and _X register with memory" proposal="LAX _" flags="N,Z" addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="LXA" title="And byte with accumulator, then _load value into _X register and _accumulator" proposal="LXA _" flags="N,Z" addressing="Immediate" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="RLA" title="_Rotate one bit _left in memory, then and _accumulator with memory" proposal="RLA _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="RRA" title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)" proposal="RRA _" flags="N,V,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="SAX" title="_Store _accumulator anded with _X register" proposal="SAX _" flags="N,Z" addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="SBX" title="_Subtract _byte from _X register (without borrow) after X register anded with the accumulator and store result in X register" proposal="SBX _" flags="N,Z,C" addressing="Immediate" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="SHA" title="_Store (don't know what _H is for) X register anded with _accumulator anded with 7" proposal="SHA _" flags="-" addressing="Absolute,Y ;(Indirect),Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="SHS" title="And X register with accumulator and move to stack pointer. _Store _high byte of the target address of the argument +1 anded with _stack pointer" proposal="SHS _" flags="-" addressing="Absolute,Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="SHX" title="_Store _high byte of the target address of the argument +1 anded with _X register" proposal="SHX _" flags="-" addressing="Absolute,Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="SHY" title="_Store _high byte of the target address of the argument +1 anded with _Y register" proposal="SHY _" flags="-" addressing="Absolute,x" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="SLO" title="_Shift _left one bit in memory, then _or accumulator with memory" proposal="SLO _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y" />
<illegalopcode cpus="MOS6502_ILLEGAL" name="SRE" title="_Shift _right one bit in memory, then _eor accumulator with memory" proposal="SRE _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X);(Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="ANC" title="_A_nd byte with accumulator and set _carry" proposal="ANC _" flags="N,Z,C" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="ANE" title="_A_nd X register with accumulator but _exact operation unknown" proposal="ANE _" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="ARR" title="_And byte with accumulator then _rotate one bit _right in accumulator" proposal="ARR _" flags="N,V,Z,C" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="DCP" title="_De_crement memory by one and com_pare with memory" proposal="DCP _" flags="C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="ISB" title="_Increase memory by one, then _subtract memory from accumulator (with _borrow)" proposal="ISB _" flags="N,V,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="LAS" title="_Load _accumulator, X register and _stack pointer with with memory anded stack pointer" proposal="LAS _" flags="N,Z" addressing="Absolute,Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="LAX" title="_Load _accumulator and _X register with memory" proposal="LAX _" flags="N,Z" addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="LXA" title="And byte with accumulator, then _load value into _X register and _accumulator" proposal="LXA _" flags="N,Z" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="RLA" title="_Rotate one bit _left in memory, then and _accumulator with memory" proposal="RLA _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="RRA" title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)" proposal="RRA _" flags="N,V,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SAX" title="_Store _accumulator anded with _X register" proposal="SAX _" flags="N,Z" addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SBX" title="_Subtract _byte from _X register (without borrow) after X register anded with the accumulator and store result in X register" proposal="SBX _" flags="N,Z,C" addressing="Immediate" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SHA" title="_Store (don't know what _H is for) X register anded with _accumulator anded with 7" proposal="SHA _" flags="-" addressing="Absolute,Y ;(Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SHS" title="And X register with accumulator and move to stack pointer. _Store _high byte of the target address of the argument +1 anded with _stack pointer" proposal="SHS _" flags="-" addressing="Absolute,Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SHX" title="_Store _high byte of the target address of the argument +1 anded with _X register" proposal="SHX _" flags="-" addressing="Absolute,Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SHY" title="_Store _high byte of the target address of the argument +1 anded with _Y register" proposal="SHY _" flags="-" addressing="Absolute,x" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SLO" title="_Shift _left one bit in memory, then _or accumulator with memory" proposal="SLO _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y" />
<illegalopcode targets="MOS6502_ILLEGAL" name="SRE" title="_Shift _right one bit in memory, then _eor accumulator with memory" proposal="SRE _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X);(Indirect),Y" />
</instructionset>

108
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/compiler/atasm/AtasmCompiler.xml
View File

@ -16,237 +16,237 @@
sourceIncludeDefaultExtension="">
<directive
cpus="*"
targets="*"
name=".AND"
title="Logical _a_n_d"
type="DIRECTIVE"
proposal=".AND _"/>
<directive
cpus="*"
targets="*"
name=".BANK"
title="Start a new _b_a_n_k"
type="DIRECTIVE"
proposal=".BANK_"/>
<directive
cpus="*"
targets="*"
name=".BANKNUM"
title="Current _b_a_n_k _n_u_mber"
type="DIRECTIVE"
proposal=".BANKNUM_"/>
<directive
cpus="*"
targets="*"
name=".BYTE"
title="Define _b_y_t_es"
type="DIRECTIVE"
proposal=".BYTE _"/>
<directive
cpus="*"
targets="*"
name=".CBYTE"
title="Define _character _b_y_t_es"
type="DIRECTIVE"
proposal=".CBYTE _"/>
<directive
cpus="*"
targets="*"
name=".DBYTE"
title="Define _double _b_y_t_es"
type="DIRECTIVE"
proposal=".DBYTE _"/>
<directive
cpus="*"
targets="*"
name=".DEF"
title="Determine if label is _d_e_fined"
type="DIRECTIVE"
proposal=".DEF _"/>
<directive
cpus="*"
targets="*"
name=".DC"
title="_Define _constant storage"
type="DIRECTIVE"
proposal=".DC _"/>
<directive
cpus="*"
targets="*"
name=".DS"
title="_Define _storage"
type="DIRECTIVE"
proposal=".DS _"/>
<directive
cpus="*"
targets="*"
name=".ELSE"
title="_E_l_s_e"
type="DIRECTIVE"
proposal=".ELSE_"/>
<directive
cpus="*"
targets="*"
name=".END"
title="_E_n_d assembly"
type="DIRECTIVE"
proposal=".END_"/>
<directive
cpus="*"
targets="*"
name=".ENDIF"
title="_E_n_d of _I_F"
type="END_FOLDING_BLOCK_DIRECTIVE"
proposal=".ENDIF_"/>
<directive
cpus="*"
targets="*"
name=".ENDM"
title="_E_n_d of _macro"
type="END_SECTION_DIRECTIVE"
proposal=".ENDM_"/>
<directive
cpus="*"
targets="*"
name=".ENDR"
title="_E_n_d of _repeat block"
type="END_SECTION_DIRECTIVE"
proposal=".ENDR_"/>
<directive
cpus="*"
targets="*"
name=".ERROR"
title="Generate _e_r_r_o_r"
type="DIRECTIVE"
proposal=".ERROR &quot;_&quot; _"/>
<directive
cpus="*"
targets="*"
name=".FLOAT"
title="Define _f_l_o_a_ting point number"
type="DIRECTIVE"
proposal=".FLOAT _"/>
<directive
cpus="*"
targets="*"
name=".IF"
title="_I_f"
type="BEGIN_FOLDING_BLOCK_DIRECTIVE"
proposal=".IF _\n.ENDIF"/>
<directive
cpus="*"
targets="*"
name=".INCBIN"
title="_I_n_clude _b_i_nary file"
type="BINARY_INCLUDE_DIRECTIVE"
proposal=".INCBIN &quot;_&quot;"/>
<directive
cpus="*"
targets="*"
name=".INCLUDE"
title="_I_n_c_l_u_d_e source file"
type="SOURCE_INCLUDE_DIRECTIVE"
proposal=".INCLUDE &quot;_&quot;"/>
<directive
cpus="*"
targets="*"
name=".LOCAL"
title="Start new _l_o_c_a_l label region"
type="DIRECTIVE"
proposal=".LOCAL_"/>
<directive
cpus="*"
targets="*"
name=".MACRO"
title="Define _m_a_c_r_o"
type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE"
proposal=".MACRO _\n.ENDM _"/>
/>
<directive
cpus="*"
targets="*"
name=".NOT"
title="Logical _n_o_t"
type="DIRECTIVE"
proposal=".NOT _"/>
<directive
cpus="*"
targets="*"
name=".OPT"
title="Set or clear compiler _o_p_tions"
type="DIRECTIVE"
proposal=".OPT _"/>
<directive
cpus="*"
targets="*"
name=".OR"
title="Logical _o_r"
type="DIRECTIVE"
proposal=".OR _"/>
<directive
cpus="*"
targets="*"
name=".PAGE"
title="Set _p_a_g_e options"
type="DIRECTIVE"
proposal=".PAGE _"/>
<directive
cpus="*"
targets="*"
name=".REF"
title="Determine if label has been _r_e_ferenced"
type="DIRECTIVE"
proposal=".REF _"/>
<directive
cpus="*"
targets="*"
name=".REPT"
title="Begin _R_e_pea_t block"
type="BEGIN_REPEAT_SECTION_DIRECTIVE"
proposal=".REPT _\n.ENDR"/>
<directive
cpus="*"
targets="*"
name=".SBYTE"
title="Define _screen _b_y_t_es"
type="DIRECTIVE"
proposal=".SBYTE _"/>
<directive
cpus="*"
targets="*"
name=".SET"
title="_S_e_t compiler offset"
type="DIRECTIVE"
proposal=".SET _"/>
<directive
cpus="*"
targets="*"
name=".TAB"
title="Set _t_a_b size"
type="DIRECTIVE"
proposal=".TAB _"/>
<directive
cpus="*"
targets="*"
name=".TITLE"
title="Set page _t_i_t_l_e"
type="DIRECTIVE"
proposal=".TITLE _"/>
<directive
cpus="*"
targets="*"
name=".WARN"
title="Generate _w_a_r_ning"
type="DIRECTIVE"
proposal=".WARN &quot;_&quot;"/>
<directive
cpus="*"
targets="*"
name=".WORD"
title="Define _w_o_r_ds"
type="DIRECTIVE"
proposal=".WORD _"/>
<pseudoopcode
cpus="*"
targets="*"
name="BGE"
title="_Branch _greater than or _equal"
proposal="BGE _"/>
<pseudoopcode
cpus="*"
targets="*"
name="BLT"
title="_Branch _less _than"
proposal="BLT _"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="ANC" title="_A_nd byte with accumulator and set _carry" proposal="ANC _" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="ARR" title="_And byte with accumulator then _rotate one bit _right in accumulator" proposal="ARR _" flags="N,V,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="ATX" title="_And byte with accumulator, then _transfer accumulator to _X register" proposal="ATX _" flags="N,Z" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="AXS" title="_And _X register with accumulator and store result in X register, then _subtract byte from X register (without borrow)" proposal="AXS _" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="AX7" title="_And _X register with accumulator then and result with _7 and store in memory" proposal="AX7 _" flags="-" addressing="Absolute,Y ;(Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="AXE" title="_And _X register with accumulator but _exact operation unknown" proposal="AXE _" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="DCP" title="_De_crement memory by one and com_pare with memory" proposal="DCP _" flags="C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="ISB" title="_Increase memory by one, then _subtract memory from accumulator (with _borrow)" proposal="ISB _" flags="N,V,Z,C"
<illegalopcode targets="MOS6502_ILLEGAL" name="ANC" title="_A_nd byte with accumulator and set _carry" proposal="ANC _" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="ARR" title="_And byte with accumulator then _rotate one bit _right in accumulator" proposal="ARR _" flags="N,V,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="ATX" title="_And byte with accumulator, then _transfer accumulator to _X register" proposal="ATX _" flags="N,Z" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="AXS" title="_And _X register with accumulator and store result in X register, then _subtract byte from X register (without borrow)" proposal="AXS _" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="AX7" title="_And _X register with accumulator then and result with _7 and store in memory" proposal="AX7 _" flags="-" addressing="Absolute,Y ;(Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="AXE" title="_And _X register with accumulator but _exact operation unknown" proposal="AXE _" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="DCP" title="_De_crement memory by one and com_pare with memory" proposal="DCP _" flags="C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="ISB" title="_Increase memory by one, then _subtract memory from accumulator (with _borrow)" proposal="ISB _" flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="JAM" title="_J_a_m processor, i.e. stop program counter" proposal="JAM_" flags="-" addressing="Implied"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="LAS" title="_Load _accumulator, X register and _stack pointer with with memory anded stack pointer" proposal="LAS _" flags="N,Z" addressing="Absolute,Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="LAX" title="_Load _accumulator and _X register with memory" proposal="LAX _" flags="N,Z" addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="RLA" title="_Rotate one bit _left in memory, then and _accumulator with memory" proposal="RLA _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="RRA" title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)" proposal="RRA _" flags="N,V,Z,C"
<illegalopcode targets="MOS6502_ILLEGAL" name="JAM" title="_J_a_m processor, i.e. stop program counter" proposal="JAM_" flags="-" addressing="Implied"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="LAS" title="_Load _accumulator, X register and _stack pointer with with memory anded stack pointer" proposal="LAS _" flags="N,Z" addressing="Absolute,Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="LAX" title="_Load _accumulator and _X register with memory" proposal="LAX _" flags="N,Z" addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="RLA" title="_Rotate one bit _left in memory, then and _accumulator with memory" proposal="RLA _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="RRA" title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)" proposal="RRA _" flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="SAX" title="_Store _accumulator anded with _X register" proposal="SAX _" flags="N,Z" addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="SLO" title="_Shift _left one bit in memory, then _or accumulator with memory" proposal="SLO _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="SRE" title="_Shift _right one bit in memory, then _eor accumulator with memory" proposal="SRE _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="SXA" title="_Store _X register _anded with high byte of the target address of the argument +1" proposal="SXA _" flags="-" addressing="Absolute,Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="SYA" title="_Store _Y register _anded with high byte of the target address of the argument +1" proposal="SYA _" flags="-" addressing="Absolute,x"/>
<illegalopcode cpus="MOS6502_ILLEGAL" name="XAS" title="Transfer _X register anded with _accumulator in stack pointer, then and stack pointer with the high byte of the target address of the argument +1. _Store result in memory." proposal="XAS _"
<illegalopcode targets="MOS6502_ILLEGAL" name="SAX" title="_Store _accumulator anded with _X register" proposal="SAX _" flags="N,Z" addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="SLO" title="_Shift _left one bit in memory, then _or accumulator with memory" proposal="SLO _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="SRE" title="_Shift _right one bit in memory, then _eor accumulator with memory" proposal="SRE _" flags="N,Z,C" addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="SXA" title="_Store _X register _anded with high byte of the target address of the argument +1" proposal="SXA _" flags="-" addressing="Absolute,Y"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="SYA" title="_Store _Y register _anded with high byte of the target address of the argument +1" proposal="SYA _" flags="-" addressing="Absolute,x"/>
<illegalopcode targets="MOS6502_ILLEGAL" name="XAS" title="Transfer _X register anded with _accumulator in stack pointer, then and stack pointer with the high byte of the target address of the argument +1. _Store result in memory." proposal="XAS _"
flags="-" addressing="Absolute,Y"/>
</instructionset>

126
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/compiler/dasm/DasmCompiler.xml
View File

@ -16,271 +16,271 @@
sourceIncludeDefaultExtension="">
<directive
cpus="*"
targets="*"
name="ALIGN"
title="_A_l_i_g_n program counter"
type="DIRECTIVE"
proposal="ALIGN _"/>
<directive
cpus="*"
targets="*"
name="BYTE"
title="Declare constant as _b_y_t_e"
type="DIRECTIVE"
proposal="BYTE _"/>
<directive
cpus="*"
targets="*"
name="DC"
title="_Declare _constant"
type="DIRECTIVE"
proposal="DC _"/>
<directive
cpus="*"
targets="*"
name="DC.B"
title="_Declare _constant as _byte"
type="DIRECTIVE"
proposal="DC.B _"/>
<directive
cpus="*"
targets="*"
name="DC.L"
title="_Declare _constant as _long"
type="DIRECTIVE"
proposal="DC.L _"/>
<directive
cpus="*"
targets="*"
name="DC.W"
title="_Declare _constant as _word"
type="DIRECTIVE"
proposal="DC.W _"/>
<directive
cpus="*"
targets="*"
name="DS"
title="_Declare _space"
type="DIRECTIVE"
proposal="DS _"/>
<directive
cpus="*"
targets="*"
name="DS.B"
title="_Declare _space in _bytes"
type="DIRECTIVE"
proposal="DS.B _"/>
<directive
cpus="*"
targets="*"
name="DS.L"
title="_Declare _space in _longs"
type="DIRECTIVE"
proposal="DS.L _"/>
<directive
cpus="*"
targets="*"
name="DS.W"
title="_Declare _space in _words"
type="DIRECTIVE"
proposal="DS.W _"/>
<directive
cpus="*"
targets="*"
name="DV"
title="_Declare _value"
type="DIRECTIVE"
proposal="DV _"/>
<directive
cpus="*"
targets="*"
name="DV.B"
title="_Declare _value as _byte"
type="DIRECTIVE"
proposal="DV.B _"/>
<directive
cpus="*"
targets="*"
name="DV.L"
title="_Declare _value as _long"
type="DIRECTIVE"
proposal="DV.L _"/>
<directive
cpus="*"
targets="*"
name="DV.W"
title="_Declare _value as _word"
type="DIRECTIVE"
proposal="DV.W _"/>
<directive
cpus="*"
targets="*"
name="ECHO"
title="_E_c_h_o"
type="DIRECTIVE"
proposal="ECHO _"/>
<directive
cpus="*"
targets="*"
name="EIF"
title="_End of _I_F"
type="END_FOLDING_BLOCK_DIRECTIVE"
proposal="EIF_"/>
<directive
cpus="*"
targets="*"
name="ELSE"
title="_E_l_s_e"
type="DIRECTIVE"
proposal="ELSE_"/>
<directive
cpus="*"
targets="*"
name="END"
title="_E_n_d assmbly"
type="DIRECTIVE"
proposal="END\n_"/>
<directive
cpus="*"
targets="*"
name="ENDIF"
title="_E_n_d of _I_F"
type="END_FOLDING_BLOCK_DIRECTIVE"
proposal="ENDIF_"/>
<directive
cpus="*"
targets="*"
name="ENDM"
title="_E_n_d of _macro"
type="END_SECTION_DIRECTIVE"
proposal="ENDM_"/>
<directive
cpus="*"
targets="*"
name="EQM"
title="Set _e_quate _macro"
type="DIRECTIVE"
proposal="EQM _"/>
<directive
cpus="*"
targets="*"
name="EQU"
title="Set _e_q_uate"
type="DIRECTIVE"
proposal="EQU _"/>
<directive
cpus="*"
targets="*"
name="ERR"
title="End assmbly with _e_r_ror"
type="DIRECTIVE"
proposal="ERR _"/>
<directive
cpus="*"
targets="*"
name="HEX"
title="Declare raw _h_e_x data"
type="DIRECTIVE"
proposal="HEX _"/>
<directive
cpus="*"
targets="*"
name="IF"
title="_I_f"
type="BEGIN_FOLDING_BLOCK_DIRECTIVE"
proposal="IF _\nENDIF"/>
<directive
cpus="*"
targets="*"
name="IFCONST"
title="_I_f _c_o_n_s_tant defined"
type="BEGIN_FOLDING_BLOCK_DIRECTIVE"
proposal="IFCONST _\nENDIF"/>
<directive
cpus="*"
targets="*"
name="IFNCONST"
title="_I_f _not _c_o_n_s_tant defined"
type="BEGIN_FOLDING_BLOCK_DIRECTIVE"
proposal="IFNCONST _\nENDIF"/>
<directive
cpus="*"
targets="*"
name="INCBIN"
title="_I_n_clude _b_i_nary file"
type="BINARY_INCLUDE_DIRECTIVE"
proposal="INCBIN &quot;_&quot;"/>
<directive
cpus="*"
targets="*"
name="INCDIR"
title="_I_n_clude _d_i_rectory"
type="DIRECTIVE"
proposal="INCDIR &quot;_&quot;"/>
<directive
cpus="*"
targets="*"
name="INCLUDE"
title="_I_n_c_l_u_d_e source file"
type="SOURCE_INCLUDE_DIRECTIVE"
proposal="INCLUDE &quot;_&quot;"/>
<directive
cpus="*"
targets="*"
name="LIST"
title="Turn _l_i_s_ting ON or OFF"
type="DIRECTIVE"
proposal="LIST _"/>
<directive
cpus="*"
targets="*"
name="LONG"
title="Declare constant as _l_o_n_g"
type="DIRECTIVE"
proposal="LONG _"/>
<directive
cpus="*"
targets="*"
name="MAC"
title="Define _m_a_cro"
type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE"
proposal="MAC _\nENDM _"/>
<directive
cpus="*"
targets="*"
name="MEXIT"
title="_Macro _e_x_i_t"
type="DIRECTIVE"
proposal="MEXIT_"/>
<directive
cpus="*"
targets="*"
name="ORG"
title="Set _o_ri_gin"
type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE"
proposal="ORG _"/>
<directive
cpus="*"
targets="*"
name="PROCESSOR"
title="Set _p_r_o_c_e_s_s_o_r model"
type="DIRECTIVE"
proposal="PROCESSOR 6502\n_"/>
<directive
cpus="*"
targets="*"
name="REND"
title="_Relocatable origin _e_n_d"
type="DIRECTIVE"
proposal="REND_"/>
<directive
cpus="*"
targets="*"
name="REPEAT"
title="Begin _r_e_p_e_a_t block"
type="BEGIN_REPEAT_SECTION_DIRECTIVE"
proposal="REPEAT _\nREPEND"/>
<directive
cpus="*"
targets="*"
name="REPEND"
title="_R_e_peat block _e_n_d"
type="END_SECTION_DIRECTIVE"
proposal="REPEND_"/>
<directive
cpus="*"
targets="*"
name="RORG"
title="Set _relocatable _o_ri_gin"
type="DIRECTIVE"
proposal="RORG _"/>
<directive
cpus="*"
targets="*"
name="SEG"
title="Start _s_e_gment"
type="DIRECTIVE"
proposal="SEG _"/>
<directive
cpus="*"
targets="*"
name="SEG.U"
title="Start _s_e_gment _uninitialized"
type="DIRECTIVE"
proposal="SEG.U _"/>
<directive
cpus="*"
targets="*"
name="SET"
title="_S_e_t redefinable symbol"
type="DIRECTIVE"
proposal="SET _"/>
<directive
cpus="*"
targets="*"
name="SUBROUTINE"
title="Begin _s_u_b_r_o_u_t_i_n_e"
type="DIRECTIVE"
proposal="SUBROUTINE\n_"/>
<directive
cpus="*"
targets="*"
name="WORD"
title="Declare constant as _w_o_r_d"
type="DIRECTIVE"
@ -288,125 +288,125 @@
<!-- Illegal opcodes are taken 1:1 from ATASM -->
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="ANC"
title="_A_nd byte with accumulator and set _carry"
proposal="ANC _"
flags="N,Z,C"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="ANE"
title="_A_nd X register with accumulator but _exact operation unknown"
proposal="ANE _"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="ARR"
title="_And byte with accumulator then _rotate one bit _right in accumulator"
proposal="ARR _"
flags="N,V,Z,C"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="DCP"
title="_De_crement memory by one and com_pare with memory"
proposal="DCP _"
flags="C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="ISB"
title="_Increase memory by one, then _subtract memory from accumulator (with _borrow)"
proposal="ISB _"
flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="LAS"
title="_Load _accumulator, X register and _stack pointer with with memory anded stack pointer"
proposal="LAS _"
flags="N,Z"
addressing="Absolute,Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="LAX"
title="_Load _accumulator and _X register with memory"
proposal="LAX _"
flags="N,Z"
addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="LXA"
title="And byte with accumulator, then _load value into _X register and _accumulator"
proposal="LXA _"
flags="N,Z"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="RLA"
title="_Rotate one bit _left in memory, then and _accumulator with memory"
proposal="RLA _"
flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="RRA"
title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)"
proposal="RRA _"
flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="SAX"
title="_Store _accumulator anded with _X register"
proposal="SAX _"
flags="N,Z"
addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="SBX"
title="_Subtract _byte from _X register (without borrow) after X register anded with the accumulator and store result in X register"
proposal="SBX _"
flags="N,Z,C"
addressing="Immediate"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="SHA"
title="_Store (don't know what _H is for) X register anded with _accumulator anded with 7"
proposal="SHA _"
flags="-"
addressing="Absolute,Y ;(Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="SHS"
title="And X register with accumulator and move to stack pointer. _Store _high byte of the target address of the argument +1 anded with _stack pointer"
proposal="SHS _"
flags="-"
addressing="Absolute,Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="SHX"
title="_Store _high byte of the target address of the argument +1 anded with _X register"
proposal="SHX _"
flags="-"
addressing="Absolute,Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="SHY"
title="_Store _high byte of the target address of the argument +1 anded with _Y register"
proposal="SHY _"
flags="-"
addressing="Absolute,x"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="SLO"
title="_Shift _left one bit in memory, then _or accumulator with memory"
proposal="SLO _"
flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y"/>
<illegalopcode
cpus="MOS6502_ILLEGAL"
targets="MOS6502_ILLEGAL"
name="SRE"
title="_Shift _right one bit in memory, then _eor accumulator with memory"
proposal="SRE _"

2
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/compiler/kickass/KickAssCompiler.txt
View File

@ -46,7 +46,7 @@
}
title = result.toString();
}
System.out.println(" <constant cpu=\"" + cpuString
System.out.println(" <constant target=\"" + cpuString
+ "\" name=\"" + name + "\" title=\"" + title
+ "\"/>");
}

636
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/compiler/kickass/KickAssCompiler.xml
View File

@ -4,51 +4,51 @@
identifierStartCharacters="_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz" identifierPartCharacters="_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" identifierSeparatorCharacter="." labelDefinitionSuffixCharacter=":"
macroUsagePrefixCharacter=":" instructionsCaseSensitive="true" sourceIncludeDefaultExtension="">
<directive cpus="*" name=".align" title="_A_l_i_g_n memory" type="DIRECTIVE" proposal=".align _"/>
<directive cpus="*" name=".assert" title="_A_s_s_e_r_t" type="DIRECTIVE" proposal=".assert _"/>
<directive cpus="*" name=".asserterror" title="_A_s_s_e_r_t _e_r_r_o_r" type="DIRECTIVE" proposal=".asserterror _"/>
<directive cpus="*" name=".by" title="Define _b_ytes" type="DIRECTIVE" proposal=".by _"/>
<directive cpus="*" name=".byte" title="Define _b_y_t_e" type="DIRECTIVE" proposal=".byte _"/>
<directive cpus="*" name=".const" title="Define _c_o_n_s_tants" type="DIRECTIVE" proposal=".const _"/>
<directive cpus="*" name=".define" title="_D_e_f_i_n_e symbols" type="DIRECTIVE" proposal=".define _"/>
<directive cpus="*" name=".dw" title="_Define _words" type="DIRECTIVE" proposal=".dw _"/>
<directive cpus="*" name=".dword" title="Define _double _w_o_r_ds" type="DIRECTIVE" proposal=".dword _"/>
<!-- Commented out intentionally <directive cpus="*" name=".easteregg"
<directive targets="*" name=".align" title="_A_l_i_g_n memory" type="DIRECTIVE" proposal=".align _"/>
<directive targets="*" name=".assert" title="_A_s_s_e_r_t" type="DIRECTIVE" proposal=".assert _"/>
<directive targets="*" name=".asserterror" title="_A_s_s_e_r_t _e_r_r_o_r" type="DIRECTIVE" proposal=".asserterror _"/>
<directive targets="*" name=".by" title="Define _b_ytes" type="DIRECTIVE" proposal=".by _"/>
<directive targets="*" name=".byte" title="Define _b_y_t_e" type="DIRECTIVE" proposal=".byte _"/>
<directive targets="*" name=".const" title="Define _c_o_n_s_tants" type="DIRECTIVE" proposal=".const _"/>
<directive targets="*" name=".define" title="_D_e_f_i_n_e symbols" type="DIRECTIVE" proposal=".define _"/>
<directive targets="*" name=".dw" title="_Define _words" type="DIRECTIVE" proposal=".dw _"/>
<directive targets="*" name=".dword" title="Define _double _w_o_r_ds" type="DIRECTIVE" proposal=".dword _"/>
<!-- Commented out intentionally <directive targets="*" name=".easteregg"
title="Create _e_a_s_t_e_r_e_g_g.prg file" type="DIRECTIVE" proposal=".easteregg
_"/> -->
<directive cpus="*" name="else" title="_E_l_s_e" type="DIRECTIVE" proposal="else_"/> <!-- "else" is considered part of the ".IF" directive -->
<directive cpus="*" name=".enum" title="Define _e_n_u_meration" type="BEGIN_ENUM_DEFINITION_SECTION_DIRECTIVE" proposal=".enum _"/>
<directive cpus="*" name=".error" title="Generate _e_r_r_o_r" type="DIRECTIVE" proposal=".error _"/>
<directive cpus="*" name=".eval" title="_E_v_a_luate expression" type="DIRECTIVE" proposal=".eval _"/>
<directive cpus="*" name=".filenamespace" title="Set _f_i_l_e _n_a_m_e_s_p_a_c_e" type="DIRECTIVE" proposal=".filenamespace _"/>
<directive cpus="*" name=".fill" title="_F_i_l_l memory with a given byte" type="DIRECTIVE" proposal=".fill _"/>
<directive cpus="*" name=".for" title="Begin _f_o_r loop" type="DIRECTIVE" proposal=".for _"/>
<directive cpus="*" name=".function" title="Define _f_u_n_c_t_i_o_n" type="DIRECTIVE" proposal=".function _"/>
<directive cpus="*" name=".if" title="_I_f" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal=".if _ {\n}"/>
<directive cpus="*" name=".import" title="_I_m_p_o_r_t contents of file" type="SOURCE_INCLUDE_DIRECTIVE" proposal=".import &quot;_&quot;"/> <!-- first argument is source/binary/c64/text -->
<directive cpus="*" name=".importonce" title="_I_m_p_o_r_t contents of file only _o_n_c_e" type="DIRECTIVE" proposal=".importonce_"/>
<directive cpus="*" name=".label" title="Define _l_a_b_e_l" type="DIRECTIVE" proposal=".label _"/>
<directive cpus="*" name=".macro" title="Define _m_a_c_r_o" type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE" proposal=".macro _ {\n.}"/>
<directive cpus="*" name=".namespace" title="Begin local _n_a_m_e_s_p_a_c_e block" type="BEGIN_LOCAL_SECTION_DIRECTIVE" proposal=".namespace _{\n}"/>
<directive cpus="*" name=".pc" title="Set _program _counter" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal=".pc = _"/>
<directive cpus="*" name=".print" title="_P_r_i_n_t string or value during output pass" type="DIRECTIVE" proposal=".print &quot;_&quot;"/>
<directive cpus="*" name=".printnow" title="_P_r_i_n_t string or value _n_o_w during current pass" type="DIRECTIVE" proposal=".printnow &quot;_&quot;"/>
<directive cpus="*" name=".pseudocommand" title="Define _p_s_e_u_d_o_c_o_m_m_a_n_d" type="DIRECTIVE" proposal=".pseudocommand _ {\n.}"/>
<directive cpus="*" name=".pseudopc" title="Set _p_s_e_u_d_o _program _counter" type="DIRECTIVE" proposal=".pseudopc = _"/>
<directive cpus="*" name=".return" title="_R_e_t_u_r_n value of a function" type="DIRECTIVE" proposal=".return _"/>
<directive cpus="*" name=".struct" title="Define _s_t_r_u_c_t" type="BEGIN_STRUCTURE_DEFINITION_SECTION_DIRECTIVE" proposal=".struct _ {\n}"/>
<directive cpus="*" name=".symbol" title="_S_y_m_b_o_l" type="DIRECTIVE" proposal=".symbol _"/>
<directive cpus="*" name=".te" title="Define _t_ext" type="DIRECTIVE" proposal=".te &quot;_&quot;"/>
<directive cpus="*" name=".text" title="Define _t_e_x_t" type="DIRECTIVE" proposal=".text &quot;_&quot;"/>
<directive cpus="*" name=".var" title="Define _v_a_riables" type="DIRECTIVE" proposal=".var_"/>
<directive cpus="*" name=".wo" title="Define _w_ords" type="DIRECTIVE" proposal=".wo _"/>
<directive cpus="*" name=".word" title="Define _w_o_r_ds" type="DIRECTIVE" proposal=".word _"/>
<directive targets="*" name="else" title="_E_l_s_e" type="DIRECTIVE" proposal="else_"/> <!-- "else" is considered part of the ".IF" directive -->
<directive targets="*" name=".enum" title="Define _e_n_u_meration" type="BEGIN_ENUM_DEFINITION_SECTION_DIRECTIVE" proposal=".enum _"/>
<directive targets="*" name=".error" title="Generate _e_r_r_o_r" type="DIRECTIVE" proposal=".error _"/>
<directive targets="*" name=".eval" title="_E_v_a_luate expression" type="DIRECTIVE" proposal=".eval _"/>
<directive targets="*" name=".filenamespace" title="Set _f_i_l_e _n_a_m_e_s_p_a_c_e" type="DIRECTIVE" proposal=".filenamespace _"/>
<directive targets="*" name=".fill" title="_F_i_l_l memory with a given byte" type="DIRECTIVE" proposal=".fill _"/>
<directive targets="*" name=".for" title="Begin _f_o_r loop" type="DIRECTIVE" proposal=".for _"/>
<directive targets="*" name=".function" title="Define _f_u_n_c_t_i_o_n" type="DIRECTIVE" proposal=".function _"/>
<directive targets="*" name=".if" title="_I_f" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal=".if _ {\n}"/>
<directive targets="*" name=".import" title="_I_m_p_o_r_t contents of file" type="SOURCE_INCLUDE_DIRECTIVE" proposal=".import &quot;_&quot;"/> <!-- first argument is source/binary/c64/text -->
<directive targets="*" name=".importonce" title="_I_m_p_o_r_t contents of file only _o_n_c_e" type="DIRECTIVE" proposal=".importonce_"/>
<directive targets="*" name=".label" title="Define _l_a_b_e_l" type="DIRECTIVE" proposal=".label _"/>
<directive targets="*" name=".macro" title="Define _m_a_c_r_o" type="BEGIN_MACRO_DEFINITION_SECTION_DIRECTIVE" proposal=".macro _ {\n.}"/>
<directive targets="*" name=".namespace" title="Begin local _n_a_m_e_s_p_a_c_e block" type="BEGIN_LOCAL_SECTION_DIRECTIVE" proposal=".namespace _{\n}"/>
<directive targets="*" name=".pc" title="Set _program _counter" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal=".pc = _"/>
<directive targets="*" name=".print" title="_P_r_i_n_t string or value during output pass" type="DIRECTIVE" proposal=".print &quot;_&quot;"/>
<directive targets="*" name=".printnow" title="_P_r_i_n_t string or value _n_o_w during current pass" type="DIRECTIVE" proposal=".printnow &quot;_&quot;"/>
<directive targets="*" name=".pseudocommand" title="Define _p_s_e_u_d_o_c_o_m_m_a_n_d" type="DIRECTIVE" proposal=".pseudocommand _ {\n.}"/>
<directive targets="*" name=".pseudopc" title="Set _p_s_e_u_d_o _program _counter" type="DIRECTIVE" proposal=".pseudopc = _"/>
<directive targets="*" name=".return" title="_R_e_t_u_r_n value of a function" type="DIRECTIVE" proposal=".return _"/>
<directive targets="*" name=".struct" title="Define _s_t_r_u_c_t" type="BEGIN_STRUCTURE_DEFINITION_SECTION_DIRECTIVE" proposal=".struct _ {\n}"/>
<directive targets="*" name=".symbol" title="_S_y_m_b_o_l" type="DIRECTIVE" proposal=".symbol _"/>
<directive targets="*" name=".te" title="Define _t_ext" type="DIRECTIVE" proposal=".te &quot;_&quot;"/>
<directive targets="*" name=".text" title="Define _t_e_x_t" type="DIRECTIVE" proposal=".text &quot;_&quot;"/>
<directive targets="*" name=".var" title="Define _v_a_riables" type="DIRECTIVE" proposal=".var_"/>
<directive targets="*" name=".wo" title="Define _w_ords" type="DIRECTIVE" proposal=".wo _"/>
<directive targets="*" name=".word" title="Define _w_o_r_ds" type="DIRECTIVE" proposal=".word _"/>
<!-- Build in high level directives ! -->
<directive cpus="*" name="LoadBinary" title="_L_o_a_d _b_i_n_a_r_y file" type="BINARY_INCLUDE_DIRECTIVE" proposal="LoadBinary(&quot;_&quot;)"/>
<directive cpus="*" name="LoadSid" title="_L_o_a_d _S_I_D module file" type="BINARY_INCLUDE_DIRECTIVE" proposal="LoadSid(&quot;_&quot;)"/>
<directive cpus="*" name="LoadPicture" title="_L_o_a_d _p_i_c_t_u_r_e file" type="BINARY_INCLUDE_DIRECTIVE" proposal="LoadPicture(&quot;_&quot;)"/>
<directive cpus="*" name="createFile" title="_C_r_e_a_t_e _f_i_l_e" type="BINARY_OUTPUT_DIRECTIVE" proposal="createFile(&quot;_&quot;)"/>
<directive targets="*" name="LoadBinary" title="_L_o_a_d _b_i_n_a_r_y file" type="BINARY_INCLUDE_DIRECTIVE" proposal="LoadBinary(&quot;_&quot;)"/>
<directive targets="*" name="LoadSid" title="_L_o_a_d _S_I_D module file" type="BINARY_INCLUDE_DIRECTIVE" proposal="LoadSid(&quot;_&quot;)"/>
<directive targets="*" name="LoadPicture" title="_L_o_a_d _p_i_c_t_u_r_e file" type="BINARY_INCLUDE_DIRECTIVE" proposal="LoadPicture(&quot;_&quot;)"/>
<directive targets="*" name="createFile" title="_C_r_e_a_t_e _f_i_l_e" type="BINARY_OUTPUT_DIRECTIVE" proposal="createFile(&quot;_&quot;)"/>
<!-- Other functions, maily operands used for expressions... TODO
abs
@ -99,302 +99,302 @@
-->
<!-- Scientific constants ! -->
<constant cpus="*" name="PI" title="_P_I=3.14159265"/>
<constant cpus="*" name="E" title="_e=2.71828183"/>
<constant targets="*" name="PI" title="_P_I=3.14159265"/>
<constant targets="*" name="E" title="_e=2.71828183"/>
<!-- Addressing mode constants ! -->
<constant cpus="*" name="AT_ABSOLUTE" title="_Addressing _type _a_b_s_o_l_u_t_e: $nnnn"/>
<constant cpus="*" name="AT_ABSOLUTEX" title="_Addressing _type _a_b_s_o_l_u_t_e, indexed with _X: $nnnn,x"/>
<constant cpus="*" name="AT_ABSOLUTEY" title="_Addressing _type _a_b_s_o_l_u_t_e, indexed with _Y: $nnnn,y"/>
<constant cpus="*" name="AT_IMMEDIATE" title="_Addressing _type _i_m_m_e_d_i_a_t_e: #$nn"/>
<constant cpus="*" name="AT_INDIRECT" title="_Addressing _type _i_n_d_i_r_e_c_t: ($nnnn)"/>
<constant cpus="*" name="AT_IZEROPAGEX" title="_Addressing _type _indirect _z_e_r_o _p_a_g_e, indexed with _X: ($nn,x)"/>
<constant cpus="*" name="AT_IZEROPAGEY" title="_Addressing _type _indirect _z_e_r_o _p_a_g_e, indexed with _Y: ($nn),y"/>
<constant cpus="*" name="AT_NONE" title="_Addressing _type _n_o_n_e"/>
<constant cpus="*" name="AT_ZEROPAGE" title="_Addressing _type _z_e_r_o _p_a_g_e, $nn"/>
<constant targets="*" name="AT_ABSOLUTE" title="_Addressing _type _a_b_s_o_l_u_t_e: $nnnn"/>
<constant targets="*" name="AT_ABSOLUTEX" title="_Addressing _type _a_b_s_o_l_u_t_e, indexed with _X: $nnnn,x"/>
<constant targets="*" name="AT_ABSOLUTEY" title="_Addressing _type _a_b_s_o_l_u_t_e, indexed with _Y: $nnnn,y"/>
<constant targets="*" name="AT_IMMEDIATE" title="_Addressing _type _i_m_m_e_d_i_a_t_e: #$nn"/>
<constant targets="*" name="AT_INDIRECT" title="_Addressing _type _i_n_d_i_r_e_c_t: ($nnnn)"/>
<constant targets="*" name="AT_IZEROPAGEX" title="_Addressing _type _indirect _z_e_r_o _p_a_g_e, indexed with _X: ($nn,x)"/>
<constant targets="*" name="AT_IZEROPAGEY" title="_Addressing _type _indirect _z_e_r_o _p_a_g_e, indexed with _Y: ($nn),y"/>
<constant targets="*" name="AT_NONE" title="_Addressing _type _n_o_n_e"/>
<constant targets="*" name="AT_ZEROPAGE" title="_Addressing _type _z_e_r_o _p_a_g_e, $nn"/>
<!-- C64 color constants ! -->
<constant cpus="*" name="BLACK" title="Color _b_l_a_c_k ($00)"/>
<constant cpus="*" name="BLUE" title="Color _b_l_u_e ($06)"/>
<constant cpus="*" name="BROWN" title="Color _b_r_o_w_n ($09)"/>
<constant cpus="*" name="CYAN" title="Color _c_y_a_n ($03)"/>
<constant cpus="*" name="DARK_GRAY" title="Color _d_a_r_k _g_r_a_y ($0b)"/>
<constant cpus="*" name="DARK_GREY" title="Color _d_a_r_k _g_r_e_y ($0b)"/>
<constant cpus="*" name="GRAY" title="Color _g_r_a_y ($0c)"/>
<constant cpus="*" name="GREEN" title="Color _g_r_e_e_n ($05)"/>
<constant cpus="*" name="GREY" title="Color _g_r_e_y ($0c)"/>
<constant cpus="*" name="LIGHT_BLUE" title="Color _l_i_g_h_t _b_l_u_e ($0e)"/>
<constant cpus="*" name="LIGHT_GRAY" title="Color _l_i_g_h_t _g_r_a_y ($0f)"/>
<constant cpus="*" name="LIGHT_GREEN" title="Color _l_i_g_h_t _g_r_e_e_n ($0d)"/>
<constant cpus="*" name="LIGHT_GREY" title="Color _l_i_g_h_t _g_r_e_y ($0f)"/>
<constant cpus="*" name="LIGHT_RED" title="Color _l_i_g_h_t _r_e_d ($0a)"/>
<constant cpus="*" name="ORANGE" title="Color _o_r_a_n_g_e ($08)"/>
<constant cpus="*" name="PURPLE" title="Color _p_u_r_p_l_e ($04)"/>
<constant cpus="*" name="RED" title="Color _r_e_d ($02)"/>
<constant cpus="*" name="WHITE" title="Color _w_h_i_t_e ($01)"/>
<constant cpus="*" name="YELLOW" title="Color _y_e_l_l_o_w ($07)"/>
<constant targets="*" name="BLACK" title="Color _b_l_a_c_k ($00)"/>
<constant targets="*" name="BLUE" title="Color _b_l_u_e ($06)"/>
<constant targets="*" name="BROWN" title="Color _b_r_o_w_n ($09)"/>
<constant targets="*" name="CYAN" title="Color _c_y_a_n ($03)"/>
<constant targets="*" name="DARK_GRAY" title="Color _d_a_r_k _g_r_a_y ($0b)"/>
<constant targets="*" name="DARK_GREY" title="Color _d_a_r_k _g_r_e_y ($0b)"/>
<constant targets="*" name="GRAY" title="Color _g_r_a_y ($0c)"/>
<constant targets="*" name="GREEN" title="Color _g_r_e_e_n ($05)"/>
<constant targets="*" name="GREY" title="Color _g_r_e_y ($0c)"/>
<constant targets="*" name="LIGHT_BLUE" title="Color _l_i_g_h_t _b_l_u_e ($0e)"/>
<constant targets="*" name="LIGHT_GRAY" title="Color _l_i_g_h_t _g_r_a_y ($0f)"/>
<constant targets="*" name="LIGHT_GREEN" title="Color _l_i_g_h_t _g_r_e_e_n ($0d)"/>
<constant targets="*" name="LIGHT_GREY" title="Color _l_i_g_h_t _g_r_e_y ($0f)"/>
<constant targets="*" name="LIGHT_RED" title="Color _l_i_g_h_t _r_e_d ($0a)"/>
<constant targets="*" name="ORANGE" title="Color _o_r_a_n_g_e ($08)"/>
<constant targets="*" name="PURPLE" title="Color _p_u_r_p_l_e ($04)"/>
<constant targets="*" name="RED" title="Color _r_e_d ($02)"/>
<constant targets="*" name="WHITE" title="Color _w_h_i_t_e ($01)"/>
<constant targets="*" name="YELLOW" title="Color _y_e_l_l_o_w ($07)"/>
<!-- C64 image type constants for "LoadBinary()" ! -->
<constant cpus="*" name="BF_C64FILE" title="_Binary _file format _C_6_4 program _f_i_l_e; the first two bytes are skipped"/>
<constant cpus="*" name="BF_KOALA" title="_Binary _file format _K_o_a_l_a Paint file"/>
<constant cpus="*" name="BF_FLI" title="_Binary _file format Blackmail _F_L_I editor file"/>
<constant cpus="*" name="BF_BITMAP_SINGLECOLOR" title="_Binary _file format Timanthes _b_i_t_m_a_p _s_i_n_g_l_e _c_o_l_o_r file"/>
<constant targets="*" name="BF_C64FILE" title="_Binary _file format _C_6_4 program _f_i_l_e; the first two bytes are skipped"/>
<constant targets="*" name="BF_KOALA" title="_Binary _file format _K_o_a_l_a Paint file"/>
<constant targets="*" name="BF_FLI" title="_Binary _file format Blackmail _F_L_I editor file"/>
<constant targets="*" name="BF_BITMAP_SINGLECOLOR" title="_Binary _file format Timanthes _b_i_t_m_a_p _s_i_n_g_l_e _c_o_l_o_r file"/>
<!-- Opcode constants for MOS6502 legal opcodes ! -->
<constant cpus="*" name="ADC_ABS" title="Opcode _A_D_C _a_b_solute"/>
<constant cpus="*" name="ADC_ABSX" title="Opcode _A_D_C _a_b_solute,_x"/>
<constant cpus="*" name="ADC_ABSY" title="Opcode _A_D_C _a_b_solute,_y"/>
<constant cpus="*" name="ADC_IMM" title="Opcode _A_D_C #_i_m_mediate"/>
<constant cpus="*" name="ADC_IZPX" title="Opcode _A_D_C (_indirect _zero_page,_x)"/>
<constant cpus="*" name="ADC_IZPY" title="Opcode _A_D_C (_indirect _zero_page),_y"/>
<constant cpus="*" name="ADC_ZP" title="Opcode _A_D_C _zero_page"/>
<constant cpus="*" name="ADC_ZPX" title="Opcode _A_D_C _zero_page,_x"/>
<constant cpus="*" name="AND_ABS" title="Opcode _A_N_D _a_b_solute"/>
<constant cpus="*" name="AND_ABSX" title="Opcode _A_N_D _a_b_solute,_x"/>
<constant cpus="*" name="AND_ABSY" title="Opcode _A_N_D _a_b_solute,_y"/>
<constant cpus="*" name="AND_IMM" title="Opcode _A_N_D #_i_m_mediate"/>
<constant cpus="*" name="AND_IZPX" title="Opcode _A_N_D (_indirect _zero_page,_x)"/>
<constant cpus="*" name="AND_IZPY" title="Opcode _A_N_D (_indirect _zero_page),_y"/>
<constant cpus="*" name="AND_ZP" title="Opcode _A_N_D _zero_page"/>
<constant cpus="*" name="AND_ZPX" title="Opcode _A_N_D _zero_page,_x"/>
<constant cpus="*" name="ASL" title="Opcode _A_S_L"/>
<constant cpus="*" name="ASL_ABS" title="Opcode _A_S_L _a_b_solute"/>
<constant cpus="*" name="ASL_ABSX" title="Opcode _A_S_L _a_b_solute,_x"/>
<constant cpus="*" name="ASL_ZP" title="Opcode _A_S_L _zero_page"/>
<constant cpus="*" name="ASL_ZPX" title="Opcode _A_S_L _zero_page,_x"/>
<constant cpus="*" name="BCC_REL" title="Opcode _B_C_C _r_e_lative"/>
<constant cpus="*" name="BCS_REL" title="Opcode _B_C_S _r_e_lative"/>
<constant cpus="*" name="BEQ_REL" title="Opcode _B_E_Q _r_e_lative"/>
<constant cpus="*" name="BIT_ABS" title="Opcode _B_I_T _a_b_solute"/>
<constant cpus="*" name="BIT_ABSX" title="Opcode _B_I_T _a_b_solute,_x"/>
<constant cpus="*" name="BIT_ZP" title="Opcode _B_I_T _zero_page"/>
<constant cpus="*" name="BIT_ZPX" title="Opcode _B_I_T _zero_page,_x"/>
<constant cpus="*" name="BMI_REL" title="Opcode _B_M_I _r_e_lative"/>
<constant cpus="*" name="BNE_REL" title="Opcode _B_N_E _r_e_lative"/>
<constant cpus="*" name="BPL_REL" title="Opcode _B_P_L _r_e_lative"/>
<constant cpus="*" name="BRK" title="Opcode _B_R_K"/>
<constant cpus="*" name="BVC_REL" title="Opcode _B_V_C _r_e_lative"/>
<constant cpus="*" name="BVS_REL" title="Opcode _B_V_S _r_e_lative"/>
<constant cpus="*" name="CLC" title="Opcode _C_L_C"/>
<constant cpus="*" name="CLD" title="Opcode _C_L_D"/>
<constant cpus="*" name="CLI" title="Opcode _C_L_I"/>
<constant cpus="*" name="CLV" title="Opcode _C_L_V"/>
<constant cpus="*" name="CMP_ABS" title="Opcode _C_M_P _a_b_solute"/>
<constant cpus="*" name="CMP_ABSX" title="Opcode _C_M_P _a_b_solute,_x"/>
<constant cpus="*" name="CMP_ABSY" title="Opcode _C_M_P _a_b_solute,_y"/>
<constant cpus="*" name="CMP_IMM" title="Opcode _C_M_P #_i_m_mediate"/>
<constant cpus="*" name="CMP_IZPX" title="Opcode _C_M_P (_indirect _zero_page,_x)"/>
<constant cpus="*" name="CMP_IZPY" title="Opcode _C_M_P (_indirect _zero_page),_y"/>
<constant cpus="*" name="CMP_ZP" title="Opcode _C_M_P _zero_page"/>
<constant cpus="*" name="CMP_ZPX" title="Opcode _C_M_P _zero_page,_x"/>
<constant cpus="*" name="CPX_ABS" title="Opcode _C_P_X _a_b_solute"/>
<constant cpus="*" name="CPX_IMM" title="Opcode _C_P_X #_i_m_mediate"/>
<constant cpus="*" name="CPX_ZP" title="Opcode _C_P_X _zero_page"/>
<constant cpus="*" name="CPY_ABS" title="Opcode _C_P_Y _a_b_solute"/>
<constant cpus="*" name="CPY_IMM" title="Opcode _C_P_Y #_i_m_mediate"/>
<constant cpus="*" name="CPY_ZP" title="Opcode _C_P_Y _zero_page"/>
<constant cpus="*" name="DEC_ABS" title="Opcode _D_E_C _a_b_solute"/>
<constant cpus="*" name="DEC_ABSX" title="Opcode _D_E_C _a_b_solute,_x"/>
<constant cpus="*" name="DEC_ZP" title="Opcode _D_E_C _zero_page"/>
<constant cpus="*" name="DEC_ZPX" title="Opcode _D_E_C _zero_page,_x"/>
<constant cpus="*" name="DEX" title="Opcode _D_E_X"/>
<constant cpus="*" name="DEY" title="Opcode _D_E_Y"/>
<constant cpus="*" name="EOR_ABS" title="Opcode _E_O_R _a_b_solute"/>
<constant cpus="*" name="EOR_ABSX" title="Opcode _E_O_R _a_b_solute,_x"/>
<constant cpus="*" name="EOR_ABSY" title="Opcode _E_O_R _a_b_solute,_y"/>
<constant cpus="*" name="EOR_IMM" title="Opcode _E_O_R #_i_m_mediate"/>
<constant cpus="*" name="EOR_IZPX" title="Opcode _E_O_R (_indirect _zero_page,_x)"/>
<constant cpus="*" name="EOR_IZPY" title="Opcode _E_O_R (_indirect _zero_page),_y"/>
<constant cpus="*" name="EOR_ZP" title="Opcode _E_O_R _zero_page"/>
<constant cpus="*" name="EOR_ZPX" title="Opcode _E_O_R _zero_page,_x"/>
<constant cpus="*" name="INC_ABS" title="Opcode _I_N_C _a_b_solute"/>
<constant cpus="*" name="INC_ABSX" title="Opcode _I_N_C _a_b_solute,_x"/>
<constant cpus="*" name="INC_ZP" title="Opcode _I_N_C _zero_page"/>
<constant cpus="*" name="INC_ZPX" title="Opcode _I_N_C _zero_page,_x"/>
<constant cpus="*" name="INX" title="Opcode _I_N_X"/>
<constant cpus="*" name="INY" title="Opcode _I_N_Y"/>
<constant cpus="*" name="JMP_ABS" title="Opcode _J_M_P _a_b_solute"/>
<constant cpus="*" name="JMP_IND" title="Opcode _J_M_P (_i_n_direct)"/>
<constant cpus="*" name="JSR_ABS" title="Opcode _J_S_R _a_b_solute"/>
<constant cpus="*" name="LDA_ABS" title="Opcode _L_D_A _a_b_solute"/>
<constant cpus="*" name="LDA_ABSX" title="Opcode _L_D_A _a_b_solute,_x"/>
<constant cpus="*" name="LDA_ABSY" title="Opcode _L_D_A _a_b_solute,_y"/>
<constant cpus="*" name="LDA_IMM" title="Opcode _L_D_A #_i_m_mediate"/>
<constant cpus="*" name="LDA_IZPX" title="Opcode _L_D_A (_indirect _zero_page,_x)"/>
<constant cpus="*" name="LDA_IZPY" title="Opcode _L_D_A (_indirect _zero_page),_y"/>
<constant cpus="*" name="LDA_ZP" title="Opcode _L_D_A _zero_page"/>
<constant cpus="*" name="LDA_ZPX" title="Opcode _L_D_A _zero_page,_x"/>
<constant cpus="*" name="LDX_ABS" title="Opcode _L_D_X _a_b_solute"/>
<constant cpus="*" name="LDX_ABSY" title="Opcode _L_D_X _a_b_solute,_y"/>
<constant cpus="*" name="LDX_IMM" title="Opcode _L_D_X #_i_m_mediate"/>
<constant cpus="*" name="LDX_ZP" title="Opcode _L_D_X _zero_page"/>
<constant cpus="*" name="LDX_ZPY" title="Opcode _L_D_X _zero_page,_y"/>
<constant cpus="*" name="LDY_ABS" title="Opcode _L_D_Y _a_b_solute"/>
<constant cpus="*" name="LDY_ABSX" title="Opcode _L_D_Y _a_b_solute,_x"/>
<constant cpus="*" name="LDY_IMM" title="Opcode _L_D_Y #_i_m_mediate"/>
<constant cpus="*" name="LDY_ZP" title="Opcode _L_D_Y _zero_page"/>
<constant cpus="*" name="LDY_ZPX" title="Opcode _L_D_Y _zero_page,_x"/>
<constant cpus="*" name="LSR" title="Opcode _L_S_R"/>
<constant cpus="*" name="LSR_ABS" title="Opcode _L_S_R _a_b_solute"/>
<constant cpus="*" name="LSR_ABSX" title="Opcode _L_S_R _a_b_solute,_x"/>
<constant cpus="*" name="LSR_ZP" title="Opcode _L_S_R _zero_page"/>
<constant cpus="*" name="LSR_ZPX" title="Opcode _L_S_R _zero_page,_x"/>
<constant cpus="*" name="NOP" title="Opcode _N_O_P"/>
<constant cpus="*" name="ORA_ABS" title="Opcode _O_R_A _a_b_solute"/>
<constant cpus="*" name="ORA_ABSX" title="Opcode _O_R_A _a_b_solute,_x"/>
<constant cpus="*" name="ORA_ABSY" title="Opcode _O_R_A _a_b_solute,_y"/>
<constant cpus="*" name="ORA_IMM" title="Opcode _O_R_A #_i_m_mediate"/>
<constant cpus="*" name="ORA_IZPX" title="Opcode _O_R_A (_indirect _zero_page,_x)"/>
<constant cpus="*" name="ORA_IZPY" title="Opcode _O_R_A (_indirect _zero_page),_y"/>
<constant cpus="*" name="ORA_ZP" title="Opcode _O_R_A _zero_page"/>
<constant cpus="*" name="ORA_ZPX" title="Opcode _O_R_A _zero_page,_x"/>
<constant cpus="*" name="PHA" title="Opcode _P_H_A"/>
<constant cpus="*" name="PHP" title="Opcode _P_H_P"/>
<constant cpus="*" name="PLA" title="Opcode _P_L_A"/>
<constant cpus="*" name="PLP" title="Opcode _P_L_P"/>
<constant cpus="*" name="ROL" title="Opcode _R_O_L"/>
<constant cpus="*" name="ROL_ABS" title="Opcode _R_O_L _a_b_solute"/>
<constant cpus="*" name="ROL_ABSX" title="Opcode _R_O_L _a_b_solute,_x"/>
<constant cpus="*" name="ROL_ZP" title="Opcode _R_O_L _zero_page"/>
<constant cpus="*" name="ROL_ZPX" title="Opcode _R_O_L _zero_page,_x"/>
<constant cpus="*" name="ROR" title="Opcode _R_O_R"/>
<constant cpus="*" name="ROR_ABS" title="Opcode _R_O_R _a_b_solute"/>
<constant cpus="*" name="ROR_ABSX" title="Opcode _R_O_R _a_b_solute,_x"/>
<constant cpus="*" name="ROR_ZP" title="Opcode _R_O_R _zero_page"/>
<constant cpus="*" name="ROR_ZPX" title="Opcode _R_O_R _zero_page,_x"/>
<constant cpus="*" name="RTI" title="Opcode _R_T_I"/>
<constant cpus="*" name="RTS" title="Opcode _R_T_S"/>
<constant cpus="*" name="SBC_ABS" title="Opcode _S_B_C _a_b_solute"/>
<constant cpus="*" name="SBC_ABSX" title="Opcode _S_B_C _a_b_solute,_x"/>
<constant cpus="*" name="SBC_ABSY" title="Opcode _S_B_C _a_b_solute,_y"/>
<constant cpus="*" name="SBC_IMM" title="Opcode _S_B_C #_i_m_mediate"/>
<constant cpus="*" name="SBC_IZPX" title="Opcode _S_B_C (_indirect _zero_page,_x)"/>
<constant cpus="*" name="SBC_IZPY" title="Opcode _S_B_C (_indirect _zero_page),_y"/>
<constant cpus="*" name="SBC_ZP" title="Opcode _S_B_C _zero_page"/>
<constant cpus="*" name="SBC_ZPX" title="Opcode _S_B_C _zero_page,_x"/>
<constant cpus="*" name="SEC" title="Opcode _S_E_C"/>
<constant cpus="*" name="SED" title="Opcode _S_E_D"/>
<constant cpus="*" name="SEI" title="Opcode _S_E_I"/>
<constant cpus="*" name="STA_ABS" title="Opcode _S_T_A _a_b_solute"/>
<constant cpus="*" name="STA_ABSX" title="Opcode _S_T_A _a_b_solute,_x"/>
<constant cpus="*" name="STA_ABSY" title="Opcode _S_T_A _a_b_solute,_y"/>
<constant cpus="*" name="STA_IZPX" title="Opcode _S_T_A (_indirect _zero_page,_x)"/>
<constant cpus="*" name="STA_IZPY" title="Opcode _S_T_A (_indirect _zero_page),_y"/>
<constant cpus="*" name="STA_ZP" title="Opcode _S_T_A _zero_page"/>
<constant cpus="*" name="STA_ZPX" title="Opcode _S_T_A _zero_page,_x"/>
<constant cpus="*" name="STX_ABS" title="Opcode _S_T_X _a_b_solute"/>
<constant cpus="*" name="STX_ZP" title="Opcode _S_T_X _zero_page"/>
<constant cpus="*" name="STX_ZPY" title="Opcode _S_T_X _zero_page,_y"/>
<constant cpus="*" name="STY_ABS" title="Opcode _S_T_Y _a_b_solute"/>
<constant cpus="*" name="STY_ZP" title="Opcode _S_T_Y _zero_page"/>
<constant cpus="*" name="STY_ZPX" title="Opcode _S_T_Y _zero_page,_x"/>
<constant cpus="*" name="TAX" title="Opcode _T_A_X"/>
<constant cpus="*" name="TAY" title="Opcode _T_A_Y"/>
<constant cpus="*" name="TSX" title="Opcode _T_S_X"/>
<constant cpus="*" name="TXA" title="Opcode _T_X_A"/>
<constant cpus="*" name="TXS" title="Opcode _T_X_S"/>
<constant cpus="*" name="TYA" title="Opcode _T_Y_A"/>
<constant targets="*" name="ADC_ABS" title="Opcode _A_D_C _a_b_solute"/>
<constant targets="*" name="ADC_ABSX" title="Opcode _A_D_C _a_b_solute,_x"/>
<constant targets="*" name="ADC_ABSY" title="Opcode _A_D_C _a_b_solute,_y"/>
<constant targets="*" name="ADC_IMM" title="Opcode _A_D_C #_i_m_mediate"/>
<constant targets="*" name="ADC_IZPX" title="Opcode _A_D_C (_indirect _zero_page,_x)"/>
<constant targets="*" name="ADC_IZPY" title="Opcode _A_D_C (_indirect _zero_page),_y"/>
<constant targets="*" name="ADC_ZP" title="Opcode _A_D_C _zero_page"/>
<constant targets="*" name="ADC_ZPX" title="Opcode _A_D_C _zero_page,_x"/>
<constant targets="*" name="AND_ABS" title="Opcode _A_N_D _a_b_solute"/>
<constant targets="*" name="AND_ABSX" title="Opcode _A_N_D _a_b_solute,_x"/>
<constant targets="*" name="AND_ABSY" title="Opcode _A_N_D _a_b_solute,_y"/>
<constant targets="*" name="AND_IMM" title="Opcode _A_N_D #_i_m_mediate"/>
<constant targets="*" name="AND_IZPX" title="Opcode _A_N_D (_indirect _zero_page,_x)"/>
<constant targets="*" name="AND_IZPY" title="Opcode _A_N_D (_indirect _zero_page),_y"/>
<constant targets="*" name="AND_ZP" title="Opcode _A_N_D _zero_page"/>
<constant targets="*" name="AND_ZPX" title="Opcode _A_N_D _zero_page,_x"/>
<constant targets="*" name="ASL" title="Opcode _A_S_L"/>
<constant targets="*" name="ASL_ABS" title="Opcode _A_S_L _a_b_solute"/>
<constant targets="*" name="ASL_ABSX" title="Opcode _A_S_L _a_b_solute,_x"/>
<constant targets="*" name="ASL_ZP" title="Opcode _A_S_L _zero_page"/>
<constant targets="*" name="ASL_ZPX" title="Opcode _A_S_L _zero_page,_x"/>
<constant targets="*" name="BCC_REL" title="Opcode _B_C_C _r_e_lative"/>
<constant targets="*" name="BCS_REL" title="Opcode _B_C_S _r_e_lative"/>
<constant targets="*" name="BEQ_REL" title="Opcode _B_E_Q _r_e_lative"/>
<constant targets="*" name="BIT_ABS" title="Opcode _B_I_T _a_b_solute"/>
<constant targets="*" name="BIT_ABSX" title="Opcode _B_I_T _a_b_solute,_x"/>
<constant targets="*" name="BIT_ZP" title="Opcode _B_I_T _zero_page"/>
<constant targets="*" name="BIT_ZPX" title="Opcode _B_I_T _zero_page,_x"/>
<constant targets="*" name="BMI_REL" title="Opcode _B_M_I _r_e_lative"/>
<constant targets="*" name="BNE_REL" title="Opcode _B_N_E _r_e_lative"/>
<constant targets="*" name="BPL_REL" title="Opcode _B_P_L _r_e_lative"/>
<constant targets="*" name="BRK" title="Opcode _B_R_K"/>
<constant targets="*" name="BVC_REL" title="Opcode _B_V_C _r_e_lative"/>
<constant targets="*" name="BVS_REL" title="Opcode _B_V_S _r_e_lative"/>
<constant targets="*" name="CLC" title="Opcode _C_L_C"/>
<constant targets="*" name="CLD" title="Opcode _C_L_D"/>
<constant targets="*" name="CLI" title="Opcode _C_L_I"/>
<constant targets="*" name="CLV" title="Opcode _C_L_V"/>
<constant targets="*" name="CMP_ABS" title="Opcode _C_M_P _a_b_solute"/>
<constant targets="*" name="CMP_ABSX" title="Opcode _C_M_P _a_b_solute,_x"/>
<constant targets="*" name="CMP_ABSY" title="Opcode _C_M_P _a_b_solute,_y"/>
<constant targets="*" name="CMP_IMM" title="Opcode _C_M_P #_i_m_mediate"/>
<constant targets="*" name="CMP_IZPX" title="Opcode _C_M_P (_indirect _zero_page,_x)"/>
<constant targets="*" name="CMP_IZPY" title="Opcode _C_M_P (_indirect _zero_page),_y"/>
<constant targets="*" name="CMP_ZP" title="Opcode _C_M_P _zero_page"/>
<constant targets="*" name="CMP_ZPX" title="Opcode _C_M_P _zero_page,_x"/>
<constant targets="*" name="CPX_ABS" title="Opcode _C_P_X _a_b_solute"/>
<constant targets="*" name="CPX_IMM" title="Opcode _C_P_X #_i_m_mediate"/>
<constant targets="*" name="CPX_ZP" title="Opcode _C_P_X _zero_page"/>
<constant targets="*" name="CPY_ABS" title="Opcode _C_P_Y _a_b_solute"/>
<constant targets="*" name="CPY_IMM" title="Opcode _C_P_Y #_i_m_mediate"/>
<constant targets="*" name="CPY_ZP" title="Opcode _C_P_Y _zero_page"/>
<constant targets="*" name="DEC_ABS" title="Opcode _D_E_C _a_b_solute"/>
<constant targets="*" name="DEC_ABSX" title="Opcode _D_E_C _a_b_solute,_x"/>
<constant targets="*" name="DEC_ZP" title="Opcode _D_E_C _zero_page"/>
<constant targets="*" name="DEC_ZPX" title="Opcode _D_E_C _zero_page,_x"/>
<constant targets="*" name="DEX" title="Opcode _D_E_X"/>
<constant targets="*" name="DEY" title="Opcode _D_E_Y"/>
<constant targets="*" name="EOR_ABS" title="Opcode _E_O_R _a_b_solute"/>
<constant targets="*" name="EOR_ABSX" title="Opcode _E_O_R _a_b_solute,_x"/>
<constant targets="*" name="EOR_ABSY" title="Opcode _E_O_R _a_b_solute,_y"/>
<constant targets="*" name="EOR_IMM" title="Opcode _E_O_R #_i_m_mediate"/>
<constant targets="*" name="EOR_IZPX" title="Opcode _E_O_R (_indirect _zero_page,_x)"/>
<constant targets="*" name="EOR_IZPY" title="Opcode _E_O_R (_indirect _zero_page),_y"/>
<constant targets="*" name="EOR_ZP" title="Opcode _E_O_R _zero_page"/>
<constant targets="*" name="EOR_ZPX" title="Opcode _E_O_R _zero_page,_x"/>
<constant targets="*" name="INC_ABS" title="Opcode _I_N_C _a_b_solute"/>
<constant targets="*" name="INC_ABSX" title="Opcode _I_N_C _a_b_solute,_x"/>
<constant targets="*" name="INC_ZP" title="Opcode _I_N_C _zero_page"/>
<constant targets="*" name="INC_ZPX" title="Opcode _I_N_C _zero_page,_x"/>
<constant targets="*" name="INX" title="Opcode _I_N_X"/>
<constant targets="*" name="INY" title="Opcode _I_N_Y"/>
<constant targets="*" name="JMP_ABS" title="Opcode _J_M_P _a_b_solute"/>
<constant targets="*" name="JMP_IND" title="Opcode _J_M_P (_i_n_direct)"/>
<constant targets="*" name="JSR_ABS" title="Opcode _J_S_R _a_b_solute"/>
<constant targets="*" name="LDA_ABS" title="Opcode _L_D_A _a_b_solute"/>
<constant targets="*" name="LDA_ABSX" title="Opcode _L_D_A _a_b_solute,_x"/>
<constant targets="*" name="LDA_ABSY" title="Opcode _L_D_A _a_b_solute,_y"/>
<constant targets="*" name="LDA_IMM" title="Opcode _L_D_A #_i_m_mediate"/>
<constant targets="*" name="LDA_IZPX" title="Opcode _L_D_A (_indirect _zero_page,_x)"/>
<constant targets="*" name="LDA_IZPY" title="Opcode _L_D_A (_indirect _zero_page),_y"/>
<constant targets="*" name="LDA_ZP" title="Opcode _L_D_A _zero_page"/>
<constant targets="*" name="LDA_ZPX" title="Opcode _L_D_A _zero_page,_x"/>
<constant targets="*" name="LDX_ABS" title="Opcode _L_D_X _a_b_solute"/>
<constant targets="*" name="LDX_ABSY" title="Opcode _L_D_X _a_b_solute,_y"/>
<constant targets="*" name="LDX_IMM" title="Opcode _L_D_X #_i_m_mediate"/>
<constant targets="*" name="LDX_ZP" title="Opcode _L_D_X _zero_page"/>
<constant targets="*" name="LDX_ZPY" title="Opcode _L_D_X _zero_page,_y"/>
<constant targets="*" name="LDY_ABS" title="Opcode _L_D_Y _a_b_solute"/>
<constant targets="*" name="LDY_ABSX" title="Opcode _L_D_Y _a_b_solute,_x"/>
<constant targets="*" name="LDY_IMM" title="Opcode _L_D_Y #_i_m_mediate"/>
<constant targets="*" name="LDY_ZP" title="Opcode _L_D_Y _zero_page"/>
<constant targets="*" name="LDY_ZPX" title="Opcode _L_D_Y _zero_page,_x"/>
<constant targets="*" name="LSR" title="Opcode _L_S_R"/>
<constant targets="*" name="LSR_ABS" title="Opcode _L_S_R _a_b_solute"/>
<constant targets="*" name="LSR_ABSX" title="Opcode _L_S_R _a_b_solute,_x"/>
<constant targets="*" name="LSR_ZP" title="Opcode _L_S_R _zero_page"/>
<constant targets="*" name="LSR_ZPX" title="Opcode _L_S_R _zero_page,_x"/>
<constant targets="*" name="NOP" title="Opcode _N_O_P"/>
<constant targets="*" name="ORA_ABS" title="Opcode _O_R_A _a_b_solute"/>
<constant targets="*" name="ORA_ABSX" title="Opcode _O_R_A _a_b_solute,_x"/>
<constant targets="*" name="ORA_ABSY" title="Opcode _O_R_A _a_b_solute,_y"/>
<constant targets="*" name="ORA_IMM" title="Opcode _O_R_A #_i_m_mediate"/>
<constant targets="*" name="ORA_IZPX" title="Opcode _O_R_A (_indirect _zero_page,_x)"/>
<constant targets="*" name="ORA_IZPY" title="Opcode _O_R_A (_indirect _zero_page),_y"/>
<constant targets="*" name="ORA_ZP" title="Opcode _O_R_A _zero_page"/>
<constant targets="*" name="ORA_ZPX" title="Opcode _O_R_A _zero_page,_x"/>
<constant targets="*" name="PHA" title="Opcode _P_H_A"/>
<constant targets="*" name="PHP" title="Opcode _P_H_P"/>
<constant targets="*" name="PLA" title="Opcode _P_L_A"/>
<constant targets="*" name="PLP" title="Opcode _P_L_P"/>
<constant targets="*" name="ROL" title="Opcode _R_O_L"/>
<constant targets="*" name="ROL_ABS" title="Opcode _R_O_L _a_b_solute"/>
<constant targets="*" name="ROL_ABSX" title="Opcode _R_O_L _a_b_solute,_x"/>
<constant targets="*" name="ROL_ZP" title="Opcode _R_O_L _zero_page"/>
<constant targets="*" name="ROL_ZPX" title="Opcode _R_O_L _zero_page,_x"/>
<constant targets="*" name="ROR" title="Opcode _R_O_R"/>
<constant targets="*" name="ROR_ABS" title="Opcode _R_O_R _a_b_solute"/>
<constant targets="*" name="ROR_ABSX" title="Opcode _R_O_R _a_b_solute,_x"/>
<constant targets="*" name="ROR_ZP" title="Opcode _R_O_R _zero_page"/>
<constant targets="*" name="ROR_ZPX" title="Opcode _R_O_R _zero_page,_x"/>
<constant targets="*" name="RTI" title="Opcode _R_T_I"/>
<constant targets="*" name="RTS" title="Opcode _R_T_S"/>
<constant targets="*" name="SBC_ABS" title="Opcode _S_B_C _a_b_solute"/>
<constant targets="*" name="SBC_ABSX" title="Opcode _S_B_C _a_b_solute,_x"/>
<constant targets="*" name="SBC_ABSY" title="Opcode _S_B_C _a_b_solute,_y"/>
<constant targets="*" name="SBC_IMM" title="Opcode _S_B_C #_i_m_mediate"/>
<constant targets="*" name="SBC_IZPX" title="Opcode _S_B_C (_indirect _zero_page,_x)"/>
<constant targets="*" name="SBC_IZPY" title="Opcode _S_B_C (_indirect _zero_page),_y"/>
<constant targets="*" name="SBC_ZP" title="Opcode _S_B_C _zero_page"/>
<constant targets="*" name="SBC_ZPX" title="Opcode _S_B_C _zero_page,_x"/>
<constant targets="*" name="SEC" title="Opcode _S_E_C"/>
<constant targets="*" name="SED" title="Opcode _S_E_D"/>
<constant targets="*" name="SEI" title="Opcode _S_E_I"/>
<constant targets="*" name="STA_ABS" title="Opcode _S_T_A _a_b_solute"/>
<constant targets="*" name="STA_ABSX" title="Opcode _S_T_A _a_b_solute,_x"/>
<constant targets="*" name="STA_ABSY" title="Opcode _S_T_A _a_b_solute,_y"/>
<constant targets="*" name="STA_IZPX" title="Opcode _S_T_A (_indirect _zero_page,_x)"/>
<constant targets="*" name="STA_IZPY" title="Opcode _S_T_A (_indirect _zero_page),_y"/>
<constant targets="*" name="STA_ZP" title="Opcode _S_T_A _zero_page"/>
<constant targets="*" name="STA_ZPX" title="Opcode _S_T_A _zero_page,_x"/>
<constant targets="*" name="STX_ABS" title="Opcode _S_T_X _a_b_solute"/>
<constant targets="*" name="STX_ZP" title="Opcode _S_T_X _zero_page"/>
<constant targets="*" name="STX_ZPY" title="Opcode _S_T_X _zero_page,_y"/>
<constant targets="*" name="STY_ABS" title="Opcode _S_T_Y _a_b_solute"/>
<constant targets="*" name="STY_ZP" title="Opcode _S_T_Y _zero_page"/>
<constant targets="*" name="STY_ZPX" title="Opcode _S_T_Y _zero_page,_x"/>
<constant targets="*" name="TAX" title="Opcode _T_A_X"/>
<constant targets="*" name="TAY" title="Opcode _T_A_Y"/>
<constant targets="*" name="TSX" title="Opcode _T_S_X"/>
<constant targets="*" name="TXA" title="Opcode _T_X_A"/>
<constant targets="*" name="TXS" title="Opcode _T_X_S"/>
<constant targets="*" name="TYA" title="Opcode _T_Y_A"/>
<!-- Opcodes and constants for MOS6502 illegal opcodes ! -->
<!-- anc2, sbc2, ... -->
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="AHX_ABSY" title="Opcode _A_H_X _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="AHX_IZPY" title="Opcode _A_H_X (_indirect _zero_page),_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ALR_IMM" title="Opcode _A_L_R #_i_m_mediate"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ANC2_IMM" title="Opcode _A_N_C_2 #_i_m_mediate"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ANC_IMM" title="Opcode _A_N_C #_i_m_mediate"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ARR_IMM" title="Opcode _A_R_R #_i_m_mediate"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="AXS_IMM" title="Opcode _A_X_S #_i_m_mediate"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ABS" title="Opcode _D_C_P _a_b_solute"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ABSX" title="Opcode _D_C_P _a_b_solute,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ABSY" title="Opcode _D_C_P _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_IZPX" title="Opcode _D_C_P (_indirect _zero_page,_x)"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_IZPY" title="Opcode _D_C_P (_indirect _zero_page),_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ZP" title="Opcode _D_C_P _zero_page"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ZPX" title="Opcode _D_C_P _zero_page,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ABS" title="Opcode _I_S_C _a_b_solute"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ABSX" title="Opcode _I_S_C _a_b_solute,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ABSY" title="Opcode _I_S_C _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_IZPX" title="Opcode _I_S_C (_indirect _zero_page,_x)"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_IZPY" title="Opcode _I_S_C (_indirect _zero_page),_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ZP" title="Opcode _I_S_C _zero_page"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ZPX" title="Opcode _I_S_C _zero_page,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAS_ABSY" title="Opcode _L_A_S _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_ABS" title="Opcode _L_A_X _a_b_solute"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_ABSY" title="Opcode _L_A_X _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_IMM" title="Opcode _L_A_X #_i_m_mediate"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_IZPX" title="Opcode _L_A_X (_indirect _zero_page,_x)"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_IZPY" title="Opcode _L_A_X (_indirect _zero_page),_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_ZP" title="Opcode _L_A_X _zero_page"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_ZPY" title="Opcode _L_A_X _zero_page,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ABS" title="Opcode _R_L_A _a_b_solute"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ABSX" title="Opcode _R_L_A _a_b_solute,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ABSY" title="Opcode _R_L_A _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_IZPX" title="Opcode _R_L_A (_indirect _zero_page,_x)"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_IZPY" title="Opcode _R_L_A (_indirect _zero_page),_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ZP" title="Opcode _R_L_A _zero_page"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ZPX" title="Opcode _R_L_A _zero_page,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ABS" title="Opcode _R_R_A _a_b_solute"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ABSX" title="Opcode _R_R_A _a_b_solute,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ABSY" title="Opcode _R_R_A _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_IZPX" title="Opcode _R_R_A (_indirect _zero_page,_x)"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_IZPY" title="Opcode _R_R_A (_indirect _zero_page),_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ZP" title="Opcode _R_R_A _zero_page"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ZPX" title="Opcode _R_R_A _zero_page,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX_ABS" title="Opcode _S_A_X _a_b_solute"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX_IZPX" title="Opcode _S_A_X (_indirect _zero_page,_x)"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX_ZP" title="Opcode _S_A_X _zero_page"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX_ZPY" title="Opcode _S_A_X _zero_page,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SBC2_IMM" title="Opcode _S_B_C_2 #_i_m_mediate"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SHX_ABSY" title="Opcode _S_H_X _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SHY_ABSX" title="Opcode _S_H_Y _a_b_solute,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ABS" title="Opcode _S_L_O _a_b_solute"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ABSX" title="Opcode _S_L_O _a_b_solute,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ABSY" title="Opcode _S_L_O _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_IZPX" title="Opcode _S_L_O (_indirect _zero_page,_x)"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_IZPY" title="Opcode _S_L_O (_indirect _zero_page),_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ZP" title="Opcode _S_L_O _zero_page"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ZPX" title="Opcode _S_L_O _zero_page,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ABS" title="Opcode _S_R_E _a_b_solute"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ABSX" title="Opcode _S_R_E _a_b_solute,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ABSY" title="Opcode _S_R_E _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_IZPX" title="Opcode _S_R_E (_indirect _zero_page,_x)"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_IZPY" title="Opcode _S_R_E (_indirect _zero_page),_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ZP" title="Opcode _S_R_E _zero_page"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ZPX" title="Opcode _S_R_E _zero_page,_x"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="TAS_ABSY" title="Opcode _T_A_S _a_b_solute,_y"/>
<constant cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="XAA_IMM" title="Opcode _X_A_A #_i_m_mediate"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="AHX_ABSY" title="Opcode _A_H_X _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="AHX_IZPY" title="Opcode _A_H_X (_indirect _zero_page),_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ALR_IMM" title="Opcode _A_L_R #_i_m_mediate"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ANC2_IMM" title="Opcode _A_N_C_2 #_i_m_mediate"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ANC_IMM" title="Opcode _A_N_C #_i_m_mediate"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ARR_IMM" title="Opcode _A_R_R #_i_m_mediate"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="AXS_IMM" title="Opcode _A_X_S #_i_m_mediate"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ABS" title="Opcode _D_C_P _a_b_solute"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ABSX" title="Opcode _D_C_P _a_b_solute,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ABSY" title="Opcode _D_C_P _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_IZPX" title="Opcode _D_C_P (_indirect _zero_page,_x)"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_IZPY" title="Opcode _D_C_P (_indirect _zero_page),_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ZP" title="Opcode _D_C_P _zero_page"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP_ZPX" title="Opcode _D_C_P _zero_page,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ABS" title="Opcode _I_S_C _a_b_solute"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ABSX" title="Opcode _I_S_C _a_b_solute,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ABSY" title="Opcode _I_S_C _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_IZPX" title="Opcode _I_S_C (_indirect _zero_page,_x)"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_IZPY" title="Opcode _I_S_C (_indirect _zero_page),_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ZP" title="Opcode _I_S_C _zero_page"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC_ZPX" title="Opcode _I_S_C _zero_page,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAS_ABSY" title="Opcode _L_A_S _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_ABS" title="Opcode _L_A_X _a_b_solute"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_ABSY" title="Opcode _L_A_X _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_IMM" title="Opcode _L_A_X #_i_m_mediate"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_IZPX" title="Opcode _L_A_X (_indirect _zero_page,_x)"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_IZPY" title="Opcode _L_A_X (_indirect _zero_page),_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_ZP" title="Opcode _L_A_X _zero_page"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX_ZPY" title="Opcode _L_A_X _zero_page,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ABS" title="Opcode _R_L_A _a_b_solute"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ABSX" title="Opcode _R_L_A _a_b_solute,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ABSY" title="Opcode _R_L_A _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_IZPX" title="Opcode _R_L_A (_indirect _zero_page,_x)"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_IZPY" title="Opcode _R_L_A (_indirect _zero_page),_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ZP" title="Opcode _R_L_A _zero_page"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA_ZPX" title="Opcode _R_L_A _zero_page,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ABS" title="Opcode _R_R_A _a_b_solute"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ABSX" title="Opcode _R_R_A _a_b_solute,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ABSY" title="Opcode _R_R_A _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_IZPX" title="Opcode _R_R_A (_indirect _zero_page,_x)"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_IZPY" title="Opcode _R_R_A (_indirect _zero_page),_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ZP" title="Opcode _R_R_A _zero_page"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA_ZPX" title="Opcode _R_R_A _zero_page,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX_ABS" title="Opcode _S_A_X _a_b_solute"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX_IZPX" title="Opcode _S_A_X (_indirect _zero_page,_x)"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX_ZP" title="Opcode _S_A_X _zero_page"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX_ZPY" title="Opcode _S_A_X _zero_page,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SBC2_IMM" title="Opcode _S_B_C_2 #_i_m_mediate"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SHX_ABSY" title="Opcode _S_H_X _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SHY_ABSX" title="Opcode _S_H_Y _a_b_solute,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ABS" title="Opcode _S_L_O _a_b_solute"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ABSX" title="Opcode _S_L_O _a_b_solute,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ABSY" title="Opcode _S_L_O _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_IZPX" title="Opcode _S_L_O (_indirect _zero_page,_x)"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_IZPY" title="Opcode _S_L_O (_indirect _zero_page),_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ZP" title="Opcode _S_L_O _zero_page"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO_ZPX" title="Opcode _S_L_O _zero_page,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ABS" title="Opcode _S_R_E _a_b_solute"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ABSX" title="Opcode _S_R_E _a_b_solute,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ABSY" title="Opcode _S_R_E _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_IZPX" title="Opcode _S_R_E (_indirect _zero_page,_x)"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_IZPY" title="Opcode _S_R_E (_indirect _zero_page),_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ZP" title="Opcode _S_R_E _zero_page"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE_ZPX" title="Opcode _S_R_E _zero_page,_x"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="TAS_ABSY" title="Opcode _T_A_S _a_b_solute,_y"/>
<constant targets="MOS6502_ILLEGAL,MOS6502_DTV" name="XAA_IMM" title="Opcode _X_A_A #_i_m_mediate"/>
<!-- Opcode constants for MOS6502_DTV ! -->
<constant cpus="MOS6502_DTV" name="BRA_REL" title="Opcode _B_R_A _r_e_lative"/>
<constant cpus="MOS6502_DTV" name="SAC_IMM" title="Opcode _S_A_C #_i_m_mediate"/>
<constant cpus="MOS6502_DTV" name="SIR_IMM" title="Opcode _S_I_R #_i_m_mediate"/>
<constant targets="MOS6502_DTV" name="BRA_REL" title="Opcode _B_R_A _r_e_lative"/>
<constant targets="MOS6502_DTV" name="SAC_IMM" title="Opcode _S_A_C #_i_m_mediate"/>
<constant targets="MOS6502_DTV" name="SIR_IMM" title="Opcode _S_I_R #_i_m_mediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ANC" title="_A_nd byte with accumulator and set _carry" proposal="ANC _" opcodes="$0b" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ANC2" title="_A_nd byte with accumulator and set _carry, _2nd opcode" proposal="ANC2 _" opcodes="$2b" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ARR" title="_And byte with accumulator then _rotate one bit _right in accumulator" opcodes="$6b" proposal="ARR _" flags="N,V,Z,C" addressing="Immediate"/>
<!--<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ATX" title="_And byte with accumulator, then _transfer accumulator to _X register" opcode="$cb" proposal="ATX _" flags="N,Z" addressing="Immediate"/>-->
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="AXS" title="_And _X register with accumulator and store result in X register, then _subtract byte from X register (without borrow)" proposal="AXS _" flags="N,Z,C" addressing="Immediate"/>
<!--<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="AX7" title="_And _X register with accumulator then and result with _7 and store in memory" proposal="AX7 _" flags="-" addressing="Absolute,Y ;(Indirect),Y"/> -->
<!-- <illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="AXE" title="_And _X register with accumulator but _exact operation unknown" proposal="AXE _" addressing="Immediate"/> -->
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP" title="_De_crement memory by one and com_pare with memory" proposal="DCP _" opcodes="$c7,$d7,$c3,$d3,$cf,$df,$db" flags="C"
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ANC" title="_A_nd byte with accumulator and set _carry" proposal="ANC _" opcodes="$0b" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ANC2" title="_A_nd byte with accumulator and set _carry, _2nd opcode" proposal="ANC2 _" opcodes="$2b" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ARR" title="_And byte with accumulator then _rotate one bit _right in accumulator" opcodes="$6b" proposal="ARR _" flags="N,V,Z,C" addressing="Immediate"/>
<!--<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ATX" title="_And byte with accumulator, then _transfer accumulator to _X register" opcode="$cb" proposal="ATX _" flags="N,Z" addressing="Immediate"/>-->
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="AXS" title="_And _X register with accumulator and store result in X register, then _subtract byte from X register (without borrow)" proposal="AXS _" flags="N,Z,C" addressing="Immediate"/>
<!--<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="AX7" title="_And _X register with accumulator then and result with _7 and store in memory" proposal="AX7 _" flags="-" addressing="Absolute,Y ;(Indirect),Y"/> -->
<!-- <illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="AXE" title="_And _X register with accumulator but _exact operation unknown" proposal="AXE _" addressing="Immediate"/> -->
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="DCP" title="_De_crement memory by one and com_pare with memory" proposal="DCP _" opcodes="$c7,$d7,$c3,$d3,$cf,$df,$db" flags="C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC" title="_Increase memory by one, then _subtract memory from accumulator (without _carry)" proposal="ISC _" opcodes="$e7,$f7,$e3,$f3,$ef,$ff,$fb" flags="N,V,Z,C"
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="ISC" title="_Increase memory by one, then _subtract memory from accumulator (without _carry)" proposal="ISC _" opcodes="$e7,$f7,$e3,$f3,$ef,$ff,$fb" flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<!-- <illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="JAM" title="_J_a_m processor, i.e. stop program counter" proposal="JAM_" flags="-" addressing="Implied"/> -->
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAS" title="_Load _accumulator, X register and _stack pointer with with memory anded stack pointer" proposal="LAS _" opcodes="$bb" flags="N,Z" addressing="Absolute,Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX" title="_Load _accumulator and _X register with memory" proposal="LAX _" opcodes="$ab,$a7,$b7,$a3,$b3,$af,$bf" flags="N,Z" addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA" title="_Rotate one bit _left in memory, then and _accumulator with memory" proposal="RLA _" opcodes="$27,$37,$23,$33,$2f,$3f,$3b" flags="N,Z,C"
<!-- <illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="JAM" title="_J_a_m processor, i.e. stop program counter" proposal="JAM_" flags="-" addressing="Implied"/> -->
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAS" title="_Load _accumulator, X register and _stack pointer with with memory anded stack pointer" proposal="LAS _" opcodes="$bb" flags="N,Z" addressing="Absolute,Y"/>
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="LAX" title="_Load _accumulator and _X register with memory" proposal="LAX _" opcodes="$ab,$a7,$b7,$a3,$b3,$af,$bf" flags="N,Z" addressing="Zero Page; Zero Page,Y; Absolute; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RLA" title="_Rotate one bit _left in memory, then and _accumulator with memory" proposal="RLA _" opcodes="$27,$37,$23,$33,$2f,$3f,$3b" flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA" title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)" proposal="RRA _" opcodes="$67,$77,$63,$73,$6f,$7f,$7b" flags="N,V,Z,C"
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="RRA" title="_Rotate one bit _right in memory, then add memory to _accumulator (with carry)" proposal="RRA _" opcodes="$67,$77,$63,$73,$6f,$7f,$7b" flags="N,V,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX" title="_Store _accumulator anded with _X register" proposal="SAX _" opcodes="$87,$97,$83,$8f" flags="N,Z" addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SBC2" title="_Su_btract from accumulator with _carry, _2nd opcode" proposal="SBC2 _" opcodes="$eb" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO" title="_Shift _left one bit in memory, then _or accumulator with memory" proposal="SLO _" opcodes="$07,$17,$03,$13,$0f,$1f,$1b" flags="N,Z,C"
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SAX" title="_Store _accumulator anded with _X register" proposal="SAX _" opcodes="$87,$97,$83,$8f" flags="N,Z" addressing="Zero Page;Zero Page,Y;(Indirect,X);Absolute"/>
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SBC2" title="_Su_btract from accumulator with _carry, _2nd opcode" proposal="SBC2 _" opcodes="$eb" flags="N,Z,C" addressing="Immediate"/>
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SLO" title="_Shift _left one bit in memory, then _or accumulator with memory" proposal="SLO _" opcodes="$07,$17,$03,$13,$0f,$1f,$1b" flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y; (Indirect,X); (Indirect),Y"/>
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE" title="_Shift _right one bit in memory, then _eor accumulator with memory" proposal="SRE _" opcodes="$47,$57,$43,$53,$4f,$5f,$5b" flags="N,Z,C"
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SRE" title="_Shift _right one bit in memory, then _eor accumulator with memory" proposal="SRE _" opcodes="$47,$57,$43,$53,$4f,$5f,$5b" flags="N,Z,C"
addressing="Zero Page; Zero Page,X; Absolute; Absolute,X; Absolute,Y;(Indirect,X);(Indirect),Y"/>
<!-- <illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SXA" title="_Store _X register _anded with high byte of the target address of the argument +1" proposal="SXA _" flags="-" addressing="Absolute,Y"/> -->
<!-- <illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="SYA" title="_Store _Y register _anded with high byte of the target address of the argument +1" proposal="SYA _" flags="-" addressing="Absolute,x"/> -->
<illegalopcode cpus="MOS6502_ILLEGAL,MOS6502_DTV" name="TAS" title="_Transfer X register anded with _accumulator in stack pointer, then and stack pointer with the high byte of the target address of the argument +1. _Store result in memory." proposal="TAS _"
<!-- <illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SXA" title="_Store _X register _anded with high byte of the target address of the argument +1" proposal="SXA _" flags="-" addressing="Absolute,Y"/> -->
<!-- <illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="SYA" title="_Store _Y register _anded with high byte of the target address of the argument +1" proposal="SYA _" flags="-" addressing="Absolute,x"/> -->
<illegalopcode targets="MOS6502_ILLEGAL,MOS6502_DTV" name="TAS" title="_Transfer X register anded with _accumulator in stack pointer, then and stack pointer with the high byte of the target address of the argument +1. _Store result in memory." proposal="TAS _"
opcodes="$9b" flags="-" addressing="Absolute,Y"/>
</instructionset>

312
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/compiler/mads/MadsCompiler.xml
View File

File diff suppressed because it is too large Load Diff

122
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/compiler/merlin32/Merlin32Compiler.xml
View File

@ -6,75 +6,75 @@
sourceIncludeDefaultExtension="s"
>
<!-- 6502 Pseudo Opcodes -->
<pseudoopcode cpus="*" name="BGE" title="_Branch _greater or _equal" proposal="BGE _"/>
<pseudoopcode cpus="*" name="BLT" title="_Branch _less _than" proposal="BLT _"/>
<pseudoopcode targets="*" name="BGE" title="_Branch _greater or _equal" proposal="BGE _"/>
<pseudoopcode targets="*" name="BLT" title="_Branch _less _than" proposal="BLT _"/>
<!-- 65816 Opcodes -->
<opcode cpus="MOS65816" name="ADCL" title="_A_dd to accumulator with _carry (_long)" proposal="ADCL _"
<opcode targets="MOS65816" name="ADCL" title="_A_dd to accumulator with _carry (_long)" proposal="ADCL _"
modes="idl=$67,abl=$6f,idly=$77,alx=$7f"/>
<opcode cpus="MOS65816" name="ANDL" title="Binary _a_n_d with accumulator (_long)" proposal="ANDL _"
<opcode targets="MOS65816" name="ANDL" title="Binary _a_n_d with accumulator (_long)" proposal="ANDL _"
modes="idl=$27,abl=$2f,idly=$37,alx=$3f"/>
<opcode cpus="MOS65816" name="CMPL" title="_Co_m_pare with accumulator (_long)" proposal="CMPL _"
<opcode targets="MOS65816" name="CMPL" title="_Co_m_pare with accumulator (_long)" proposal="CMPL _"
modes="idl=$c7,abl=$cf,idly=$d7,alx=$df"/>
<opcode cpus="MOS65816" name="EORL" title="Binary _exclusive-_o_r with accumulator (_long)" proposal="EORL _"
<opcode targets="MOS65816" name="EORL" title="Binary _exclusive-_o_r with accumulator (_long)" proposal="EORL _"
modes="idl=$47,abl=$4f,idly=$57,alx=$5f"/>
<opcode cpus="MOS65816" name="JMPL" title="_Ju_m_p to new address (_long)" proposal="JMPL _" modes="abl=$5c,ial=$7c"/>
<opcode cpus="MOS65816" name="JSRL" title="_Jump to _sub _routine (_long)" proposal="JSRL _" modes="abs=$22"/>
<opcode cpus="MOS65816" name="LDAL" title="_Loa_d _accumulator (_long)" proposal="LDAL _" modes="idl=$a7,ibl=$af,idly=$b7,alx=$bf"/>
<opcode cpus="MOS65816" name="ORAL" title="Binary _o_r with _accumulator (_long)" proposal="ORAL _"
<opcode targets="MOS65816" name="JMPL" title="_Ju_m_p to new address (_long)" proposal="JMPL _" modes="abl=$5c,ial=$7c"/>
<opcode targets="MOS65816" name="JSRL" title="_Jump to _sub _routine (_long)" proposal="JSRL _" modes="abs=$22"/>
<opcode targets="MOS65816" name="LDAL" title="_Loa_d _accumulator (_long)" proposal="LDAL _" modes="idl=$a7,ibl=$af,idly=$b7,alx=$bf"/>
<opcode targets="MOS65816" name="ORAL" title="Binary _o_r with _accumulator (_long)" proposal="ORAL _"
modes="idl=$07,abl=$0f,idl=$17,alx=$1f"/>
<opcode cpus="MOS65816" name="SBCL" title="_Su_btract from accumulator with _carry (_long)" proposal="SBCL _"
<opcode targets="MOS65816" name="SBCL" title="_Su_btract from accumulator with _carry (_long)" proposal="SBCL _"
modes="idl=$e7,abl=$ef,idly=$f7,alx=$ff"/>
<opcode cpus="MOS65816" name="STAL" title="_S_tore _accumulator in memory (_long)" proposal="STAL _"
<opcode targets="MOS65816" name="STAL" title="_S_tore _accumulator in memory (_long)" proposal="STAL _"
modes="idl=$87,abl=$8f,idly=$97,alx=$9f"/>
<!-- Directives -->
<directive cpus="*" name="ADR" title="Define _a_dd_ress" type="DIRECTIVE" proposal="ADR _"/>
<directive cpus="*" name="ADRL" title="Define _a_dd_ress (_long )" type="DIRECTIVE" proposal="ADRL _"/>
<directive cpus="*" name="ALI" title="Linker: Set boundary _a_l_ignment" type="DIRECTIVE" proposal="ALI _NONE/BANK/PAGE"/>
<directive cpus="*" name="ASC" title="Define _A_S_CII string" type="DIRECTIVE" proposal="ASC '_'"/>
<directive cpus="*" name="ASM" title="Linker: Set _a_sse_mbly file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="ASM '_'"/>
<directive cpus="*" name="AUX" title="Linker: Set GS/OS file _a_u_xiliary type" type="DIRECTIVE" proposal="AUX _"/>
<directive cpus="*" name="BSZ" title="Set _bank _si_ze" type="DIRECTIVE" proposal="BSZ _"/>
<directive cpus="*" name="CHK" title="Insert _c_hec_ksum" type="DIRECTIVE" proposal="CHK_"/>
<directive cpus="*" name="DA" title="_Define _address" type="DIRECTIVE" proposal="DA _"/>
<directive cpus="*" name="DAT" title="Insert current _d_a_te" type="DIRECTIVE" proposal="DAT _"/>
<directive cpus="*" name="DB" title="_Define _byte" type="DIRECTIVE" proposal="DB _"/>
<directive cpus="*" name="DCI" title="Define _dextral _character _inverted text" type="DIRECTIVE" proposal="DCI '_'"/>
<directive cpus="*" name="DDB" title="_Define _double _byte" type="DIRECTIVE" proposal="DDB _"/>
<directive cpus="*" name="DEND" title="_Dummy section _e_n_d" type="END_SECTION_DIRECTIVE" proposal="DEND_"/>
<directive cpus="*" name="DFB" title="_De_fine _byte" type="DIRECTIVE" proposal="DFB _"/>
<directive cpus="*" name="DO" title="_D_o if expression not zero" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="DO _\nFIN"/>
<directive cpus="*" name="DS" title="_Define _storage" type="DIRECTIVE" proposal="DS _"/>
<directive cpus="*" name="DSK" title="Set _di_s_k binary output file" type="BINARY_OUTPUT_DIRECTIVE" proposal="DSK '_'"/>
<directive cpus="*" name="DUM" title="_D_u_mmy section" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal="DUM _\nDEND"/>
<directive cpus="*" name="DW" title="_Define _word" type="DIRECTIVE" proposal="DW _"/>
<directive cpus="*" name="ELSE" title="_E_l_s_e" type="DIRECTIVE" proposal="ELSE_"/>
<directive cpus="*" name="END" title="_E_n_d assembly" type="DIRECTIVE" proposal="END_"/>
<directive cpus="*" name="ENT" title="Define label as an _e_n_try label in a REL Segment" type="DIRECTIVE" proposal="ENT_"/>
<directive cpus="*" name="EQU" title="Define _e_q_uate" type="DIRECTIVE" proposal="EQU _"/>
<directive cpus="*" name="ERR" title="Force _e_r_ror if expression not zero" type="DIRECTIVE" proposal="ERR _"/>
<directive cpus="*" name="EXT" title="Define label as _e_x_ternal to the current REL segment" type="DIRECTIVE"
<directive targets="*" name="ADR" title="Define _a_dd_ress" type="DIRECTIVE" proposal="ADR _"/>
<directive targets="*" name="ADRL" title="Define _a_dd_ress (_long )" type="DIRECTIVE" proposal="ADRL _"/>
<directive targets="*" name="ALI" title="Linker: Set boundary _a_l_ignment" type="DIRECTIVE" proposal="ALI _NONE/BANK/PAGE"/>
<directive targets="*" name="ASC" title="Define _A_S_CII string" type="DIRECTIVE" proposal="ASC '_'"/>
<directive targets="*" name="ASM" title="Linker: Set _a_sse_mbly file" type="SOURCE_INCLUDE_DIRECTIVE" proposal="ASM '_'"/>
<directive targets="*" name="AUX" title="Linker: Set GS/OS file _a_u_xiliary type" type="DIRECTIVE" proposal="AUX _"/>
<directive targets="*" name="BSZ" title="Set _bank _si_ze" type="DIRECTIVE" proposal="BSZ _"/>
<directive targets="*" name="CHK" title="Insert _c_hec_ksum" type="DIRECTIVE" proposal="CHK_"/>
<directive targets="*" name="DA" title="_Define _address" type="DIRECTIVE" proposal="DA _"/>
<directive targets="*" name="DAT" title="Insert current _d_a_te" type="DIRECTIVE" proposal="DAT _"/>
<directive targets="*" name="DB" title="_Define _byte" type="DIRECTIVE" proposal="DB _"/>
<directive targets="*" name="DCI" title="Define _dextral _character _inverted text" type="DIRECTIVE" proposal="DCI '_'"/>
<directive targets="*" name="DDB" title="_Define _double _byte" type="DIRECTIVE" proposal="DDB _"/>
<directive targets="*" name="DEND" title="_Dummy section _e_n_d" type="END_SECTION_DIRECTIVE" proposal="DEND_"/>
<directive targets="*" name="DFB" title="_De_fine _byte" type="DIRECTIVE" proposal="DFB _"/>
<directive targets="*" name="DO" title="_D_o if expression not zero" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="DO _\nFIN"/>
<directive targets="*" name="DS" title="_Define _storage" type="DIRECTIVE" proposal="DS _"/>
<directive targets="*" name="DSK" title="Set _di_s_k binary output file" type="BINARY_OUTPUT_DIRECTIVE" proposal="DSK '_'"/>
<directive targets="*" name="DUM" title="_D_u_mmy section" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal="DUM _\nDEND"/>
<directive targets="*" name="DW" title="_Define _word" type="DIRECTIVE" proposal="DW _"/>
<directive targets="*" name="ELSE" title="_E_l_s_e" type="DIRECTIVE" proposal="ELSE_"/>
<directive targets="*" name="END" title="_E_n_d assembly" type="DIRECTIVE" proposal="END_"/>
<directive targets="*" name="ENT" title="Define label as an _e_n_try label in a REL Segment" type="DIRECTIVE" proposal="ENT_"/>
<directive targets="*" name="EQU" title="Define _e_q_uate" type="DIRECTIVE" proposal="EQU _"/>
<directive targets="*" name="ERR" title="Force _e_r_ror if expression not zero" type="DIRECTIVE" proposal="ERR _"/>
<directive targets="*" name="EXT" title="Define label as _e_x_ternal to the current REL segment" type="DIRECTIVE"
proposal="EXT_"/>
<directive cpus="*" name="FIN" title="_F _i_nish IF or DO" type="END_FOLDING_BLOCK_DIRECTIVE" proposal="FIN_"/>
<directive cpus="*" name="FLS" title="Define _f_la_shing text" type="DIRECTIVE" proposal="FLS '_'"/>
<directive cpus="*" name="HEX" title="Define _h_e_xadecimal data" type="DIRECTIVE" proposal="HEX _"/>
<directive cpus="*" name="IF" title="Do _i_f expression not zero" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="IF _\nFIN"/>
<directive cpus="*" name="INV" title="Define _i_n_verse text" type="DIRECTIVE" proposal="INV '_'"/>
<directive cpus="*" name="KND" title="Linker: Set segment _ki_n_d and attributes" type="DIRECTIVE" proposal="KND _"/>
<directive cpus="*" name="LNA" title="Linker: Set _load segment _n_ame" type="DIRECTIVE" proposal="LNA '_'"/>
<directive cpus="*" name="LNK" title="Set _li_n_ker binary output file" type="BINARY_OUTPUT_DIRECTIVE" proposal="LNK '_'"/>
<directive cpus="*" name="LUP" title="Begin loop (_l_uu_p) block" type="BEGIN_REPEAT_SECTION_DIRECTIVE" proposal="LUP _"/>
<directive cpus="MOS65816" name="MX" title="Set _M and _X register size" type="DIRECTIVE" proposal="MX _"/>
<directive cpus="*" name="ORG" title="Set _o_ri_gin" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal="ORG _"/>
<directive cpus="*" name="PMC" title="_Put _macro _call" type="DIRECTIVE" proposal="PMC _"/>
<directive cpus="*" name="PUT" title="_P_u_t source include file at this location" type="SOURCE_INCLUDE_DIRECTIVE" proposal="PUT '_'"/>
<directive cpus="*" name="PUTBIN" title="_P_u_t _b_i_nary include file at this location" type="BINARY_INCLUDE_DIRECTIVE" proposal="PUTBIN '_'"/>
<directive cpus="*" name="REL" title="Activate _r_e_locatable mode" type="DIRECTIVE" proposal="REL_"/>
<directive cpus="*" name="REV" title="Define _r_e_verse text" type="DIRECTIVE" proposal="REV '_'"/>
<directive cpus="*" name="SAV" title="_S_a_ve output binary file" type="BINARY_OUTPUT_DIRECTIVE" proposal="SAV '_'"/>
<directive cpus="*" name="SNA" title="Linker: Set _segment _n_ame" type="DIRECTIVE" proposal="SNA '_'"/>
<directive cpus="*" name="STR" title="Define _s_t_ring with leading length byte" type="DIRECTIVE" proposal="STR '_'"/>
<directive cpus="*" name="STRL" title="Define _s_t_ring with leading length word (_long)" type="DIRECTIVE" proposal="STRL '_'"/>
<directive cpus="*" name="TYP" title="Set ProDOS output file _t_y_pe " type="DIRECTIVE" proposal="TYP $06_"/>
<directive cpus="*" name="USE" title ="_U_s_e source include file at this location" type="SOURCE_INCLUDE_DIRECTIVE" proposal="USE '_'"/>
<directive cpus="*" name="XPL" title="Linker: Add E_x_press_Load segment" type="DIRECTIVE" proposal="XPL_"/>
<directive targets="*" name="FIN" title="_F _i_nish IF or DO" type="END_FOLDING_BLOCK_DIRECTIVE" proposal="FIN_"/>
<directive targets="*" name="FLS" title="Define _f_la_shing text" type="DIRECTIVE" proposal="FLS '_'"/>
<directive targets="*" name="HEX" title="Define _h_e_xadecimal data" type="DIRECTIVE" proposal="HEX _"/>
<directive targets="*" name="IF" title="Do _i_f expression not zero" type="BEGIN_FOLDING_BLOCK_DIRECTIVE" proposal="IF _\nFIN"/>
<directive targets="*" name="INV" title="Define _i_n_verse text" type="DIRECTIVE" proposal="INV '_'"/>
<directive targets="*" name="KND" title="Linker: Set segment _ki_n_d and attributes" type="DIRECTIVE" proposal="KND _"/>
<directive targets="*" name="LNA" title="Linker: Set _load segment _n_ame" type="DIRECTIVE" proposal="LNA '_'"/>
<directive targets="*" name="LNK" title="Set _li_n_ker binary output file" type="BINARY_OUTPUT_DIRECTIVE" proposal="LNK '_'"/>
<directive targets="*" name="LUP" title="Begin loop (_l_uu_p) block" type="BEGIN_REPEAT_SECTION_DIRECTIVE" proposal="LUP _"/>
<directive targets="MOS65816" name="MX" title="Set _M and _X register size" type="DIRECTIVE" proposal="MX _"/>
<directive targets="*" name="ORG" title="Set _o_ri_gin" type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE" proposal="ORG _"/>
<directive targets="*" name="PMC" title="_Put _macro _call" type="DIRECTIVE" proposal="PMC _"/>
<directive targets="*" name="PUT" title="_P_u_t source include file at this location" type="SOURCE_INCLUDE_DIRECTIVE" proposal="PUT '_'"/>
<directive targets="*" name="PUTBIN" title="_P_u_t _b_i_nary include file at this location" type="BINARY_INCLUDE_DIRECTIVE" proposal="PUTBIN '_'"/>
<directive targets="*" name="REL" title="Activate _r_e_locatable mode" type="DIRECTIVE" proposal="REL_"/>
<directive targets="*" name="REV" title="Define _r_e_verse text" type="DIRECTIVE" proposal="REV '_'"/>
<directive targets="*" name="SAV" title="_S_a_ve output binary file" type="BINARY_OUTPUT_DIRECTIVE" proposal="SAV '_'"/>
<directive targets="*" name="SNA" title="Linker: Set _segment _n_ame" type="DIRECTIVE" proposal="SNA '_'"/>
<directive targets="*" name="STR" title="Define _s_t_ring with leading length byte" type="DIRECTIVE" proposal="STR '_'"/>
<directive targets="*" name="STRL" title="Define _s_t_ring with leading length word (_long)" type="DIRECTIVE" proposal="STRL '_'"/>
<directive targets="*" name="TYP" title="Set ProDOS output file _t_y_pe " type="DIRECTIVE" proposal="TYP $06_"/>
<directive targets="*" name="USE" title ="_U_s_e source include file at this location" type="SOURCE_INCLUDE_DIRECTIVE" proposal="USE '_'"/>
<directive targets="*" name="XPL" title="Linker: Add E_x_press_Load segment" type="DIRECTIVE" proposal="XPL_"/>
</instructionset>

94
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/compiler/xasm/XasmCompiler.xml
View File

@ -15,252 +15,252 @@
sourceIncludeDefaultExtension="asx">
<directive
cpus="*"
targets="*"
name="DTA"
title="Define _da_t_a"
type="DIRECTIVE"
proposal="DTA _"/>
<directive
cpus="*"
targets="*"
name="EIF"
title="_End _i_f"
type="BEGIN_FOLDING_BLOCK_DIRECTIVE"
proposal="EIF_"/>
<directive
cpus="*"
targets="*"
name="ELI"
title="_E_lse _if"
type="END_FOLDING_BLOCK_DIRECTIVE"
proposal="ELI _"/>
<directive
cpus="*"
targets="*"
name="ELS"
title="_E_l_se"
type="DIRECTIVE"
proposal="ELS _"/>
<directive
cpus="*"
targets="*"
name="END"
title="_E_n_d block or assembly"
type="END_SECTION_DIRECTIVE"
proposal="END_"/>
<directive
cpus="*"
targets="*"
name="EQU"
title="Set _e_q_uate"
type="DIRECTIVE"
proposal="EQU _"/>
<directive
cpus="*"
targets="*"
name="ERT"
title="_E_rror if _true"
type="DIRECTIVE"
proposal="ERT _"/>
<directive
cpus="*"
targets="*"
name="ICL"
title="_In_c_lude another source file"
type="SOURCE_INCLUDE_DIRECTIVE"
proposal="ICL &quot;_&quot;"/>
<directive
cpus="*"
targets="*"
name="IFT"
title="_I_f _true"
type="BEGIN_FOLDING_BLOCK_DIRECTIVE"
proposal="IFT _"/>
<directive
cpus="*"
targets="*"
name="INI"
title="Set _i_n_it address"
type="DIRECTIVE"
proposal="INI _"/>
<directive
cpus="*"
targets="*"
name="INS"
title="_I_n_sert contents of file"
type="BINARY_INCLUDE_DIRECTIVE"
proposal="INS &quot;_&quot;"/>
<directive
cpus="*"
targets="*"
name="OPT"
title="Set assembly _o_p_tions"
type="DIRECTIVE"
proposal="OPT _"/>
<directive
cpus="*"
targets="*"
name="ORG"
title="Set _o_ri_gin"
type="BEGIN_IMPLEMENTATION_SECTION_DIRECTIVE"
proposal="ORG _"/>
<directive
cpus="*"
targets="*"
name="RUN"
title="Set _r_u_n address"
type="DIRECTIVE"
proposal="RUN _"/>
<pseudoopcode
cpus="*"
targets="*"
name="ADD"
title="_A_d_d to accumulator without carry"
proposal="ADD _"/>
<pseudoopcode
cpus="*"
targets="*"
name="INW"
title="_I_ncrement _word by one"
proposal="INW _"/>
<pseudoopcode
cpus="*"
targets="*"
name="JCC"
title="_Jump if _carry _clear"
proposal="JCC _"/>
<pseudoopcode
cpus="*"
targets="*"
name="JCS"
title="_Jump if _carry _set"
proposal="JCS _"/>
<pseudoopcode
cpus="*"
targets="*"
name="JEQ"
title="_Jump if _e_qual / zero"
proposal="JEQ _"/>
<pseudoopcode
cpus="*"
targets="*"
name="JMI"
title="_Jump if _m_inus"
proposal="JMI _"/>
<pseudoopcode
cpus="*"
targets="*"
name="JNE"
title="_Jump if _not _equal / zero"
proposal="JNE _"/>
<pseudoopcode
cpus="*"
targets="*"
name="JPL"
title="_Jump if _p_lus"
proposal="JPL _"/>
<pseudoopcode
cpus="*"
targets="*"
name="JVC"
title="_Jump if o_verflow _clear"
proposal="JVC _"/>
<pseudoopcode
cpus="*"
targets="*"
name="JVS"
title="_Jump if o_verflow _set"
proposal="JVS _"/>
<pseudoopcode
cpus="*"
targets="*"
name="MVA"
title="_Mo_ve byte using _accumulator"
proposal="MVA _"/>
<pseudoopcode
cpus="*"
targets="*"
name="MVX"
title="_Mo_ve byte using _X register"
proposal="MVX _"/>
<pseudoopcode
cpus="*"
targets="*"
name="MVY"
title="_Mo_ve byte using _Y register"
proposal="MVY _"/>
<pseudoopcode
cpus="*"
targets="*"
name="MWA"
title="_Move _word using _accumulator"
proposal="MWA _"/>
<pseudoopcode
cpus="*"
targets="*"
name="MWX"
title="_Move _word using _X register"
proposal="MWX _"/>
<pseudoopcode
cpus="*"
targets="*"
name="MWY"
title="_Move _word using _Y register"
proposal="MWY _"/>
<pseudoopcode
cpus="*"
targets="*"
name="RCC"
title="_Repeat if _carry _clear"
proposal="RCC _"/>
<pseudoopcode
cpus="*"
targets="*"
name="RCS"
title="_Repeat if _carry _set"
proposal="RCS _"/>
<pseudoopcode
cpus="*"
targets="*"
name="REQ"
title="_Repeat if _e_qual / zero"
proposal="REQ _"/>
<pseudoopcode
cpus="*"
targets="*"
name="RMI"
title="_Repeat if _m_inus"
proposal="RMI _"/>
<pseudoopcode
cpus="*"
targets="*"
name="RNE"
title="_Repeat if _not _equal / zero"
proposal="RNE _"/>
<pseudoopcode
cpus="*"
targets="*"
name="RPL"
title="_Repeat if _p_lus"
proposal="RPL _"/>
<pseudoopcode
cpus="*"
targets="*"
name="RVC"
title="_Repeat if o_verflow _clear"
proposal="RVC _"/>
<pseudoopcode
cpus="*"
targets="*"
name="RVS"
title="_Repeat if o_verflow _set"
proposal="RVS _"/>
<pseudoopcode
cpus="*"
targets="*"
name="SCC"
title="_Skip if _carry _clear"
proposal="SCC _"/>
<pseudoopcode
cpus="*"
targets="*"
name="SCS"
title="_Skip if _carry _set"
proposal="SCS _"/>
<pseudoopcode
cpus="*"
targets="*"
name="SEQ"
title="_Skip if _e_qual / zero"
proposal="SEQ _"/>
<pseudoopcode
cpus="*"
targets="*"
name="SMI"
title="_Skip if _m_inus"
proposal="SMI _"/>
<pseudoopcode
cpus="*"
targets="*"
name="SNE"
title="_Skip if _not _equal / zero"
proposal="SNE _"/>
<pseudoopcode
cpus="*"
targets="*"
name="SPL"
title="_Skip if _p_lus"
proposal="SPL _"/>
<pseudoopcode
cpus="*"
targets="*"
name="SUB"
title="_S_u_btract from accumulator without carry"
proposal="SUB _"/>
<pseudoopcode
cpus="*"
targets="*"
name="SVC"
title="_Skip if o_verflow _clear"
proposal="SVC _"/>
<pseudoopcode
cpus="*"
targets="*"
name="SVS"
title="_Skip if o_verflow _set"
proposal="SVS _"/>

7
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/preferences/AssemblerPreferencesApple2CompilersPage.java
View File

@ -19,7 +19,8 @@
package com.wudsn.ide.lng.asm.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding Apple 2 compilers.
@ -27,13 +28,13 @@ import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
* @author Peter Dell
*
*/
public final class AssemblerPreferencesApple2CompilersPage extends AssemblerPreferencesCompilersPage {
public final class AssemblerPreferencesApple2CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public AssemblerPreferencesApple2CompilersPage() {
super(Hardware.APPLE2);
super(Language.ASM, Hardware.APPLE2);
}

7
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/preferences/AssemblerPreferencesAtari2600CompilersPage.java
View File

@ -19,7 +19,8 @@
package com.wudsn.ide.lng.asm.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding Apple 2 compilers.
@ -27,13 +28,13 @@ import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
* @author Peter Dell
*
*/
public final class AssemblerPreferencesAtari2600CompilersPage extends AssemblerPreferencesCompilersPage {
public final class AssemblerPreferencesAtari2600CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public AssemblerPreferencesAtari2600CompilersPage() {
super(Hardware.ATARI2600);
super(Language.ASM,Hardware.ATARI2600);
}

7
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/preferences/AssemblerPreferencesAtari7800CompilersPage.java
View File

@ -19,7 +19,8 @@
package com.wudsn.ide.lng.asm.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding Apple 2 compilers.
@ -27,13 +28,13 @@ import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
* @author Peter Dell
*
*/
public final class AssemblerPreferencesAtari7800CompilersPage extends AssemblerPreferencesCompilersPage {
public final class AssemblerPreferencesAtari7800CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public AssemblerPreferencesAtari7800CompilersPage() {
super(Hardware.ATARI7800);
super(Language.ASM, Hardware.ATARI7800);
}

7
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/preferences/AssemblerPreferencesAtari8CompilersPage.java
View File

@ -19,7 +19,8 @@
package com.wudsn.ide.lng.asm.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding Atari 8-bit
@ -28,13 +29,13 @@ import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
* @author Peter Dell
*
*/
public final class AssemblerPreferencesAtari8CompilersPage extends AssemblerPreferencesCompilersPage {
public final class AssemblerPreferencesAtari8CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public AssemblerPreferencesAtari8CompilersPage() {
super(Hardware.ATARI8BIT);
super(Language.ASM,Hardware.ATARI8BIT);
}

7
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/preferences/AssemblerPreferencesC64CompilersPage.java
View File

@ -19,7 +19,8 @@
package com.wudsn.ide.lng.asm.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding C64 compilers.
@ -27,13 +28,13 @@ import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
* @author Peter Dell
*
*/
public final class AssemblerPreferencesC64CompilersPage extends AssemblerPreferencesCompilersPage {
public final class AssemblerPreferencesC64CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public AssemblerPreferencesC64CompilersPage() {
super(Hardware.C64);
super(Language.ASM, Hardware.C64);
}

7
com.wudsn.ide.asm.compilers/src/com/wudsn/ide/lng/asm/preferences/AssemblerPreferencesNESCompilersPage.java
View File

@ -19,7 +19,8 @@
package com.wudsn.ide.lng.asm.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding NES compilers.
@ -27,13 +28,13 @@ import com.wudsn.ide.lng.preferences.AssemblerPreferencesCompilersPage;
* @author Peter Dell
*
*/
public final class AssemblerPreferencesNESCompilersPage extends AssemblerPreferencesCompilersPage {
public final class AssemblerPreferencesNESCompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public AssemblerPreferencesNESCompilersPage() {
super(Hardware.NES);
super(Language.ASM,Hardware.NES);
}

10
com.wudsn.ide.asm/OSGI-INF/l10n/bundle.properties
View File

@ -7,11 +7,11 @@ com.wudsn.ide.lng.Hardware.C64=C64
com.wudsn.ide.lng.Hardware.NES=NES
com.wudsn.ide.lng.Hardware.TEST=Test
com.wudsn.ide.lng.CPU.MOS6502=6502
com.wudsn.ide.lng.CPU.MOS6502_ILLEGAL=6502 with illegal opcodes
com.wudsn.ide.lng.CPU.MOS65C02=65C02
com.wudsn.ide.lng.CPU.MOS6502_DTV=6502 DTV
com.wudsn.ide.lng.CPU.MOS65816=65816
com.wudsn.ide.lng.Target.MOS6502=6502
com.wudsn.ide.lng.Target.MOS6502_ILLEGAL=6502 with illegal opcodes
com.wudsn.ide.lng.Target.MOS65C02=65C02
com.wudsn.ide.lng.Target.MOS6502_DTV=6502 DTV
com.wudsn.ide.lng.Target.MOS65816=65816
com.wudsn.ide.lng.compiler.AssemblerSourceFile.name=Assembler Source File

10
com.wudsn.ide.asm/OSGI-INF/l10n/bundle_de_DE.properties
View File

@ -7,11 +7,11 @@ com.wudsn.ide.lng.Hardware.C64=C64
com.wudsn.ide.lng.Hardware.NES=NES
com.wudsn.ide.lng.Hardware.TEST=Test
com.wudsn.ide.lng.CPU.MOS6502=6502
com.wudsn.ide.lng.CPU.MOS6502_ILLEGAL=6502 mit illegalen Opcodes
com.wudsn.ide.lng.CPU.MOS65C02=65C02
com.wudsn.ide.lng.CPU.MOS6502_DTV=6502 DTV
com.wudsn.ide.lng.CPU.MOS65816=65816
com.wudsn.ide.lng.Target.MOS6502=6502
com.wudsn.ide.lng.Target.MOS6502_ILLEGAL=6502 mit illegalen Opcodes
com.wudsn.ide.lng.Target.MOS65C02=65C02
com.wudsn.ide.lng.Target.MOS6502_DTV=6502 DTV
com.wudsn.ide.lng.Target.MOS65816=65816
com.wudsn.ide.lng.compiler.AssemblerSourceFile.name=Assembler Quell-Datei

4
com.wudsn.ide.asm/schema/compilers.exsd
View File

@ -139,9 +139,9 @@
</complexType>
</element>
<element name="supportedCPU">
<element name="supportedTarget">
<complexType>
<attribute name="cpu">
<attribute name="target">
<annotation>
<documentation>

144
com.wudsn.ide.asm/schema/runners.exsd Normal file
View File

@ -0,0 +1,144 @@
<?xml version='1.0' encoding='UTF-8'?>
<!-- Schema file written by PDE -->
<schema targetNamespace="com.wudsn.ide.lng" xmlns="http://www.w3.org/2001/XMLSchema">
<annotation>
<appInfo>
<meta.schema plugin="com.wudsn.ide.lng" id="runners" name="Runner"/>
</appInfo>
<documentation>
This extension point allows for adding new runner, for example runners, to the WUDSN IDE.
</documentation>
</annotation>
<element name="extension">
<annotation>
<appInfo>
<meta.element />
</appInfo>
</annotation>
<complexType>
<sequence minOccurs="1" maxOccurs="unbounded">
<element ref="runner"/>
</sequence>
<attribute name="point" type="string" use="required">
<annotation>
<documentation>
</documentation>
</annotation>
</attribute>
<attribute name="id" type="string">
<annotation>
<documentation>
</documentation>
</annotation>
</attribute>
<attribute name="name" type="string">
<annotation>
<documentation>
</documentation>
<appInfo>
<meta.attribute translatable="true"/>
</appInfo>
</annotation>
</attribute>
</complexType>
</element>
<element name="runner">
<complexType>
<attribute name="hardware" use="required">
<annotation>
<documentation>
</documentation>
</annotation>
<simpleType>
<restriction base="string">
<enumeration value="APPLE2">
</enumeration>
<enumeration value="ATARI2600">
</enumeration>
<enumeration value="ATARI7800">
</enumeration>
<enumeration value="ATARI8BIT">
</enumeration>
<enumeration value="C64">
</enumeration>
<enumeration value="GENERIC">
</enumeration>
<enumeration value="NES">
</enumeration>
<enumeration value="TEST">
</enumeration>
</restriction>
</simpleType>
</attribute>
<attribute name="id" type="string" use="required">
<annotation>
<documentation>
</documentation>
</annotation>
</attribute>
<attribute name="name" type="string" use="required">
<annotation>
<documentation>
</documentation>
<appInfo>
<meta.attribute translatable="true"/>
</appInfo>
</annotation>
</attribute>
<attribute name="class" type="string">
<annotation>
<documentation>
Optional implementation class to provide runner specific breakouts, for example for creating breakpoint files.
</documentation>
<appInfo>
<meta.attribute kind="java" basedOn="com.wudsn.ide.lng.runner.Runner:"/>
</appInfo>
</annotation>
</attribute>
<attribute name="homePageURL" type="string">
<annotation>
<documentation>
</documentation>
</annotation>
</attribute>
<attribute name="defaultCommandLine" type="string">
<annotation>
<documentation>
</documentation>
</annotation>
</attribute>
</complexType>
</element>
<annotation>
<appInfo>
<meta.section type="since"/>
</appInfo>
<documentation>
WUDSN IDE 1.3.0
</documentation>
</annotation>
<annotation>
<appInfo>
<meta.section type="copyright"/>
</appInfo>
<documentation>
(c) 2009 Peter Dell
</documentation>
</annotation>
</schema>

1
com.wudsn.ide.asm/src/com/wudsn/ide/lng/HardwareUtility.java
View File

@ -27,6 +27,7 @@ import com.wudsn.ide.lng.compiler.writer.AppleFileWriter;
*
* @author Peter Dell
*
* TODO: Move to right place/class
*/
public final class HardwareUtility {

30
com.wudsn.ide.asm/src/com/wudsn/ide/lng/Language.java Normal file
View File

@ -0,0 +1,30 @@
/**
* Copyright (C) 2009 - 2021 <a href="https://www.wudsn.com" target="_top">Peter Dell</a>
*
* This file is part of WUDSN IDE.
*
* WUDSN IDE is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* WUDSN IDE is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.lng;
/**
* Enum for the hardware platforms.
*
* @author Peter Dell
*
*/
public enum Language {
ASM, PAS
}

2
com.wudsn.ide.asm/src/com/wudsn/ide/lng/CPU.java → com.wudsn.ide.asm/src/com/wudsn/ide/lng/Target.java
View File

@ -25,7 +25,7 @@ package com.wudsn.ide.lng;
*
* @since 1.6.1
*/
public enum CPU {
public enum Target {
MOS6502, MOS6502_ILLEGAL, MOS65C02, MOS6502_DTV, MOS65816
}

2
com.wudsn.ide.asm/src/com/wudsn/ide/lng/Texts.java
View File

@ -170,7 +170,7 @@ public final class Texts extends NLS {
/**
* Preferences: compiler.
*/
public static String PREFERENCES_COMPILER_CPU_LABEL;
public static String PREFERENCES_COMPILER_TARGET_LABEL;
public static String PREFERENCES_COMPILER_EXECUTABLE_PATH_LABEL;
public static String PREFERENCES_COMPILER_HARDWARE_ACTIVE_LABEL;

10
com.wudsn.ide.asm/src/com/wudsn/ide/lng/Texts.properties
View File

@ -89,7 +89,7 @@ PREFERENCES_ITALIC_LABEL=&Italic
PREFERENCES_DOWNLOAD_LINK=Download
PREFERENCES_DOWNLOAD_LINK_TOOL_TIP=Open download page {0}
PREFERENCES_COMPILER_CPU_LABEL=CP&U
PREFERENCES_COMPILER_TARGET_LABEL=&Target
PREFERENCES_COMPILER_EXECUTABLE_PATH_LABEL=Path to &Compiler
PREFERENCES_COMPILER_HARDWARE_ACTIVE_LABEL=Use for {0}
PREFERENCES_COMPILER_DEFAULT_PARAMETERS_LABEL=&Default Parameters
@ -119,7 +119,7 @@ TOC_ASSEMBLER_GENERAL_TOPIC_LABEL=General
TOC_ASSEMBLER_NAME_LABEL=Name
TOC_ASSEMBLER_HOME_PAGE_LABEL=Home Page
TOC_ASSEMBLER_DEFAULT_HARDWARE_LABEL=Default Hardware
TOC_ASSEMBLER_SUPPORTED_CPUS_LABEL=Supported CPUs
TOC_ASSEMBLER_SUPPORTED_TARGETS_LABEL=Supported Targets
TOC_ASSEMBLER_DEFAULT_PARAMETERS_LABEL=Default Parameters
TOC_ASSEMBLER_INSTRUCTIONS_TOPIC_LABEL=Instructions
TOC_ASSEMBLER_INSTRUCTION_TYPE_DIRECTIVES_LABEL=Directives
@ -156,9 +156,9 @@ TOC_HARDWARE_EMULATOR_LABEL=Emulator
TOC_HARDWARE_HOME_PAGE_LABEL=Home Page
TOC_HARDWARE_DEFAULT_PARAMETERS_LABEL=Default Parameters
TOC_CPUS_TOPIC_LABEL=CPUs
TOC_CPU_NAME_LABEL=CPU
TOC_CPU_OPCODE_LABEL=Opcode
TOC_TARGETS_TOPIC_LABEL=Targets
TOC_TARGETS_NAME_LABEL=Target
TOC_TARGET_OPCODE_LABEL=Opcode
MESSAGE_E100=Path to '{0}' compiler executable is not set in the 'Assembler' preferences.
MESSAGE_E101=The compiler '{0}' does not specify default parameters.

10
com.wudsn.ide.asm/src/com/wudsn/ide/lng/Texts_de_DE.properties
View File

@ -87,7 +87,7 @@ PREFERENCES_ITALIC_LABEL=&Kursiv
PREFERENCES_DOWNLOAD_LINK=Download
PREFERENCES_DOWNLOAD_LINK_TOOL_TIP=Webseite {0} für Download öffnen
PREFERENCES_COMPILER_CPU_LABEL=CP&U
PREFERENCES_COMPILER_TARGET_LABEL=&Ziel
PREFERENCES_COMPILER_EXECUTABLE_PATH_LABEL=Pfad zum &Kompiler
PREFERENCES_COMPILER_HARDWARE_ACTIVE_LABEL=Verwenden für {0}
PREFERENCES_COMPILER_DEFAULT_PARAMETERS_LABEL=&Standardparameter
@ -117,7 +117,7 @@ TOC_ASSEMBLER_GENERAL_TOPIC_LABEL=Allgemein
TOC_ASSEMBLER_NAME_LABEL=Name
TOC_ASSEMBLER_HOME_PAGE_LABEL=Home Page
TOC_ASSEMBLER_DEFAULT_HARDWARE_LABEL=Standardhardware
TOC_ASSEMBLER_SUPPORTED_CPUS_LABEL=Unterstütze CPUs
TOC_ASSEMBLER_SUPPORTED_TARGETS_LABEL=Unterstütze Ziele
TOC_ASSEMBLER_DEFAULT_PARAMETERS_LABEL=Standardparameter
TOC_ASSEMBLER_INSTRUCTIONS_TOPIC_LABEL=Befehle
TOC_ASSEMBLER_INSTRUCTION_TYPE_DIRECTIVES_LABEL=Direktiven
@ -154,9 +154,9 @@ TOC_HARDWARE_EMULATOR_LABEL=Emulator
TOC_HARDWARE_HOME_PAGE_LABEL=Home Page
TOC_HARDWARE_DEFAULT_PARAMETERS_LABEL=Standardparameter
TOC_CPUS_TOPIC_LABEL=CPUs
TOC_CPU_NAME_LABEL=CPU
TOC_CPU_OPCODE_LABEL=Opcode
TOC_TARGETS_TOPIC_LABEL=Ziele
TOC_TARGET_NAME_LABEL=Ziel
TOC_TARGET_OPCODE_LABEL=Opcode
MESSAGE_E100=Pfad zur ausführbaren Datei des Kompilers '{0}' ist in den 'Assembler' Voreinstellungen nicht angegeben.
MESSAGE_E101=Der Kompiler '{0}' definiert keine Standardparameter.

186
com.wudsn.ide.asm/src/com/wudsn/ide/lng/compiler/Compiler.xml
View File

@ -4,110 +4,108 @@
<!-- See http://www.65xx.com/wdc/documentation/w65c816s.pdf for the description of the 16bit opcodes. -->
<!-- http://www.westerndesigncenter.com/wdc/datasheets/Programmanual.pdf -->
<opcodes>
<!-- Common legal 6502 opcodes used by all compilers -->
<!-- 6502 addressing modes: imm, zp, zpx, zpy, izx, izy, abs, abx, aby, ind, rel -->
<!-- 65816 addressing modes: sr,dp,dpx,dpy,idp,idx,idy,idl,idly,isy,abl,alx,ind,iax,ial,rell,bm -->
<opcode cpus="MOS6502*,MOS65816" name="ADC" title="_A_dd to accumulator with _carry" proposal="ADC _" modes="imm=$69,zp=$65,zpx=$75,izx=$61,izy=$71,abs=$6d,abx=$7d,aby=$79"/>
<opcode cpus="MOS6502*,MOS65816" name="AND" title="Binary _a_n_d with accumulator" proposal="AND _" modes="imm=$29,zp=$25,zpx=$35,izx=$21,izy=$31,abs=$2d,abx=$3d,aby=$39"/>
<opcode cpus="MOS6502*,MOS65816" name="ASL" title="_Arithmetic _shift _left" proposal="ASL_" modes="imp=$0a,zp=$06,zpx=$16,abs=$0e,abx=$1e"/>
<opcode cpus="MOS6502*,MOS65816" name="BCC" title="_Branch on _carry _clear" proposal="BCC _" modes="rel=$90"/>
<opcode cpus="MOS6502*,MOS65816" name="BCS" title="_Branch on _carry _set" proposal="BCS _" modes="rel=$b0"/>
<opcode cpus="MOS6502*,MOS65816" name="BEQ" title="_Branch on result _e_qual / zero" proposal="BEQ _" modes="rel=$f0"/>
<opcode cpus="MOS6502*,MOS65816" name="BIT" title="Test _b_i_ts in memory with accumulator" proposal="BIT _ " modes="zp=$24,abs=$2c"/>
<opcode cpus="MOS6502*,MOS65816" name="BMI" title="_Branch on result _m_inus" proposal="BMI _" modes="rel=$30"/>
<opcode cpus="MOS6502*,MOS65816" name="BNE" title="_Branch on result _not _equal / zero" proposal="BNE _" modes="rel=$d0"/>
<opcode cpus="MOS6502*,MOS65816" name="BPL" title="_Branch on result _p_lus" proposal="BPL _" modes="rel=$10"/>
<opcode cpus="MOS6502*,MOS65816" name="BRK" title="Forced _b_rea_k" proposal="BRK_" modes="imp=$00"/>
<opcode cpus="MOS6502*,MOS65816" name="BVC" title="_Branch on o_verflow _clear" proposal="BVC _" modes="rel=$50"/>
<opcode cpus="MOS6502*,MOS65816" name="BVS" title="_Branch on o_verflow _set" proposal="BVS _" modes="rel=$70"/>
<opcode cpus="MOS6502*,MOS65816" name="CLC" title="_C_lear _carry flag" proposal="CLC_" modes="imp=$18"/>
<opcode cpus="MOS6502*,MOS65816" name="CLD" title="_C_lear _decimal mode" proposal="CLD_" modes="imp=$d8"/>
<opcode cpus="MOS6502*,MOS65816" name="CLI" title="_C_lear _interrupt disable bit" proposal="CLI_" modes="imp=$58"/>
<opcode cpus="MOS6502*,MOS65816" name="CLV" title="_C_lear o_verflow flag" proposal="CLV_" modes="imp=$b8"/>
<opcode cpus="MOS6502*,MOS65816" name="CMP" title="_Co_m_pare with accumulator" proposal="CMP _" modes="imm=$c9,zp=$c5,zpx=$d5,izx=$c1,izy=$d1,abs=$cd,abx=$dd,aby=$d9"/>
<opcode cpus="MOS6502*,MOS65816" name="CPX" title="_Com_pare with _X register" proposal="CPX _" modes="imm=$e0,zp=$e4,abs=$ec"/>
<opcode cpus="MOS6502*,MOS65816" name="CPY" title="_Com_pare with _Y register" proposal="CPY _" modes="imm=$c0,zp=$c4,abs=$cc"/>
<opcode cpus="MOS6502*,MOS65816" name="DEC" title="_D_e_crement memory by one" proposal="DEC _" modes="zp=$c6,zpx=$d6,abs=$ce,abx=$de"/>
<opcode cpus="MOS6502*,MOS65816" name="DEX" title="_D_ecrement _X register by one" proposal="DEX_" modes="imp=$ca"/>
<opcode cpus="MOS6502*,MOS65816" name="DEY" title="_D_ecrement _Y register by one" proposal="DEY_" modes="imp=$88"/>
<opcode cpus="MOS6502*,MOS65816" name="EOR" title="Binary _exclusive-_o_r with accumulator" proposal="EOR _" modes="imm=$49,zp=$45,zpx=$55,izx=$41,izy=$51,abs=$4d,abx=$5d,aby=$59"/>
<opcode cpus="MOS6502*,MOS65816" name="INC" title="_I_n_crement memory by one" proposal="INC _" modes="zp=$e6,zpx=$f6,abs=$ee,abx=$fe"/>
<opcode cpus="MOS6502*,MOS65816" name="INX" title="_I_ncrement _X register by one" proposal="INX_" modes="imp=$e8"/>
<opcode cpus="MOS6502*,MOS65816" name="INY" title="_I_ncrement _Y register by one" proposal="INY_" modes="imp=$c8"/>
<opcode cpus="MOS6502*,MOS65816" name="JMP" title="_Ju_m_p to new address" proposal="JMP _" modes="abs=$4c,ind=$6c,iax=$7c[MOS65C02;MOS65816]"/>
<opcode cpus="MOS6502*,MOS65816" name="JSR" title="_Jump to _sub _routine" proposal="JSR _" modes="abs=$20"/>
<opcode cpus="MOS6502*,MOS65816" name="LDA" title="_Loa_d _accumulator" proposal="LDA _" modes="imm=$a9,zp=$a5,zpx=$b5,izx=$a1,izy=$b1,abs=$ad,abx=$bd,aby=$b9"/>
<opcode cpus="MOS6502*,MOS65816" name="LDX" title="_Loa_d _X register" proposal="LDX _" modes="imm=$a2,zp=$a6,zpy=$b6,abs=$ae,aby=$be"/>
<opcode cpus="MOS6502*,MOS65816" name="LDY" title="_Loa_d _Y register" proposal="LDY _" modes="imm=$a0,zp=$a4,zpx=$b4,abs=$ac,abx=$bc"/>
<opcode cpus="MOS6502*,MOS65816" name="LSR" title="_Logical _shift _right" proposal="LSR_" modes="imp=$4a,zp=$46,zpx=$56,abs=$4e,abx=$5e"/>
<opcode cpus="MOS6502*,MOS65816" name="NOP" title="_No _o_peration" proposal="NOP_" modes="imp=$ea"/>
<opcode cpus="MOS6502*,MOS65816" name="ORA" title="Binary _o_r with _accumulator" proposal="ORA _" modes="imm=$09,zp=$05,zpx=$15,izx=$01,izy=$11,abs=$0d,abx=$1d,aby=$19"/>
<opcode cpus="MOS6502*,MOS65816" name="PHA" title="_Pus_h _accumulator on stack" proposal="PHA_" modes="imp=$48"/>
<opcode cpus="MOS6502*,MOS65816" name="PHP" title="_Pus_h _processor status register on stack" proposal="PHP_" modes="imp=$08"/>
<opcode cpus="MOS6502*,MOS65816" name="PLA" title="_Pul_l _accumulator from stack" proposal="PLA_" modes="imp=$68"/>
<opcode cpus="MOS6502*,MOS65816" name="PLP" title="_Pul_l _processor status register from stack" proposal="PLP_" modes="imp=$28"/>
<opcode cpus="MOS6502*,MOS65816" name="ROL" title="_R_otate one bit _left" proposal="ROL _" modes="imp=$2a,zp=$26,zpx=$36,abs=$2e,abx=$3e"/>
<opcode cpus="MOS6502*,MOS65816" name="ROR" title="_R_otate one bit _right" proposal="ROR _" modes="imp=$6a,zp=$66,zpx=$76,abs=$6e,abx=$7e"/>
<opcode cpus="MOS6502*,MOS65816" name="RTI" title="_Re_turn from _interrupt" proposal="RTI_" modes="imp=$40"/>
<opcode cpus="MOS6502*,MOS65816" name="RTS" title="_Re_turn from _sub routine" proposal="RTS_" modes="imp=$60"/>
<opcode cpus="MOS6502*,MOS65816" name="SBC" title="_Su_btract from accumulator with _carry" proposal="SBC _" modes="imm=$e9,zp=$e5,zpx=$f5,izx=$e1,izy=$f1,abs=$ed,abx=$ed,aby=$e9"/>
<opcode cpus="MOS6502*,MOS65816" name="SEC" title="_S_et _carry flag" proposal="SEC_" modes="imp=$38"/>
<opcode cpus="MOS6502*,MOS65816" name="SED" title="_S_et _decimal mode" proposal="SED_" modes="imp=$f8"/>
<opcode cpus="MOS6502*,MOS65816" name="SEI" title="_S_et _interrupt disable status" proposal="SEI_" modes="imp=$78"/>
<opcode cpus="MOS6502*,MOS65816" name="STA" title="_S_tore _accumulator in memory" proposal="STA _" modes="zp=$85,zpx=$95,izx=$81,izy=$91,abs=$8d,abx=$9d,aby=$99"/>
<opcode cpus="MOS6502*,MOS65816" name="STX" title="_S_tore _X register in memory" proposal="STX _" modes="zp=$86,zpy=$96,abs=$8e"/>
<opcode cpus="MOS6502*,MOS65816" name="STY" title="_S_tore _Y register in memory" proposal="STY _" modes="zp=$84,zpx=$94,abs=$8c"/>
<opcode cpus="MOS6502*,MOS65816" name="TAX" title="_Transfer _accumulator to _X register" proposal="TAX_" modes="imp=$aa"/>
<opcode cpus="MOS6502*,MOS65816" name="TAY" title="_Transfer _accumulator to _Y register" proposal="TAY_" modes="imp=$a8"/>
<opcode cpus="MOS6502*,MOS65816" name="TSX" title="_Transfer _stack pointer to _X register" proposal="TSX_" modes="imp=$ba"/>
<opcode cpus="MOS6502*,MOS65816" name="TXA" title="_Transfer _X register to _accumulator" proposal="TXA_" modes="imp=$8a"/>
<opcode cpus="MOS6502*,MOS65816" name="TXS" title="_Transfer _X register to _stack pointer" proposal="TXS_" modes="imp=$9a"/>
<opcode cpus="MOS6502*,MOS65816" name="TYA" title="_Transfer _Y register to _accumulator" proposal="TYA_" modes="imp=$98"/>
<opcode targets="MOS6502*,MOS65816" name="ADC" title="_A_dd to accumulator with _carry" proposal="ADC _" modes="imm=$69,zp=$65,zpx=$75,izx=$61,izy=$71,abs=$6d,abx=$7d,aby=$79"/>
<opcode targets="MOS6502*,MOS65816" name="AND" title="Binary _a_n_d with accumulator" proposal="AND _" modes="imm=$29,zp=$25,zpx=$35,izx=$21,izy=$31,abs=$2d,abx=$3d,aby=$39"/>
<opcode targets="MOS6502*,MOS65816" name="ASL" title="_Arithmetic _shift _left" proposal="ASL_" modes="imp=$0a,zp=$06,zpx=$16,abs=$0e,abx=$1e"/>
<opcode targets="MOS6502*,MOS65816" name="BCC" title="_Branch on _carry _clear" proposal="BCC _" modes="rel=$90"/>
<opcode targets="MOS6502*,MOS65816" name="BCS" title="_Branch on _carry _set" proposal="BCS _" modes="rel=$b0"/>
<opcode targets="MOS6502*,MOS65816" name="BEQ" title="_Branch on result _e_qual / zero" proposal="BEQ _" modes="rel=$f0"/>
<opcode targets="MOS6502*,MOS65816" name="BIT" title="Test _b_i_ts in memory with accumulator" proposal="BIT _ " modes="zp=$24,abs=$2c"/>
<opcode targets="MOS6502*,MOS65816" name="BMI" title="_Branch on result _m_inus" proposal="BMI _" modes="rel=$30"/>
<opcode targets="MOS6502*,MOS65816" name="BNE" title="_Branch on result _not _equal / zero" proposal="BNE _" modes="rel=$d0"/>
<opcode targets="MOS6502*,MOS65816" name="BPL" title="_Branch on result _p_lus" proposal="BPL _" modes="rel=$10"/>
<opcode targets="MOS6502*,MOS65816" name="BRK" title="Forced _b_rea_k" proposal="BRK_" modes="imp=$00"/>
<opcode targets="MOS6502*,MOS65816" name="BVC" title="_Branch on o_verflow _clear" proposal="BVC _" modes="rel=$50"/>
<opcode targets="MOS6502*,MOS65816" name="BVS" title="_Branch on o_verflow _set" proposal="BVS _" modes="rel=$70"/>
<opcode targets="MOS6502*,MOS65816" name="CLC" title="_C_lear _carry flag" proposal="CLC_" modes="imp=$18"/>
<opcode targets="MOS6502*,MOS65816" name="CLD" title="_C_lear _decimal mode" proposal="CLD_" modes="imp=$d8"/>
<opcode targets="MOS6502*,MOS65816" name="CLI" title="_C_lear _interrupt disable bit" proposal="CLI_" modes="imp=$58"/>
<opcode targets="MOS6502*,MOS65816" name="CLV" title="_C_lear o_verflow flag" proposal="CLV_" modes="imp=$b8"/>
<opcode targets="MOS6502*,MOS65816" name="CMP" title="_Co_m_pare with accumulator" proposal="CMP _" modes="imm=$c9,zp=$c5,zpx=$d5,izx=$c1,izy=$d1,abs=$cd,abx=$dd,aby=$d9"/>
<opcode targets="MOS6502*,MOS65816" name="CPX" title="_Com_pare with _X register" proposal="CPX _" modes="imm=$e0,zp=$e4,abs=$ec"/>
<opcode targets="MOS6502*,MOS65816" name="CPY" title="_Com_pare with _Y register" proposal="CPY _" modes="imm=$c0,zp=$c4,abs=$cc"/>
<opcode targets="MOS6502*,MOS65816" name="DEC" title="_D_e_crement memory by one" proposal="DEC _" modes="zp=$c6,zpx=$d6,abs=$ce,abx=$de"/>
<opcode targets="MOS6502*,MOS65816" name="DEX" title="_D_ecrement _X register by one" proposal="DEX_" modes="imp=$ca"/>
<opcode targets="MOS6502*,MOS65816" name="DEY" title="_D_ecrement _Y register by one" proposal="DEY_" modes="imp=$88"/>
<opcode targets="MOS6502*,MOS65816" name="EOR" title="Binary _exclusive-_o_r with accumulator" proposal="EOR _" modes="imm=$49,zp=$45,zpx=$55,izx=$41,izy=$51,abs=$4d,abx=$5d,aby=$59"/>
<opcode targets="MOS6502*,MOS65816" name="INC" title="_I_n_crement memory by one" proposal="INC _" modes="zp=$e6,zpx=$f6,abs=$ee,abx=$fe"/>
<opcode targets="MOS6502*,MOS65816" name="INX" title="_I_ncrement _X register by one" proposal="INX_" modes="imp=$e8"/>
<opcode targets="MOS6502*,MOS65816" name="INY" title="_I_ncrement _Y register by one" proposal="INY_" modes="imp=$c8"/>
<opcode targets="MOS6502*,MOS65816" name="JMP" title="_Ju_m_p to new address" proposal="JMP _" modes="abs=$4c,ind=$6c,iax=$7c[MOS65C02;MOS65816]"/>
<opcode targets="MOS6502*,MOS65816" name="JSR" title="_Jump to _sub _routine" proposal="JSR _" modes="abs=$20"/>
<opcode targets="MOS6502*,MOS65816" name="LDA" title="_Loa_d _accumulator" proposal="LDA _" modes="imm=$a9,zp=$a5,zpx=$b5,izx=$a1,izy=$b1,abs=$ad,abx=$bd,aby=$b9"/>
<opcode targets="MOS6502*,MOS65816" name="LDX" title="_Loa_d _X register" proposal="LDX _" modes="imm=$a2,zp=$a6,zpy=$b6,abs=$ae,aby=$be"/>
<opcode targets="MOS6502*,MOS65816" name="LDY" title="_Loa_d _Y register" proposal="LDY _" modes="imm=$a0,zp=$a4,zpx=$b4,abs=$ac,abx=$bc"/>
<opcode targets="MOS6502*,MOS65816" name="LSR" title="_Logical _shift _right" proposal="LSR_" modes="imp=$4a,zp=$46,zpx=$56,abs=$4e,abx=$5e"/>
<opcode targets="MOS6502*,MOS65816" name="NOP" title="_No _o_peration" proposal="NOP_" modes="imp=$ea"/>
<opcode targets="MOS6502*,MOS65816" name="ORA" title="Binary _o_r with _accumulator" proposal="ORA _" modes="imm=$09,zp=$05,zpx=$15,izx=$01,izy=$11,abs=$0d,abx=$1d,aby=$19"/>
<opcode targets="MOS6502*,MOS65816" name="PHA" title="_Pus_h _accumulator on stack" proposal="PHA_" modes="imp=$48"/>
<opcode targets="MOS6502*,MOS65816" name="PHP" title="_Pus_h _processor status register on stack" proposal="PHP_" modes="imp=$08"/>
<opcode targets="MOS6502*,MOS65816" name="PLA" title="_Pul_l _accumulator from stack" proposal="PLA_" modes="imp=$68"/>
<opcode targets="MOS6502*,MOS65816" name="PLP" title="_Pul_l _processor status register from stack" proposal="PLP_" modes="imp=$28"/>
<opcode targets="MOS6502*,MOS65816" name="ROL" title="_R_otate one bit _left" proposal="ROL _" modes="imp=$2a,zp=$26,zpx=$36,abs=$2e,abx=$3e"/>
<opcode targets="MOS6502*,MOS65816" name="ROR" title="_R_otate one bit _right" proposal="ROR _" modes="imp=$6a,zp=$66,zpx=$76,abs=$6e,abx=$7e"/>
<opcode targets="MOS6502*,MOS65816" name="RTI" title="_Re_turn from _interrupt" proposal="RTI_" modes="imp=$40"/>
<opcode targets="MOS6502*,MOS65816" name="RTS" title="_Re_turn from _sub routine" proposal="RTS_" modes="imp=$60"/>
<opcode targets="MOS6502*,MOS65816" name="SBC" title="_Su_btract from accumulator with _carry" proposal="SBC _" modes="imm=$e9,zp=$e5,zpx=$f5,izx=$e1,izy=$f1,abs=$ed,abx=$ed,aby=$e9"/>
<opcode targets="MOS6502*,MOS65816" name="SEC" title="_S_et _carry flag" proposal="SEC_" modes="imp=$38"/>
<opcode targets="MOS6502*,MOS65816" name="SED" title="_S_et _decimal mode" proposal="SED_" modes="imp=$f8"/>
<opcode targets="MOS6502*,MOS65816" name="SEI" title="_S_et _interrupt disable status" proposal="SEI_" modes="imp=$78"/>
<opcode targets="MOS6502*,MOS65816" name="STA" title="_S_tore _accumulator in memory" proposal="STA _" modes="zp=$85,zpx=$95,izx=$81,izy=$91,abs=$8d,abx=$9d,aby=$99"/>
<opcode targets="MOS6502*,MOS65816" name="STX" title="_S_tore _X register in memory" proposal="STX _" modes="zp=$86,zpy=$96,abs=$8e"/>
<opcode targets="MOS6502*,MOS65816" name="STY" title="_S_tore _Y register in memory" proposal="STY _" modes="zp=$84,zpx=$94,abs=$8c"/>
<opcode targets="MOS6502*,MOS65816" name="TAX" title="_Transfer _accumulator to _X register" proposal="TAX_" modes="imp=$aa"/>
<opcode targets="MOS6502*,MOS65816" name="TAY" title="_Transfer _accumulator to _Y register" proposal="TAY_" modes="imp=$a8"/>
<opcode targets="MOS6502*,MOS65816" name="TSX" title="_Transfer _stack pointer to _X register" proposal="TSX_" modes="imp=$ba"/>
<opcode targets="MOS6502*,MOS65816" name="TXA" title="_Transfer _X register to _accumulator" proposal="TXA_" modes="imp=$8a"/>
<opcode targets="MOS6502*,MOS65816" name="TXS" title="_Transfer _X register to _stack pointer" proposal="TXS_" modes="imp=$9a"/>
<opcode targets="MOS6502*,MOS65816" name="TYA" title="_Transfer _Y register to _accumulator" proposal="TYA_" modes="imp=$98"/>
<!-- Common legal 65C02 opcodes used by all compilers -->
<opcode cpus="MOS65C02,MOS65816" name="BRA" title="_B_ranch _always" proposal="BRA _" modes="rel=$80"/>
<opcode cpus="MOS65C02,MOS65816" name="PHX" title="_Pus_h _X register on stack" proposal="PHX_" modes="imp=$da"/>
<opcode cpus="MOS65C02,MOS65816" name="PHY" title="_Pus_h _Y register on stack" proposal="PHY_" modes="imp=$5a"/>
<opcode cpus="MOS65C02,MOS65816" name="PLX" title="_Pul_l _X register from stack" proposal="PLX_" modes="imp=$fa"/>
<opcode cpus="MOS65C02,MOS65816" name="PLY" title="_Pul_l _Y register from stack" proposal="PLY_" modes="imp=$7a"/>
<opcode cpus="MOS65C02,MOS65816" name="STP" title="_S_to_p the clock" proposal="STP_" modes="imp=$db"/>
<opcode cpus="MOS65C02,MOS65816" name="STZ" title="_S_tore _zero in memory" proposal="STZ _" modes="zp=$64,zpx=$74,abs=$9c,abx=$9e"/>
<opcode cpus="MOS65C02,MOS65816" name="TRB" title="_Test and _reset _bit" proposal="TRB _" modes="zp=$14"/>
<opcode cpus="MOS65C02,MOS65816" name="TSB" title="_Test and _set _bit" proposal="TSB _" modes="zp=$04,abs=$0c"/>
<opcode cpus="MOS65C02,MOS65816" name="WAI" title="_W_ait for _interrupt" proposal="WAI_" modes="imp=$cb"/>
<opcode targets="MOS65C02,MOS65816" name="BRA" title="_B_ranch _always" proposal="BRA _" modes="rel=$80"/>
<opcode targets="MOS65C02,MOS65816" name="PHX" title="_Pus_h _X register on stack" proposal="PHX_" modes="imp=$da"/>
<opcode targets="MOS65C02,MOS65816" name="PHY" title="_Pus_h _Y register on stack" proposal="PHY_" modes="imp=$5a"/>
<opcode targets="MOS65C02,MOS65816" name="PLX" title="_Pul_l _X register from stack" proposal="PLX_" modes="imp=$fa"/>
<opcode targets="MOS65C02,MOS65816" name="PLY" title="_Pul_l _Y register from stack" proposal="PLY_" modes="imp=$7a"/>
<opcode targets="MOS65C02,MOS65816" name="STP" title="_S_to_p the clock" proposal="STP_" modes="imp=$db"/>
<opcode targets="MOS65C02,MOS65816" name="STZ" title="_S_tore _zero in memory" proposal="STZ _" modes="zp=$64,zpx=$74,abs=$9c,abx=$9e"/>
<opcode targets="MOS65C02,MOS65816" name="TRB" title="_Test and _reset _bit" proposal="TRB _" modes="zp=$14"/>
<opcode targets="MOS65C02,MOS65816" name="TSB" title="_Test and _set _bit" proposal="TSB _" modes="zp=$04,abs=$0c"/>
<opcode targets="MOS65C02,MOS65816" name="WAI" title="_W_ait for _interrupt" proposal="WAI_" modes="imp=$cb"/>
<!-- Common legal W65816 opcodes used by all compilers -->
<opcode cpus="MOS65816" name="BRL" title="_B_ranch always _long" proposal="BRL _" modes="rel=$82"/>
<opcode cpus="MOS65816" name="COP" title="_C_o_processor" proposal="COP _" modes="imp=$02"/>
<opcode cpus="MOS65816" name="JML" title="_Ju_mp _long" proposal="JML _" modes="abl=$5c,ial=$7c"/>
<opcode cpus="MOS65816" name="JSL" title="_Jump _subroutine _long" proposal="JSL _" modes="abl=$22,iax=$fc"/>
<opcode cpus="MOS65816" name="MVN" title="Block _mo_ve _negative" proposal="MVN _" modes="bm=$54"/>
<opcode cpus="MOS65816" name="MVP" title="Block _mo_ve _positive" proposal="MVP _" modes="bm=$44"/>
<opcode cpus="MOS65816" name="PEA" title="_Push _effective _address on stack" proposal="PEA _" modes="abs=$f4"/>
<opcode cpus="MOS65816" name="PEI" title="_Push _effective _indirect address on stack" proposal="PEI _" modes="idp=$d4"/>
<opcode cpus="MOS65816" name="PER" title="_Push _effective _relative address on stack" proposal="PER _" modes="rell=$62"/>
<opcode cpus="MOS65816" name="PHB" title="_Pus_h data _bank register on stack" proposal="PHB_" modes="imp=$8b"/>
<opcode cpus="MOS65816" name="PHD" title="_Pus_h _direct register on stack" proposal="PHD_" modes="imp=$0b"/>
<opcode cpus="MOS65816" name="PHK" title="_Pus_h program ban_k register on stack" proposal="PHK_" modes="imp=$4b"/>
<opcode cpus="MOS65816" name="PLB" title="_Pul_l data _bank register from stack" proposal="PLB_" modes="imp=$ab"/>
<opcode cpus="MOS65816" name="PLD" title="_Pul_l _direct register from stack" proposal="PLD_" modes="imp=$2b"/>
<opcode cpus="MOS65816" name="REP" title="_R_eset _processor status bits" proposal="REP_" modes="imm=$c2"/>
<opcode cpus="MOS65816" name="RTL" title="_Re_turn from subroutine _long" proposal="RTL_" modes="imp=$6b"/>
<opcode cpus="MOS65816" name="SEP" title="_S_et _processor status bits" proposal="SEP _" modes="imm=$e2"/>
<opcode cpus="MOS65816" name="TCD" title="_Transfer _C accumulator to _direct register" proposal="TCD_" modes="imp=$5b"/>
<opcode cpus="MOS65816" name="TCS" title="_Transfer _C accumulator to _stack pointer" proposal="TCS_" modes="imp=$1b"/>
<opcode cpus="MOS65816" name="TDC" title="_Transfer _direct register to _C accumulator" proposal="TDC_" modes="imp=$7b"/>
<opcode cpus="MOS65816" name="TSC" title="_Transfer _stack pointer to _C accumulator" proposal="TSC_" modes="imp=$3b"/>
<opcode cpus="MOS65816" name="TXY" title="_Transfer _X register to _Y register" proposal="TXY_" modes="imp=$9b"/>
<opcode cpus="MOS65816" name="TYX" title="_Transfer _Y register to _X register" proposal="TYX_" modes="imp=$bb"/>
<opcode cpus="MOS65816" name="WDM" title="Reserved by _W_D_M for future use" proposal="WDM_" modes="imp=$42"/>
<opcode cpus="MOS65816" name="XBA" title="E_xchange _B and _A accumulator" proposal="XBA_" modes="imp=$eb"/>
<opcode cpus="MOS65816" name="XCE" title="E_xchange _carry and _emulation Bits" proposal="XCE _" modes="imp=$fb"/>
<opcode targets="MOS65816" name="BRL" title="_B_ranch always _long" proposal="BRL _" modes="rel=$82"/>
<opcode targets="MOS65816" name="COP" title="_C_o_processor" proposal="COP _" modes="imp=$02"/>
<opcode targets="MOS65816" name="JML" title="_Ju_mp _long" proposal="JML _" modes="abl=$5c,ial=$7c"/>
<opcode targets="MOS65816" name="JSL" title="_Jump _subroutine _long" proposal="JSL _" modes="abl=$22,iax=$fc"/>
<opcode targets="MOS65816" name="MVN" title="Block _mo_ve _negative" proposal="MVN _" modes="bm=$54"/>
<opcode targets="MOS65816" name="MVP" title="Block _mo_ve _positive" proposal="MVP _" modes="bm=$44"/>
<opcode targets="MOS65816" name="PEA" title="_Push _effective _address on stack" proposal="PEA _" modes="abs=$f4"/>
<opcode targets="MOS65816" name="PEI" title="_Push _effective _indirect address on stack" proposal="PEI _" modes="idp=$d4"/>
<opcode targets="MOS65816" name="PER" title="_Push _effective _relative address on stack" proposal="PER _" modes="rell=$62"/>
<opcode targets="MOS65816" name="PHB" title="_Pus_h data _bank register on stack" proposal="PHB_" modes="imp=$8b"/>
<opcode targets="MOS65816" name="PHD" title="_Pus_h _direct register on stack" proposal="PHD_" modes="imp=$0b"/>
<opcode targets="MOS65816" name="PHK" title="_Pus_h program ban_k register on stack" proposal="PHK_" modes="imp=$4b"/>
<opcode targets="MOS65816" name="PLB" title="_Pul_l data _bank register from stack" proposal="PLB_" modes="imp=$ab"/>
<opcode targets="MOS65816" name="PLD" title="_Pul_l _direct register from stack" proposal="PLD_" modes="imp=$2b"/>
<opcode targets="MOS65816" name="REP" title="_R_eset _processor status bits" proposal="REP_" modes="imm=$c2"/>
<opcode targets="MOS65816" name="RTL" title="_Re_turn from subroutine _long" proposal="RTL_" modes="imp=$6b"/>
<opcode targets="MOS65816" name="SEP" title="_S_et _processor status bits" proposal="SEP _" modes="imm=$e2"/>
<opcode targets="MOS65816" name="TCD" title="_Transfer _C accumulator to _direct register" proposal="TCD_" modes="imp=$5b"/>
<opcode targets="MOS65816" name="TCS" title="_Transfer _C accumulator to _stack pointer" proposal="TCS_" modes="imp=$1b"/>
<opcode targets="MOS65816" name="TDC" title="_Transfer _direct register to _C accumulator" proposal="TDC_" modes="imp=$7b"/>
<opcode targets="MOS65816" name="TSC" title="_Transfer _stack pointer to _C accumulator" proposal="TSC_" modes="imp=$3b"/>
<opcode targets="MOS65816" name="TXY" title="_Transfer _X register to _Y register" proposal="TXY_" modes="imp=$9b"/>
<opcode targets="MOS65816" name="TYX" title="_Transfer _Y register to _X register" proposal="TYX_" modes="imp=$bb"/>
<opcode targets="MOS65816" name="WDM" title="Reserved by _W_D_M for future use" proposal="WDM_" modes="imp=$42"/>
<opcode targets="MOS65816" name="XBA" title="E_xchange _B and _A accumulator" proposal="XBA_" modes="imp=$eb"/>
<opcode targets="MOS65816" name="XCE" title="E_xchange _carry and _emulation Bits" proposal="XCE _" modes="imp=$fb"/>
</opcodes>

10
com.wudsn.ide.asm/src/com/wudsn/ide/lng/compiler/CompilerDefinition.java
View File

@ -33,7 +33,7 @@ import com.wudsn.ide.base.common.StringUtility;
import com.wudsn.ide.base.common.TextUtility;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.AssemblerPlugin;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
import com.wudsn.ide.lng.Texts;
import com.wudsn.ide.lng.compiler.syntax.CompilerSyntax;
@ -56,7 +56,7 @@ public final class CompilerDefinition implements Comparable<CompilerDefinition>
private String homePageURL;
// Editing and source parsing.
private List<CPU> supportedCPUs;
private List<Target> supportedCPUs;
private CompilerSyntax syntax;
// Compiling.
@ -299,7 +299,7 @@ public final class CompilerDefinition implements Comparable<CompilerDefinition>
* not <code>null</code>.
* @since 1.6.1
*/
final void setSupportedCPUs(List<CPU> supportedCPUs) {
final void setSupportedCPUs(List<Target> supportedCPUs) {
if (supportedCPUs == null) {
throw new IllegalArgumentException("Parameter 'supportedCPUs' must not be null.");
}
@ -311,14 +311,14 @@ public final class CompilerDefinition implements Comparable<CompilerDefinition>
/**
* Gets the unmodifiable list of CPUs supported by this compiler. The first
* entry defines the default CPU.
* entry defines the default Target.
*
* @return The unmodifiable list of CPUs supported by this compiler, not empty
* and, not <code>null</code>.
*
* @since 1.6.1
*/
public final List<CPU> getSupportedCPUs() {
public final List<Target> getSupportedTargets() {
if (supportedCPUs == null) {
throw new IllegalStateException("Field 'supportedCPUs' must not be null.");
}

16
com.wudsn.ide.asm/src/com/wudsn/ide/lng/compiler/CompilerRegistry.java
View File

@ -33,7 +33,7 @@ import org.eclipse.core.runtime.IExtensionRegistry;
import org.eclipse.core.runtime.Platform;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
import com.wudsn.ide.lng.compiler.syntax.CompilerSyntax;
/**
@ -100,14 +100,14 @@ public final class CompilerRegistry {
compilerDefinition.setDefaultParameters(configurationElement.getAttribute("defaultParameters"));
configurationElement.getChildren("supportedCPU");
IConfigurationElement[] supportedCPUArray;
supportedCPUArray = configurationElement.getChildren("supportedCPU");
List<CPU> supportedCPUs = new ArrayList<CPU>(supportedCPUArray.length);
for (IConfigurationElement supportedCPU : supportedCPUArray) {
supportedCPUs.add(CPU.valueOf(supportedCPU.getAttribute("cpu")));
IConfigurationElement[] supportedTargetsArray;
supportedTargetsArray = configurationElement.getChildren("supportedCPU");
List<Target> supportedTargets = new ArrayList<Target>(supportedTargetsArray.length);
for (IConfigurationElement supportedCPU : supportedTargetsArray) {
supportedTargets.add(Target.valueOf(supportedCPU.getAttribute("target")));
}
supportedCPUs = Collections.unmodifiableList(supportedCPUs);
compilerDefinition.setSupportedCPUs(supportedCPUs);
supportedTargets = Collections.unmodifiableList(supportedTargets);
compilerDefinition.setSupportedCPUs(supportedTargets);
compilerDefinition
.setDefaultHardware(Hardware.valueOf(configurationElement.getAttribute("defaultHardware")));

2
com.wudsn.ide.asm/src/com/wudsn/ide/lng/compiler/parser/CompilerSourceParser.java
View File

@ -141,7 +141,7 @@ public abstract class CompilerSourceParser {
}
/**
* Gets the instruction for the currently active CPU.
* Gets the instruction for the currently active Target.
*
* @return The instruction set, not <code>null</code>.
*

59
com.wudsn.ide.asm/src/com/wudsn/ide/lng/compiler/syntax/CompilerSyntax.java
View File

@ -40,7 +40,7 @@ import org.xml.sax.SAXParseException;
import org.xml.sax.helpers.DefaultHandler;
import com.wudsn.ide.base.common.StringUtility;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
import com.wudsn.ide.lng.compiler.CompilerRegistry;
/**
@ -242,8 +242,8 @@ public final class CompilerSyntax {
} else {
// Begin parsing of instructions.
String cpusString;
Set<CPU> cpus;
String targetsString;
Set<Target> targets;
String name;
String title;
String proposal;
@ -255,12 +255,12 @@ public final class CompilerSyntax {
throw new SAXException("No name specified for '" + qName + "'.");
}
cpusString = attributes.getValue("cpus");
if (cpusString == null) {
throw new SAXException("No CPUs specified for '" + name + "'.");
targetsString = attributes.getValue("targets");
if (targetsString == null) {
throw new SAXException("No targets specified for '" + name + "'.");
}
cpus = new TreeSet<CPU>();
StringTokenizer tokenizer = new StringTokenizer(cpusString, ",");
targets = new TreeSet<Target>();
StringTokenizer tokenizer = new StringTokenizer(targetsString, ",");
while (tokenizer.hasMoreTokens()) {
String token = tokenizer.nextToken();
boolean found = false;
@ -268,23 +268,24 @@ public final class CompilerSyntax {
// Wild card?
if (token.endsWith("*")) {
token = token.substring(0, token.length() - 1);
for (CPU cpu : CPU.values()) {
if (cpu.name().startsWith(token) || cpu == CPU.MOS65C02 && token.equals("MOS6502")) {
cpus.add(cpu);
for (Target target : Target.values()) {
// TODO: Why special logic here for MOS65C02?
if (target.name().startsWith(token) || target == Target.MOS65C02 && token.equals("MOS6502")) {
targets.add(target);
found = true;
}
}
} else {
// Exact match
for (CPU cpu : CPU.values()) {
if (cpu.name().equals(token)) {
cpus.add(cpu);
for (Target target : Target.values()) {
if (target.name().equals(token)) {
targets.add(target);
found = true;
}
}
}
if (!found) {
throw new SAXException("No cpu matches the cpus '" + cpusString + "' for '" + name + "'.");
throw new SAXException("No target matches the target '" + targetsString + "' for '" + name + "'.");
}
}
@ -359,7 +360,7 @@ public final class CompilerSyntax {
throw new SAXException(
"Unknown directive type '" + typeString + "' for directive '" + name + "'.");
}
instructionsList.add(new Directive(cpus, type, instructionsCaseSensitive, name, title, proposal));
instructionsList.add(new Directive(targets, type, instructionsCaseSensitive, name, title, proposal));
} else if (qName.equals("opcode") || qName.equals("illegalopcode") || qName.equals("pseudoopcode")) {
if (qName.equals("opcode")) {
@ -389,8 +390,8 @@ public final class CompilerSyntax {
name = name.toLowerCase();
proposal = proposal.toLowerCase();
}
instructionsList.add(new Opcode(cpus, type, instructionsCaseSensitive, name, title, proposal,
cpus.contains(CPU.MOS65816), flags, modes));
instructionsList.add(new Opcode(targets, type, instructionsCaseSensitive, name, title, proposal,
targets.contains(Target.MOS65816), flags, modes));
}
}
}
@ -429,7 +430,7 @@ public final class CompilerSyntax {
private String sourceIncludeDefaultExtension;
private List<Instruction> instructionList;
private Map<CPU, InstructionSet> instructionSets;
private Map<Target, InstructionSet> instructionSets;
/**
* Creates new instance. Called by {@link CompilerRegistry}.
@ -615,7 +616,7 @@ public final class CompilerSyntax {
instructionList = Collections.unmodifiableList(xmlHandler.instructionsList);
// Create instruction set map.
instructionSets = new TreeMap<CPU, InstructionSet>();
instructionSets = new TreeMap<Target, InstructionSet>();
}
static boolean[] createBooleanArray(String string) {
@ -895,25 +896,25 @@ public final class CompilerSyntax {
}
/**
* Gets the instruction set for a CPU.
* Gets the instruction set for a Target.
*
* @param cpu The CPU this which the allowed list of instructions shall be
* @param target The Target this which the allowed list of instructions shall be
* returned, not <code>null</code>.
* @return The set of instructions supported by the compiler for the specified
* CPU, not <code>null</code>.
* Target, not <code>null</code>.
*
* @since 1.6.1
*/
public InstructionSet getInstructionSet(CPU cpu) {
if (cpu == null) {
throw new IllegalArgumentException("Parameter 'cpu' must not be null.");
public InstructionSet getInstructionSet(Target target) {
if (target == null) {
throw new IllegalArgumentException("Parameter 'target' must not be null.");
}
InstructionSet result;
synchronized (instructionSets) {
result = instructionSets.get(cpu);
result = instructionSets.get(target);
if (result == null) {
result = new InstructionSet(this, instructionList, cpu);
instructionSets.put(cpu, result);
result = new InstructionSet(this, instructionList, target);
instructionSets.put(target, result);
}
}

4
com.wudsn.ide.asm/src/com/wudsn/ide/lng/compiler/syntax/Directive.java
View File

@ -21,11 +21,11 @@ package com.wudsn.ide.lng.compiler.syntax;
import java.util.Set;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
public final class Directive extends Instruction {
Directive(Set<CPU> cpus, int type, boolean caseSensitive, String name, String title, String proposal) {
Directive(Set<Target> cpus, int type, boolean caseSensitive, String name, String title, String proposal) {
super(cpus, type, caseSensitive, name, title, proposal);
switch (type) {

8
com.wudsn.ide.asm/src/com/wudsn/ide/lng/compiler/syntax/Instruction.java
View File

@ -24,14 +24,14 @@ import java.util.List;
import java.util.Set;
import com.wudsn.ide.base.common.NumberFactory;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
public abstract class Instruction implements Comparable<Instruction> {
public static final char CURSOR = '_';
public static final char NEWLINE = '\n';
private Set<CPU> cpus;
private Set<Target> cpus;
private int type;
private String name;
private String upperCaseName;
@ -42,7 +42,7 @@ public abstract class Instruction implements Comparable<Instruction> {
private int[] styledTitleOffsets;
private String proposal;
protected Instruction(Set<CPU> cpus, int type, boolean caseSensitive, String name, String title, String proposal) {
protected Instruction(Set<Target> cpus, int type, boolean caseSensitive, String name, String title, String proposal) {
if (cpus == null) {
throw new IllegalArgumentException("Parameter 'cpus' must not be null.");
}
@ -130,7 +130,7 @@ public abstract class Instruction implements Comparable<Instruction> {
}
}
public Set<CPU> getCPUs() {
public Set<Target> getCPUs() {
return cpus;
}

18
com.wudsn.ide.asm/src/com/wudsn/ide/lng/compiler/syntax/InstructionSet.java
View File

@ -25,7 +25,7 @@ import java.util.List;
import java.util.Map;
import java.util.TreeMap;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
import com.wudsn.ide.lng.compiler.CompilerRegistry;
import com.wudsn.ide.lng.compiler.syntax.Opcode.OpcodeAddressingMode;
@ -64,9 +64,9 @@ public final class InstructionSet {
* @param compilerSyntax The compiler syntax, not <code>null</code>.
*
* @param instructionsList The non-filtered list of compiler instructions.
* @param cpu The cpu to filter by, not <code>null</code>.
* @param target The target to filter by, not <code>null</code>.
*/
InstructionSet(CompilerSyntax compilerSyntax, List<Instruction> instructionsList, CPU cpu) {
InstructionSet(CompilerSyntax compilerSyntax, List<Instruction> instructionsList, Target target) {
if (compilerSyntax == null) {
throw new IllegalArgumentException("Parameter 'compilerSyntax' must not be null.");
@ -74,8 +74,8 @@ public final class InstructionSet {
if (instructionsList == null) {
throw new IllegalArgumentException("Parameter 'instructionsList' must not be null.");
}
if (cpu == null) {
throw new IllegalArgumentException("Parameter 'cpu' must not be null.");
if (target == null) {
throw new IllegalArgumentException("Parameter 'target' must not be null.");
}
// Compute the list of all include instructions.
this.compilerSyntax = compilerSyntax;
@ -94,7 +94,7 @@ public final class InstructionSet {
StringBuilder instructionPartCharacters = new StringBuilder(2048);
for (Instruction instruction : instructionsList) {
if (!instruction.getCPUs().contains(cpu)) {
if (!instruction.getCPUs().contains(target)) {
continue;
}
this.instructionsList.add(instruction);
@ -121,8 +121,8 @@ public final class InstructionSet {
Opcode opcode = (Opcode) instruction;
for (OpcodeAddressingMode opcodeAddressingMode : opcode.getAddressingModes()) {
// Even if an instruction is supported by all CPUs, not all
// addressing modes may be supported by the CPU,
if (opcodeAddressingMode.getCPUs().contains(cpu)) {
// addressing modes may be supported by the Target,
if (opcodeAddressingMode.getCPUs().contains(target)) {
List<OpcodeAddressingMode> list = opcodeAddessingModesList
.get(opcodeAddressingMode.getOpcodeValue());
if (list == null) {
@ -212,7 +212,7 @@ public final class InstructionSet {
/**
* Gets list of opcode address modes for the given opcode value. Only instances
* that are support by the CPU of the instruction set are returned.
* that are support by the Target of the instruction set are returned.
*
* @param opcodeValue The opcode value.
* @return The list of opcode address modes, may be empty, not

16
com.wudsn.ide.asm/src/com/wudsn/ide/lng/compiler/syntax/Opcode.java
View File

@ -24,7 +24,7 @@ import java.util.List;
import java.util.Set;
import java.util.TreeSet;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
public final class Opcode extends Instruction {
@ -32,11 +32,11 @@ public final class Opcode extends Instruction {
public final static class OpcodeAddressingMode {
private Opcode opcode;
private Set<CPU> cpus;
private Set<Target> cpus;
private String addressingMode;
private int opcodeValue;
OpcodeAddressingMode(Opcode opcode, Set<CPU> cpus, String addressingMode, int opcodeValue) {
OpcodeAddressingMode(Opcode opcode, Set<Target> cpus, String addressingMode, int opcodeValue) {
if (opcode == null) {
throw new IllegalArgumentException("Parameter 'opcode' must not be null.");
}
@ -63,7 +63,7 @@ public final class Opcode extends Instruction {
return opcode;
}
public Set<CPU> getCPUs() {
public Set<Target> getCPUs() {
return cpus;
}
@ -133,7 +133,7 @@ public final class Opcode extends Instruction {
private String modes;
private List<OpcodeAddressingMode> addressingModes;
Opcode(Set<CPU> cpus, int type, boolean instructionsCaseSensitive, String name, String title, String proposal,
Opcode(Set<Target> cpus, int type, boolean instructionsCaseSensitive, String name, String title, String proposal,
boolean w65816, String flags, String modes) {
super(cpus, type, instructionsCaseSensitive, name, title, proposal);
@ -157,7 +157,7 @@ public final class Opcode extends Instruction {
this.flags = flags;
this.modes = modes;
addressingModes = new ArrayList<OpcodeAddressingMode>();
Set<CPU> addressingModeCPUs = cpus;
Set<Target> addressingModeCPUs = cpus;
for (String mode : modes.split(",")) {
mode = mode.trim();
String values[] = mode.split("=");
@ -167,9 +167,9 @@ public final class Opcode extends Instruction {
if (index >= 0) {
String[] cpuNameList = value.substring(index + 1, value.length() - 1).split(";");
value = value.substring(0, index);
addressingModeCPUs = new TreeSet<CPU>();
addressingModeCPUs = new TreeSet<Target>();
for (String cpuName : cpuNameList) {
addressingModeCPUs.add(CPU.valueOf(cpuName));
addressingModeCPUs.add(Target.valueOf(cpuName));
}
}
int opcode = Integer.parseInt(value, 16);

8
com.wudsn.ide.asm/src/com/wudsn/ide/lng/editor/AssemblerEditor.java
View File

@ -57,7 +57,7 @@ import com.wudsn.ide.base.common.Profiler;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.AssemblerPlugin;
import com.wudsn.ide.lng.AssemblerProperties;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
import com.wudsn.ide.lng.AssemblerProperties.InvalidAssemblerPropertyException;
import com.wudsn.ide.lng.compiler.Compiler;
import com.wudsn.ide.lng.compiler.CompilerDefinition;
@ -189,14 +189,14 @@ public abstract class AssemblerEditor extends TextEditor {
* @return The compiler source parser for this editor, not <code>null</code> .
*/
public final CompilerSourceParser createCompilerSourceParser() {
CPU cpu;
Target target;
CompilerSourceParser result;
if (compiler == null) {
throw new IllegalStateException("Field 'compiler' must not be null.");
}
cpu = getCompilerPreferences().getCPU();
target = getCompilerPreferences().getTarget();
result = compiler.createSourceParser();
result.init(compiler.getDefinition().getSyntax().getInstructionSet(cpu));
result.init(compiler.getDefinition().getSyntax().getInstructionSet(target));
return result;
}

2
com.wudsn.ide.asm/src/com/wudsn/ide/lng/editor/AssemblerSourceScanner.java
View File

@ -501,7 +501,7 @@ final class AssemblerSourceScanner extends RuleBasedScanner {
token.setData(preferences.getEditorTextAttribute(propertyName));
refresh = true;
} else if (AssemblerPreferencesConstants.isCompilerCPUName(propertyName)) {
} else if (AssemblerPreferencesConstants.isCompilerTargetName(propertyName)) {
CompilerSourceParser compilerSourceParser = editor.createCompilerSourceParser();
wordRule.setCompilerSourceParser(compilerSourceParser);
wordRule.setInstructions();

22
com.wudsn.ide.asm/src/com/wudsn/ide/lng/help/AssemblerHelpContentProducer.java
View File

@ -49,7 +49,7 @@ import com.wudsn.ide.base.common.TextUtility;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.base.hardware.HardwareUtility;
import com.wudsn.ide.lng.AssemblerPlugin;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
import com.wudsn.ide.lng.Texts;
import com.wudsn.ide.lng.compiler.Compiler;
import com.wudsn.ide.lng.compiler.CompilerDefinition;
@ -99,7 +99,7 @@ public final class AssemblerHelpContentProducer implements IHelpContentProducer
public static final String SECTION_MANUAL = "manual";
public static final String SECTION_MANUAL_FILE = "file";
public static final String SCHEMA_CPU = "cpu/";
public static final String SCHEMA_TARGET = "target/";
private static final String ICONS_PATH = "/help/topic/com.wudsn.ide.lng/icons/";
@ -114,7 +114,7 @@ public final class AssemblerHelpContentProducer implements IHelpContentProducer
return getCompilerInputStream(href);
} else if (href.startsWith(SCHEMA_HARDWARE)) {
return getHardwareInputStream(href);
} else if (href.startsWith(SCHEMA_CPU)) {
} else if (href.startsWith(SCHEMA_TARGET)) {
return getCPUInputStream(href);
} else if (href.endsWith(".html")) { // Web site documents
return getHTMLInputStream(href);
@ -338,7 +338,7 @@ public final class AssemblerHelpContentProducer implements IHelpContentProducer
writer.writeTableRow(Texts.TOC_ASSEMBLER_DEFAULT_HARDWARE_LABEL, HTMLWriter
.getImage(ICONS_PATH + HardwareUtility.getImagePath(hardware), hardware.name(), hardware.name()));
List<CPU> cpus = compilerDefinition.getSupportedCPUs();
List<Target> cpus = compilerDefinition.getSupportedTargets();
writer.beginTableRow();
writer.writeTableHeader(Texts.TOC_ASSEMBLER_SUPPORTED_CPUS_LABEL);
StringBuilder builder = new StringBuilder();
@ -437,9 +437,9 @@ public final class AssemblerHelpContentProducer implements IHelpContentProducer
List<Instruction> pseudoOpcodes = new ArrayList<Instruction>();
List<Instruction> w65816Opcodes = new ArrayList<Instruction>();
List<CPU> cpus = compilerDefinition.getSupportedCPUs();
for (CPU cpu : cpus) {
for (Instruction instruction : syntax.getInstructionSet(cpu).getInstructions()) {
List<Target> cpus = compilerDefinition.getSupportedTargets();
for (Target target : cpus) {
for (Instruction instruction : syntax.getInstructionSet(target).getInstructions()) {
if (instruction instanceof Directive) {
if (!directives.contains(instruction)) {
@ -598,19 +598,19 @@ public final class AssemblerHelpContentProducer implements IHelpContentProducer
if (href == null) {
throw new IllegalArgumentException("Parameter 'href' must not be null.");
}
String path = getPath(SCHEMA_CPU, href);
String path = getPath(SCHEMA_TARGET, href);
if (path == null) {
return null;
}
CPU cpu = CPU.valueOf(path.toUpperCase());
Target target = Target.valueOf(path.toUpperCase());
AssemblerPlugin assemblerPlugin = AssemblerPlugin.getInstance();
CompilerRegistry compilerRegistry = assemblerPlugin.getCompilerRegistry();
HTMLWriter writer = createHeader();
writer.beginTable();
writer.writeTableRow(Texts.TOC_CPU_NAME_LABEL, EnumUtility.getText(cpu));
writer.writeTableRow(Texts.TOC_CPU_NAME_LABEL, EnumUtility.getText(target));
writer.end();
writer.begin("br", null);
@ -627,7 +627,7 @@ public final class AssemblerHelpContentProducer implements IHelpContentProducer
InstructionSet[] instructionSets = new InstructionSet[compilerDefinitions.size()];
for (int c = 0; c < compilerDefinitionCount; c++) {
CompilerDefinition compilerDefinition = compilerDefinitions.get(c);
instructionSets[c] = compilerDefinition.getSyntax().getInstructionSet(cpu);
instructionSets[c] = compilerDefinition.getSyntax().getInstructionSet(target);
writer.writeTableHeader(compilerDefinition.getName());
}

10
com.wudsn.ide.asm/src/com/wudsn/ide/lng/help/AssemblerTocProvider.java
View File

@ -40,7 +40,7 @@ import org.eclipse.help.IUAElement;
import com.wudsn.ide.base.common.EnumUtility;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.AssemblerPlugin;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
import com.wudsn.ide.lng.Texts;
import com.wudsn.ide.lng.compiler.CompilerDefinition;
import com.wudsn.ide.lng.compiler.CompilerRegistry;
@ -346,11 +346,11 @@ public final class AssemblerTocProvider extends AbstractTocProvider {
}
private static List<ITopic> createCPUTopics() {
List<ITopic> cpuTopics = new ArrayList<ITopic>(CPU.values().length - 1);
for (CPU cpu : CPU.values()) {
String href = AssemblerHelpContentProducer.SCHEMA_CPU + cpu.name().toLowerCase()
List<ITopic> cpuTopics = new ArrayList<ITopic>(Target.values().length - 1);
for (Target target : Target.values()) {
String href = AssemblerHelpContentProducer.SCHEMA_TARGET + target.name().toLowerCase()
+ AssemblerHelpContentProducer.EXTENSION;
cpuTopics.add(createTopic("", EnumUtility.getText(cpu), href, null));
cpuTopics.add(createTopic("", EnumUtility.getText(target), href, null));
}
return cpuTopics;
}

14
com.wudsn.ide.asm/src/com/wudsn/ide/lng/preferences/AssemblerPreferencesConstants.java
View File

@ -147,18 +147,18 @@ public final class AssemblerPreferencesConstants {
}
/**
* Determines if preference key name represents a setting for compiler opcodes
* Determines if preference key name represents a setting for compiler targets
* visibility.
*
* @param name The name of the preferences key, not <code>null</code>.
* @return <code>true</code> if preference key name represents a setting for
* compiler opcodes visibility, <code>false</code> otherwise.
*/
public static boolean isCompilerCPUName(String name) {
public static boolean isCompilerTargetName(String name) {
if (name == null) {
throw new IllegalArgumentException("Parameter 'name' must not be null.");
}
boolean result = name.startsWith("compiler.") && name.endsWith(".cpu");
boolean result = name.startsWith("compiler.") && name.endsWith(".target");
return result;
}
@ -180,22 +180,22 @@ public final class AssemblerPreferencesConstants {
}
/**
* Gets preference key name for the compiler CPU visibility.
* Gets preference key name for the compiler Target visibility.
*
* @param compilerId The compiler id, not <code>null</code>.
* @param hardware The hardware, not <code>null</code>.
*
* @return The preference key name for the compiler CPU, not empty and not
* @return The preference key name for the compiler Target, not empty and not
* <code>null</code>.
*/
static String getCompilerCPUName(String compilerId, Hardware hardware) {
static String getCompilerTargetName(String compilerId, Hardware hardware) {
if (compilerId == null) {
throw new IllegalArgumentException("Parameter 'compilerId' must not be null.");
}
if (hardware == null) {
throw new IllegalArgumentException("Parameter 'hardware' must not be null.");
}
return getCompilerHardwarePrefix(compilerId, hardware) + ".cpu"; //$NON-NLS-1$
return getCompilerHardwarePrefix(compilerId, hardware) + ".target"; //$NON-NLS-1$
}
/**

4
com.wudsn.ide.asm/src/com/wudsn/ide/lng/preferences/AssemblerPreferencesInitializer.java
View File

@ -123,8 +123,8 @@ public final class AssemblerPreferencesInitializer extends AbstractPreferenceIni
if (hardware.equals(Hardware.GENERIC)) {
continue;
}
store.setDefault(AssemblerPreferencesConstants.getCompilerCPUName(compilerId, hardware),
compilerDefinition.getSupportedCPUs().get(0).toString());
store.setDefault(AssemblerPreferencesConstants.getCompilerTargetName(compilerId, hardware),
compilerDefinition.getSupportedTargets().get(0).toString());
name = AssemblerPreferencesConstants.getCompilerParametersName(compilerId, hardware);
store.setDefault(name, compilerDefinition.getDefaultParameters());

24
com.wudsn.ide.asm/src/com/wudsn/ide/lng/preferences/CompilerPreferences.java
View File

@ -21,7 +21,7 @@ package com.wudsn.ide.lng.preferences;
import com.wudsn.ide.base.common.StringUtility;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
import com.wudsn.ide.lng.compiler.CompilerOutputFolderMode;
import com.wudsn.ide.lng.runner.RunnerId;
@ -76,21 +76,21 @@ public final class CompilerPreferences {
}
/**
* Gets the CPU for which the instructions shall be active.
* Gets the Target for which the instructions shall be active.
*
* @return The CPU, not <code>null</code>.
* @return The Target, not <code>null</code>.
*
* @since 1.6.1
*/
public CPU getCPU() {
CPU result;
String cpuString = assemblerPreferences
.getString(AssemblerPreferencesConstants.getCompilerCPUName(compilerId, hardware));
public Target getTarget() {
Target result;
String targetString = assemblerPreferences
.getString(AssemblerPreferencesConstants.getCompilerTargetName(compilerId, hardware));
if (StringUtility.isEmpty(cpuString)) {
result = CPU.MOS6502;
if (StringUtility.isEmpty(targetString)) {
result = Target.MOS6502;
} else {
result = CPU.valueOf(cpuString);
result = Target.valueOf(targetString);
}
return result;
}
@ -102,7 +102,7 @@ public final class CompilerPreferences {
*/
@Deprecated
public boolean isIllegalOpcodesVisible() {
return getCPU() == CPU.MOS6502_ILLEGAL;
return getTarget() == Target.MOS6502_ILLEGAL;
}
/**
@ -112,7 +112,7 @@ public final class CompilerPreferences {
*/
@Deprecated
public boolean isW65816OpcodesVisible() {
return getCPU() == CPU.MOS65816;
return getTarget() == Target.MOS65816;
}
/**

36
com.wudsn.ide.asm/src/com/wudsn/ide/lng/preferences/AssemblerPreferencesCompilersPage.java → com.wudsn.ide.asm/src/com/wudsn/ide/lng/preferences/LanguagePreferencesCompilersPage.java
View File

@ -20,6 +20,7 @@
package com.wudsn.ide.lng.preferences;
import java.util.ArrayList;
import com.wudsn.ide.lng.Language;
import java.util.List;
import java.util.Map;
import java.util.TreeMap;
@ -55,7 +56,7 @@ import com.wudsn.ide.base.common.TextUtility;
import com.wudsn.ide.base.gui.SWTFactory;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.AssemblerPlugin;
import com.wudsn.ide.lng.CPU;
import com.wudsn.ide.lng.Target;
import com.wudsn.ide.lng.Texts;
import com.wudsn.ide.lng.compiler.CompilerDefinition;
import com.wudsn.ide.lng.compiler.CompilerOutputFolderMode;
@ -66,13 +67,13 @@ import com.wudsn.ide.lng.runner.RunnerId;
import com.wudsn.ide.lng.runner.RunnerRegistry;
/**
* Visual editor page for the assembler preferences regarding compilers. There
* Visual editor page for the language preferences regarding compilers. There
* is a separate page per {@link Hardware}. Subclasses only implement the
* constructor.
*
* @author Peter Dell
*/
public abstract class AssemblerPreferencesCompilersPage extends FieldEditorPreferencePage
public abstract class LanguagePreferencesCompilersPage extends FieldEditorPreferencePage
implements IWorkbenchPreferencePage {
private static final class Tab {
@ -165,6 +166,11 @@ public abstract class AssemblerPreferencesCompilersPage extends FieldEditorPrefe
}
/**
* The language.
*/
final Language langauge;
/**
* The type of hardware used to filter the compilers and emulators.
*/
@ -193,11 +199,15 @@ public abstract class AssemblerPreferencesCompilersPage extends FieldEditorPrefe
* @param hardware The type of hardware used to filter the compilers and
* emulators, not <code>null</code>.
*/
protected AssemblerPreferencesCompilersPage(Hardware hardware) {
protected LanguagePreferencesCompilersPage(Language language, Hardware hardware) {
super(GRID);
if (language == null) {
throw new IllegalArgumentException("Parameter 'language' must not be null.");
}
if (hardware == null) {
throw new IllegalArgumentException("Parameter 'hardware' must not be null.");
}
this.langauge = language;
this.hardware = hardware;
plugin = AssemblerPlugin.getInstance();
IPreferenceStore preferencesStore = plugin.getPreferenceStore();
@ -311,25 +321,25 @@ public abstract class AssemblerPreferencesCompilersPage extends FieldEditorPrefe
Composite composite;
// Field: cpu
// Field: target
composite = SWTFactory.createComposite(tabContent, 2, 3, GridData.FILL_HORIZONTAL);
// Filtering of CPU based on hardware is currently not implemented
// Filtering of Target based on hardware is currently not implemented
// because expansion boards like a W65816 board might be there/added
// for a hardware.
List<CPU> cpus = compilerDefinition.getSupportedCPUs();
String[][] entryNamesAndValues = new String[cpus.size()][];
List<Target> targets = compilerDefinition.getSupportedTargets();
String[][] entryNamesAndValues = new String[targets.size()][];
int i = 0;
for (CPU cpu : cpus) {
for (Target target : targets) {
entryNamesAndValues[i] = new String[2];
entryNamesAndValues[i][1] = cpu.name();
entryNamesAndValues[i][0] = EnumUtility.getText(cpu);
entryNamesAndValues[i][1] = target.name();
entryNamesAndValues[i][0] = EnumUtility.getText(target);
i++;
}
FieldEditor comboFieldEditor = new ComboFieldEditor(
AssemblerPreferencesConstants.getCompilerCPUName(compilerId, hardware),
Texts.PREFERENCES_COMPILER_CPU_LABEL, entryNamesAndValues, composite);
AssemblerPreferencesConstants.getCompilerTargetName(compilerId, hardware),
Texts.PREFERENCES_COMPILER_TARGET_LABEL, entryNamesAndValues, composite);
comboFieldEditor.setEnabled(entryNamesAndValues.length > 1, composite);
addField(comboFieldEditor);

2
com.wudsn.ide.base/src/com/wudsn/ide/base/common/EnumUtility.java
View File

@ -52,7 +52,7 @@ public final class EnumUtility {
try {
ResourceBundle resourceBundle;
resourceBundle = ResourceBundle.getBundle("plugin", Locale.getDefault(), enumClass.getClassLoader());
resourceBundle = ResourceBundle.getBundle("OSGI-INF/l10n/bundle", Locale.getDefault(), enumClass.getClassLoader());
result = resourceBundle.getString(key);
} catch (MissingResourceException ex) {
result = enumValue.name() + " - Text missing";

5
com.wudsn.ide.pas/META-INF/MANIFEST.MF
View File

@ -3,9 +3,10 @@ Bundle-ManifestVersion: 2
Bundle-Name: Peter Dell
Bundle-SymbolicName: com.wudsn.ide.lng.pas;singleton:=true
Bundle-Version: 1.7.2.qualifier
Bundle-Activator: com.wudsn.ide.pas.Activator
Bundle-Activator: com.wudsn.ide.lng.pas.Activator
Bundle-Vendor: WUDSN IDE Pascal Plugin
Require-Bundle: org.eclipse.core.resources,
Require-Bundle: com.wudsn.ide.lng,
org.eclipse.core.resources,
org.eclipse.core.runtime,
org.eclipse.jface.text,
org.eclipse.ui,

4
com.wudsn.ide.pas/OSGI-INF/l10n/bundle.properties
View File

@ -1,2 +1,2 @@
#Properties file for com.wudsn.ide.pas
com.wudsn.ide.pas.compiler.PascalSourceFile.name=Pascal Source File
#Properties file for com.wudsn.ide.lng.pas
com.wudsn.ide.lng.pas.compiler.PascalSourceFile.name=Pascal Source File

4
com.wudsn.ide.pas/OSGI-INF/l10n/bundle_de_DE.properties
View File

@ -1,2 +1,2 @@
#Properties file for com.wudsn.ide.pas
com.wudsn.ide.pas.compiler.PascalSourceFile.name=Pascal Quell-Datei
#Properties file for com.wudsn.ide.lng.pas
com.wudsn.ide.lng.pas.compiler.PascalSourceFile.name=Pascal Quell-Datei

8
com.wudsn.ide.pas/plugin.xml
View File

@ -21,21 +21,21 @@
<extension
point="org.eclipse.ui.genericeditor.presentationReconcilers">
<presentationReconciler
class="com.wudsn.ide.pas.editor.PascalReconciler"
class="com.wudsn.ide.lng.pas.editor.PascalReconciler"
contentType="com.wudsn.ide.pas.compiler.PascalSourceFile">
</presentationReconciler>
</extension>
<extension
point="org.eclipse.ui.genericeditor.hoverProviders">
<hoverProvider
class="com.wudsn.ide.pas.editor.PascalHoverProvider"
class="com.wudsn.ide.lng.pas.editor.PascalHoverProvider"
contentType="com.wudsn.ide.pas.compiler.PascalSourceFile">
</hoverProvider>
</extension>
<extension
point="org.eclipse.ui.genericeditor.contentAssistProcessors">
<contentAssistProcessor
class="com.wudsn.ide.pas.editor.PascalContentAssistProcessor"
class="com.wudsn.ide.lng.pas.editor.PascalContentAssistProcessor"
contentType="com.wudsn.ide.pas.compiler.PascalSourceFile">
</contentAssistProcessor>
</extension>
@ -44,7 +44,7 @@
<participant
contentTypeId="com.wudsn.ide.pas.compiler.PascalSourceFile"
extensions="pas"
class="com.wudsn.ide.pas.editor.ValidatorDocumentSetupParticipant">
class="com.wudsn.ide.lng.pas.editor.ValidatorDocumentSetupParticipant">
</participant>
</extension>

4
com.wudsn.ide.pas/src/com/wudsn/ide/pas/Activator.java → com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/Activator.java
View File

@ -16,7 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.pas;
package com.wudsn.ide.lng.pas;
import org.eclipse.ui.plugin.AbstractUIPlugin;
import org.osgi.framework.BundleContext;
@ -29,7 +29,7 @@ import org.osgi.framework.BundleContext;
public class Activator extends AbstractUIPlugin {
// The plug-in ID
public static final String PLUGIN_ID = "com.wudsn.ide.pas"; //$NON-NLS-1$
public static final String PLUGIN_ID = "com.wudsn.ide.lng.pas"; //$NON-NLS-1$
// The shared instance
private static Activator plugin;

2
com.wudsn.ide.pas/src/com/wudsn/ide/pas/editor/PascalContentAssistProcessor.java → com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/editor/PascalContentAssistProcessor.java
View File

@ -16,7 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.pas.editor;
package com.wudsn.ide.lng.pas.editor;
import org.eclipse.core.resources.IProject;
import org.eclipse.core.resources.IProjectNatureDescriptor;

2
com.wudsn.ide.pas/src/com/wudsn/ide/pas/editor/PascalHoverProvider.java → com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/editor/PascalHoverProvider.java
View File

@ -16,7 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.pas.editor;
package com.wudsn.ide.lng.pas.editor;
//import org.eclipse.core.resources.IProjectNatureDescriptor;
//import org.eclipse.core.resources.IWorkspace;

2
com.wudsn.ide.pas/src/com/wudsn/ide/pas/editor/PascalReconciler.java → com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/editor/PascalReconciler.java
View File

@ -16,7 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.pas.editor;
package com.wudsn.ide.lng.pas.editor;
import org.eclipse.swt.SWT;
import org.eclipse.swt.graphics.Color;

2
com.wudsn.ide.pas/src/com/wudsn/ide/pas/editor/PascalWordDetector.java → com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/editor/PascalWordDetector.java
View File

@ -16,7 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.pas.editor;
package com.wudsn.ide.lng.pas.editor;
import org.eclipse.jface.text.rules.IWordDetector;

2
com.wudsn.ide.pas/src/com/wudsn/ide/pas/editor/PascalWordRule.java → com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/editor/PascalWordRule.java
View File

@ -16,7 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.pas.editor;
package com.wudsn.ide.lng.pas.editor;
import java.util.StringTokenizer;

2
com.wudsn.ide.pas/src/com/wudsn/ide/pas/editor/ValidatorDocumentSetupParticipant.java → com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/editor/ValidatorDocumentSetupParticipant.java
View File

@ -16,7 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.pas.editor;
package com.wudsn.ide.lng.pas.editor;
//import java.io.StringReader;
//

41
com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/preferences/PascalPreferencesApple2CompilersPage.java Normal file
View File

@ -0,0 +1,41 @@
/**
* Copyright (C) 2009 - 2021 <a href="https://www.wudsn.com" target="_top">Peter Dell</a>
*
* This file is part of WUDSN IDE.
*
* WUDSN IDE is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* WUDSN IDE is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.lng.pas.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding Apple 2 compilers.
*
* @author Peter Dell
*
*/
public final class PascalPreferencesApple2CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public PascalPreferencesApple2CompilersPage() {
super(Language.PAS, Hardware.APPLE2);
}
}

41
com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/preferences/PascalPreferencesAtari2600CompilersPage.java Normal file
View File

@ -0,0 +1,41 @@
/**
* Copyright (C) 2009 - 2021 <a href="https://www.wudsn.com" target="_top">Peter Dell</a>
*
* This file is part of WUDSN IDE.
*
* WUDSN IDE is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* WUDSN IDE is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.lng.pas.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding Apple 2 compilers.
*
* @author Peter Dell
*
*/
public final class PascalPreferencesAtari2600CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public PascalPreferencesAtari2600CompilersPage() {
super(Language.ASM,Hardware.ATARI2600);
}
}

41
com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/preferences/PascalPreferencesAtari7800CompilersPage.java Normal file
View File

@ -0,0 +1,41 @@
/**
* Copyright (C) 2009 - 2021 <a href="https://www.wudsn.com" target="_top">Peter Dell</a>
*
* This file is part of WUDSN IDE.
*
* WUDSN IDE is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* WUDSN IDE is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.lng.pas.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding Apple 2 compilers.
*
* @author Peter Dell
*
*/
public final class PascalPreferencesAtari7800CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public PascalPreferencesAtari7800CompilersPage() {
super(Language.ASM, Hardware.ATARI7800);
}
}

42
com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/preferences/PascalPreferencesAtari8CompilersPage.java Normal file
View File

@ -0,0 +1,42 @@
/**
* Copyright (C) 2009 - 2021 <a href="https://www.wudsn.com" target="_top">Peter Dell</a>
*
* This file is part of WUDSN IDE.
*
* WUDSN IDE is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* WUDSN IDE is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.lng.pas.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding Atari 8-bit
* compilers.
*
* @author Peter Dell
*
*/
public final class PascalPreferencesAtari8CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public PascalPreferencesAtari8CompilersPage() {
super(Language.ASM,Hardware.ATARI8BIT);
}
}

41
com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/preferences/PascalPreferencesC64CompilersPage.java Normal file
View File

@ -0,0 +1,41 @@
/**
* Copyright (C) 2009 - 2021 <a href="https://www.wudsn.com" target="_top">Peter Dell</a>
*
* This file is part of WUDSN IDE.
*
* WUDSN IDE is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* WUDSN IDE is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.lng.pas.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding C64 compilers.
*
* @author Peter Dell
*
*/
public final class PascalPreferencesC64CompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public PascalPreferencesC64CompilersPage() {
super(Language.ASM, Hardware.C64);
}
}

41
com.wudsn.ide.pas/src/com/wudsn/ide/lng/pas/preferences/PascalPreferencesNESCompilersPage.java Normal file
View File

@ -0,0 +1,41 @@
/**
* Copyright (C) 2009 - 2021 <a href="https://www.wudsn.com" target="_top">Peter Dell</a>
*
* This file is part of WUDSN IDE.
*
* WUDSN IDE is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* WUDSN IDE is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with WUDSN IDE. If not, see <http://www.gnu.org/licenses/>.
*/
package com.wudsn.ide.lng.pas.preferences;
import com.wudsn.ide.base.hardware.Hardware;
import com.wudsn.ide.lng.Language;
import com.wudsn.ide.lng.preferences.LanguagePreferencesCompilersPage;
/**
* Visual editor page for the assembler preferences regarding NES compilers.
*
* @author Peter Dell
*
*/
public final class PascalPreferencesNESCompilersPage extends LanguagePreferencesCompilersPage {
/**
* Create is public. Used by extension point "org.eclipse.ui.preferencePages".
*/
public PascalPreferencesNESCompilersPage() {
super(Language.ASM,Hardware.NES);
}
}