65CE02 Opcode matrix:

imm = #$00
imw = #$0000
zp = $00
zpx = $00,X
zpy = $00,Y
izx = ($00,X)
izy = ($00),Y
izz = ($00),Z
isy = ($00,S),Y
abs = $0000
abx = $0000,X
aby = $0000,Y
ind = ($0000)
iax = ($0000,X)
rel = $0000 (8 bits PC-relative)
rell = $0000 (16 bits PC-relative)


  x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x BRK
7
ORA
izx 6
CLE
2
SEE
2
TSB
zp 5
ORA
zp 3
ASL
zp 5
RMB0
zp 5
PHP
3
ORA
imm 2
ASL
2
TSY
2
TSB
abs 6
ORA
abs 4
ASL
abs 6
BBR0
rel 2*
1x BPL
rel 2*
ORA
izy 5*
ORA
izz 5
BPL
rell 3*
TRB
zp 5
ORA
zpx 4
ASL
zpx 6
RMB1
zp 5
CLC
2
ORA
aby 4*
INC
2
INZ
2
TRB
abs 6
ORA
abx 4*
ASL
abx 6*
BBR1
rel 2*
2x JSR
abs 6
AND
izx 6
JSR
iab 6
JSR
iax 6
BIT
zp 3
AND
zp 3
ROL
zp 5
RMB2
zp 5
PLP
4
AND
imm 2
ROL
2
TYS
2
BIT
abs 4
AND
abs 4
ROL
abs 6
BBR2
rel 2*
3x BMI
rel 2*
AND
izy 5*
AND
izz 5
BMI
rell 3*
BIT
zpx 4
AND
zpx 4
ROL
zpx 6
RMB3
zp 5
SEC
2
AND
aby 4*
DEC
2
DEZ
2
BIT
abx 4*
AND
abx 4*
ROL
abx 6*
BBR3
rel 2*
4x RTI
6
EOR
izx 6
NEG
2
ASR
2
ASR
zp 5
EOR
zp 3
LSR
zp 5
RMB4
zp 5
PHA
3
EOR
imm 2
LSR
2
TAZ
2
JMP
abs 3
EOR
abs 4
LSR
abs 6
BBR4
rel 2*
5x BVC
rel 2*
EOR
izy 5*
EOR
izz 5
BVC
rell 3*
ASR
zpx 6
EOR
zpx 4
LSR
zpx 6
RMB5
zp 5
CLI
2
EOR
aby 4*
PHY
3
TAB
2
MAP
2
EOR
abx 4*
LSR
abx 6*
BBR5
rel 2*
6x RTS
6
ADC
izx 6
RTS
imm 6
BSR
rell 3*
STZ
zp 3
ADC
zp 3
ROR
zp 5
RMB6
zp 5
PLA
4
ADC
imm 2
ROR
2
TZA
2
JMP
ind 6
ADC
abs 4
ROR
abs 6
BBR6
rel 2*
7x BVS
rel 2*
ADC
izy 5*
ADC
izz 5
BVS
rell 3*
STZ
zpx 4
ADC
zpx 4
ROR
zpx 6
RMB7
zp 5
SEI
2
ADC
aby 4*
PLY
4
TBA
2
JMP
iax 6
ADC
abx 4*
ROR
abx 6*
BBR7
rel 2*
8x BRA
rel 3*
STA
izx 6
STA
isy 7
BRA
rell 4
STY
zp 3
STA
zp 3
STX
zp 3
SMB0
zp 5
DEY
2
BIT
imm 2
TXA
2
STY
abx 5
STY
abs 4
STA
abs 4
STX
abs 4
BBS0
rel 2*
9x BCC
rel 2*
STA
izy 6
STA
izz 5
BCC
rell 3*
STY
zpx 4
STA
zpx 4
STX
zpy 4
SMB1
zp 5
TYA
2
STA
aby 5
TXS
2
STX
aby 5
STZ
abs 4
STA
abx 5
STZ
abx 5
BBS1
rel 2*
Ax LDY
imm 2
LDA
izx 6
LDX
imm 2
LDZ
imm 2
LDY
zp 3
LDA
zp 3
LDX
zp 3
SMB2
zp 5
TAY
2
LDA
imm 2
TAX
2
LDZ
abs 4
LDY
abs 4
LDA
abs 4
LDX
abs 4
BBS2
rel 2*
Bx BCS
rel 2*
LDA
izy 5*
LDA
izz 5
BCS
rell 3*
LDY
zpx 4
LDA
zpx 4
LDX
zpy 4
SMB3
zp 5
CLV
2
LDA
aby 4*
TSX
2
LDZ
abx 4*
LDY
abx 4*
LDA
abx 4*
LDX
aby 4*
BBS3
rel 2*
Cx CPY
imm 2
CMP
izx 6
CPZ
imm 2
DEW
zp 6
CPY
zp 3
CMP
zp 3
DEC
zp 5
SMB4
zp 5
INY
2
CMP
imm 2
DEX
2
ASW
abs 7
CPY
abs 4
CMP
abs 4
DEC
abs 6
BBS4
rel 2*
Dx BNE
rel 2*
CMP
izy 5*
CMP
izz 5
BNE
rell 3*
CPZ
zp 3
CMP
zpx 4
DEC
zpx 6
SMB5
zp 5
CLD
2
CMP
aby 4*
PHX
3
PHZ
3
CPZ
abs 4
CMP
abx 4*
DEC
abx 6*
BBS5
rel 2*
Ex CPX
imm 2
SBC
izx 6
LDA
isy 7
INW
zp 6
CPX
zp 3
SBC
zp 3
INC
zp 5
SMB6
zp 5
INX
2
SBC
imm 2
NOP
2
ROW
abs 7
CPX
abs 4
SBC
abs 4
INC
abs 6
BBS6
rel 2*
Fx BEQ
rel 2*
SBC
izy 5*
SBC
izz 5
BEQ
rell 3*
PHW
imw 4
SBC
zpx 4
INC
zpx 6
SMB7
zp 5
SED
2
SBC
aby 4*
PLX
4
PLZ
4
PHW
abs 4
SBC
abx 4*
INC
abx 6*
BBS7
rel 2*

"*" : add 1 cycle if page boundary is crossed.
add 1 cycle if direct page register is non zero on direct page adressing modes.
add 1 cycle on conditional branches if taken.
add 1 cycle on these commands if D=1: ADC, SBC


A = Akkumulator
B = Bank-Register
X = X-Register
Y = Y-Register
Z = Z-Register
S = Stack-Pointer
P = Status-Register
+(S) = Stack-Pointer relative with pre-increment
(S)- = Stack-Pointer relative with post-decrement



These things have changed from 65C02 to 65CE02:

- new instructions.
- new adressing modes for a few instrucions.
- Z-Register is introduced.
- with the introduction of the Z-Register, also the IZP adressing mode has been changed to IZZ.

65CE02 opcodes:
OpcodeFunction NVBDIZC
CPZZ-{adr} *    **
DECA:=A-1 *    * 
DEZZ:=Z-1 *    * 
DEW{adr}:={adr}-1 (16 bit) *    * 
INCA:=A+1 *    * 
INZZ:=Z+1 *    * 
INW{adr}:={adr}+1 (16 bit) *    * 
NEGA:=0-A *    * 
ASR{adr}:={adr}/2 *    **
ASW{adr}:={adr}*2 (16 bit) *    **
ROW{adr}:={adr}*2+C (16 bit) *    **
LDZZ:={adr} *    * 
STZ{adr}:=Z        
TABB:=A *    * 
TBAA:=B *    * 
TAZZ:=A *    * 
TZAA:=Z *    * 
TSYY:=S *    * 
TYSS:=Y        
PHW(S)-:={adr} (16 bit)        
PHX(S)-:=X        
PHY(S)-:=Y        
PHZ(S)-:=Z        
PLXX:=+(S) *    * 
PLYY:=+(S) *    * 
PLZZ:=+(S) *    * 
TRB{adr}:={adr} nand A      * 
TSB{adr}:={adr} or A      * 
CLEE:=0 ?        
SEEE:=1 ?        
BRAbranch always        
BSR(S)-:=PC / branch always        
BBRnbranch on bit n reset        
BBSnbranch on bit n set        
RMBn{adr}:={adr} nand 2^n      * 
SMBn{adr}:={adr} or 2^n      * 
MAP?        

Warning! Some information is based on 65C02 documents, others is just guessed. There might be some mistakes in here.


© 2009 Graham. Last change on 30.1.2009.