From c96399d896aa1aeb9b2f499675d7a5cf616d7ca5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Carl-Henrik=20Sk=C3=A5rstedt?= Date: Thu, 10 Dec 2015 22:27:49 -0800 Subject: [PATCH] Adding read-only labels to disassembler and Atari 7800 memory map file - Changed how the instruction lookup is stored to more easily distinguish between read-only and other instructions - Added Atari 7800 labels (a78.lbl) - Added a keyword "read" to declare a read-only version of a data label to the labels file - Fixes to determining addresses representing data or code - Fixed missing data blocks that were exactly 16 bytes --- disassembler/README.MD | 14 + disassembler/a78.lbl | 100 ++ disassembler/x65dsasm.cpp | 1997 ++++++++++++++++++++++--------------- 3 files changed, 1286 insertions(+), 825 deletions(-) create mode 100644 disassembler/a78.lbl diff --git a/disassembler/README.MD b/disassembler/README.MD index cd9947c..795b5f3 100644 --- a/disassembler/README.MD +++ b/disassembler/README.MD @@ -26,6 +26,9 @@ x65dsasm binary disasm.txt [$skip[-$end]] [addr=$xxxx] [cpu=6502/65C02/65816] ### Updates +* a78.lbl file defining Atari 7800 hardware addresses +* Switched the instruction info around to more easily determine read-only instructions +* Various improvements distinguishing between code and data * c64.lbl file defining all c64 hardware addresses * Tracking label references outside of the code including zero page * Data / Code distinction improvements @@ -47,13 +50,24 @@ A special data format is pointers indicating a function pointer table, the label defined with a range to limit the size. Each pointer within the pointer table will be assigned a code label. +If the keyword "pointers" is followed by the word "data" the pointers will be interpreted as +data pointers instead of code pointers. + +A label can be redefined with a different name for read-only instructions by using the keyword +read after the address. The label must first be defined as a data label to be assigned a +read-only name. Read only instructions include ora, and, bit, eor, adc, sbc, lda, ldx, ldy, cmp, cpy and cpx. + + Example labels file: ``` +TIA_VSYNC = $00 data +TIA_CXM0P = $00 read Init = $1000 code Entry point into code SinTable = $1400 data 256 byte sinus table Interrupt = $10f3 code Interrupt code Callbacks = $1123-$112b pointers Array of function pointers +MapRefs = $1200-$1240 pointers data Array of data pointers VIC_Sprite0_x = $d000 set sprite 0 x position VIC_Sprite0_y = $d001 set sprite 0 y position VIC_Sprite1_x = $d002 set sprite 1 x position diff --git a/disassembler/a78.lbl b/disassembler/a78.lbl new file mode 100644 index 0000000..b1ff9b1 --- /dev/null +++ b/disassembler/a78.lbl @@ -0,0 +1,100 @@ +TIA_VSYNC = $00 data +TIA_VBLANK = $01 data +TIA_WSYNC = $02 data +TIA_RSYNC = $03 data +TIA_NUSIZ0 = $04 data +TIA_NUSIZ1 = $05 data +TIA_COLUP0 = $06 data +TIA_COLUP1 = $07 data +TIA_COLUPF = $08 data +TIA_COLUBK = $09 data +TIA_CTRLPF = $0A data +TIA_REFP0 = $0B data +TIA_REFP1 = $0C data +TIA_PF0 = $0D data +TIA_PF1 = $0E data +TIA_PF2 = $0F data +TIA_RESP0 = $10 data +TIA_RESP1 = $11 data +TIA_RESM0 = $12 data +TIA_RESM1 = $13 data +TIA_RESBL = $14 data +TIA_AUDC0 = $15 data +TIA_AUDC1 = $16 data +TIA_AUDF0 = $17 data +TIA_AUDF1 = $18 data +TIA_AUDV0 = $19 data +TIA_AUDV1 = $1A data +TIA_GRP0 = $1B data +TIA_GRP1 = $1C data +TIA_ENAM0 = $1D data +TIA_ENAM1 = $1E data +TIA_ENABL = $1F data +TIA_HMP0 = $20 data +TIA_HMP1 = $21 data +TIA_HMM0 = $22 data +TIA_HMM1 = $23 data +TIA_HMBL = $24 data +TIA_VDELP0 = $25 data +TIA_VDELP1 = $26 data +TIA_VDELBL = $27 data +TIA_RESMP0 = $28 data +TIA_RESMP1 = $29 data +TIA_HMOVE = $2A data +TIA_HMCLR = $2B data +TIA_CXCLR = $2C data + +TIA_CXM0P = $00 read +TIA_CXM1P = $01 read +TIA_CXP0FB = $02 read +TIA_CXP1FB = $03 read +TIA_CXM0FB = $04 read +TIA_CXM1FB = $05 read +TIA_CXBLPF = $06 read +TIA_CXPPMM = $07 read +TIA_INPT0 = $08 read +TIA_INPT1 = $09 read +TIA_INPT2 = $0A read +TIA_INPT3 = $0B read +TIA_INPT4 = $0C read +TIA_INPT5 = $0D read + +MARIA_Bkg_col = $0020 data +MARIA_pal_0_col_1 = $0021 data +MARIA_pal_0_col_2 = $0022 data +MARIA_pal_0_col_3 = $0023 data +MARIA_Wait_Sync = $0024 data +MARIA_pal_1_col_1 = $0025 data +MARIA_pal_1_col_2 = $0026 data +MARIA_pal_1_col_3 = $0027 data +MARIA_Status = $0028 data +MARIA_pal_2_col_1 = $0029 data +MARIA_pal_2_col_2 = $002A data +MARIA_pal_2_col_3 = $002B data +MARIA_Disp_List_Hi = $002C data +MARIA_pal_3_col_1 = $002D data +MARIA_pal_3_col_2 = $002E data +MARIA_pal_3_col_3 = $002F data +MARIA_Disp_List_Lo = $0030 data +MARIA_pal_4_col_1 = $0031 data +MARIA_pal_4_col_2 = $0032 data +MARIA_pal_4_col_3 = $0033 data +MARIA_Charbase = $0034 data +MARIA_pal_5_col_1 = $0035 data +MARIA_pal_5_col_2 = $0036 data +MARIA_pal_5_col_3 = $0037 data +MARIA_pal_6_col_1 = $0039 data +MARIA_pal_6_col_2 = $003A data +MARIA_pal_6_col_3 = $003B data +MARIA_CTRL = $003C data +MARIA_pal_7_col_1 = $003D data +MARIA_pal_7_col_2 = $003E data +MARIA_pal_7_col_3 = $003F data + +RIOT_IO = $0280 data +RIOT_IO_END = $0300 data +RIOT_RAM = $0480 data +RIOT_RAM_END = $0500 data +RAM = $1800 data +RAM_END = $2800 data + \ No newline at end of file diff --git a/disassembler/x65dsasm.cpp b/disassembler/x65dsasm.cpp index 0547983..10aecbc 100644 --- a/disassembler/x65dsasm.cpp +++ b/disassembler/x65dsasm.cpp @@ -107,6 +107,50 @@ static const char* aAddrModeFmtSrc[] = { "%s %s", // 1b }; +const char *AddressModeNames[] { + // address mode bit index + + // 6502 + + "AM_ZP_REL_X", // 0 ($12",x) + "AM_ZP", // 1 $12 + "AM_IMM", // 2 #$12 + "AM_ABS", // 3 $1234 + "AM_ZP_Y_REL", // 4 ($12)",y + "AM_ZP_X", // 5 $12",x + "AM_ABS_Y", // 6 $1234",y + "AM_ABS_X", // 7 $1234",x + "AM_REL", // 8 ($1234) + "AM_ACC", // 9 A + "AM_NON", // a + + // 65C02 + + "AM_ZP_REL", // b ($12) + "AM_REL_X", // c ($1234",x) + "AM_ZP_ABS", // d $12", *+$12 + + // 65816 + + "AM_ZP_REL_L", // e [$02] + "AM_ZP_REL_Y_L", // f [$00]",y + "AM_ABS_L", // 10 $bahilo + "AM_ABS_L_X", // 11 $123456",x + "AM_STK", // 12 $12",s + "AM_STK_REL_Y", // 13 ($12",s)",y + "AM_REL_L", // 14 [$1234] + "AM_BLK_MOV", // 15 $12",$34 + + "AM_ZP_Y", // 16 stx/ldx + "AM_ZP_REL_Y", // 17 sax/lax/ahx + + "AM_IMM_DBL_A", // 18 #$12/#$1234 + "AM_IMM_DBL_I", // 19 #$12/#$1234 + + "AM_BRANCH", // 1a beq $1234 + "AM_BRANCH_L", // 1b brl $1234 +}; + enum AddressModes { // address mode bit index @@ -124,13 +168,13 @@ enum AddressModes { AM_ACC, // 9 A AM_NON, // a - // 65C02 + // 65C02 AM_ZP_REL, // b ($12) AM_REL_X, // c ($1234,x) AM_ZP_ABS, // d $12, *+$12 - // 65816 + // 65816 AM_ZP_REL_L, // e [$02] AM_ZP_REL_Y_L, // f [$00],y @@ -147,793 +191,1057 @@ enum AddressModes { AM_IMM_DBL_A, // 18 #$12/#$1234 AM_IMM_DBL_I, // 19 #$12/#$1234 - AM_BRANCH, // beq $1234 - AM_BRANCH_L, // brl $1234 + AM_BRANCH, // 1a beq $1234 + AM_BRANCH_L, // 1b brl $1234 AM_COUNT, }; +enum MNM_Base { + mnm_brk, + mnm_ora, + mnm_cop, + mnm_tsb, + mnm_asl, + mnm_php, + mnm_phd, + mnm_bpl, + mnm_trb, + mnm_clc, + mnm_inc, + mnm_tcs, + mnm_jsr, + mnm_and, + mnm_bit, + mnm_rol, + mnm_plp, + mnm_pld, + mnm_bmi, + mnm_sec, + mnm_dec, + mnm_tsc, + mnm_rti, + mnm_eor, + mnm_wdm, + mnm_mvp, + mnm_lsr, + mnm_pha, + mnm_phk, + mnm_jmp, + mnm_bvc, + mnm_mvn, + mnm_cli, + mnm_phy, + mnm_tcd, + mnm_rts, + mnm_adc, + mnm_per, + mnm_stz, + mnm_ror, + mnm_rtl, + mnm_bvs, + mnm_sei, + mnm_ply, + mnm_tdc, + mnm_bra, + mnm_sta, + mnm_brl, + mnm_sty, + mnm_stx, + mnm_dey, + mnm_txa, + mnm_phb, + mnm_bcc, + mnm_tya, + mnm_txs, + mnm_txy, + mnm_ldy, + mnm_lda, + mnm_ldx, + mnm_tay, + mnm_tax, + mnm_plb, + mnm_bcs, + mnm_clv, + mnm_tsx, + mnm_tyx, + mnm_cpy, + mnm_cmp, + mnm_rep, + mnm_iny, + mnm_dex, + mnm_wai, + mnm_bne, + mnm_pei, + mnm_cld, + mnm_phx, + mnm_stp, + mnm_cpx, + mnm_sbc, + mnm_sep, + mnm_inx, + mnm_nop, + mnm_xba, + mnm_beq, + mnm_pea, + mnm_sed, + mnm_plx, + mnm_xce, + mnm_inv, + mnm_pla, + mnm_bbs0, + mnm_bbs1, + mnm_bbs2, + mnm_bbs3, + mnm_bbs4, + mnm_bbs5, + mnm_bbs6, + mnm_bbs7, + mnm_bbr0, + mnm_bbr1, + mnm_bbr2, + mnm_bbr3, + mnm_bbr4, + mnm_bbr5, + mnm_bbr6, + mnm_bbr7, + mnm_ahx, + mnm_anc, + mnm_aac, + mnm_alr, + mnm_axs, + mnm_dcp, + mnm_isc, + mnm_lax, + mnm_lax2, + mnm_rla, + mnm_rra, + mnm_sre, + mnm_sax, + mnm_slo, + mnm_xaa, + mnm_arr, + mnm_tas, + mnm_shy, + mnm_shx, + mnm_las, + mnm_sbi, + + mnm_count +}; + +const char *zsMNM[mnm_count] { + "brk", + "ora", + "cop", + "tsb", + "asl", + "php", + "phd", + "bpl", + "trb", + "clc", + "inc", + "tcs", + "jsr", + "and", + "bit", + "rol", + "plp", + "pld", + "bmi", + "sec", + "dec", + "tsc", + "rti", + "eor", + "wdm", + "mvp", + "lsr", + "pha", + "phk", + "jmp", + "bvc", + "mvn", + "cli", + "phy", + "tcd", + "rts", + "adc", + "per", + "stz", + "ror", + "rtl", + "bvs", + "sei", + "ply", + "tdc", + "bra", + "sta", + "brl", + "sty", + "stx", + "dey", + "txa", + "phb", + "bcc", + "tya", + "txs", + "txy", + "ldy", + "lda", + "ldx", + "tay", + "tax", + "plb", + "bcs", + "clv", + "tsx", + "tyx", + "cpy", + "cmp", + "rep", + "iny", + "dex", + "wai", + "bne", + "pei", + "cld", + "phx", + "stp", + "cpx", + "sbc", + "sep", + "inx", + "nop", + "xba", + "beq", + "pea", + "sed", + "plx", + "xce", + "???", + "pla", + "bbs0", + "bbs1", + "bbs2", + "bbs3", + "bbs4", + "bbs5", + "bbs6", + "bbs7", + "bbr0", + "bbr1", + "bbr2", + "bbr3", + "bbr4", + "bbr5", + "bbr6", + "bbr7", + "ahx", + "anc", + "aac", + "alr", + "axs", + "dcp", + "isc", + "lax", + "lax2", + "rla", + "rra", + "sre", + "sax", + "slo", + "xaa", + "arr", + "tas", + "shy", + "shx", + "las", + "sbi", +}; + struct dismnm { - const char *name; + MNM_Base mnemonic; unsigned char addrMode; unsigned char arg_size; }; struct dismnm a6502_ops[256] = { - { "brk", AM_NON, 0x00 }, - { "ora", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "slo", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "ora", AM_ZP, 0x01 }, - { "asl", AM_ZP, 0x01 }, - { "slo", AM_ZP, 0x01 }, - { "php", AM_NON, 0x00 }, - { "ora", AM_IMM, 0x01 }, - { "asl", AM_NON, 0x00 }, - { "anc", AM_IMM, 0x01 }, - { "???", AM_NON, 0x00 }, - { "ora", AM_ABS, 0x02 }, - { "asl", AM_ABS, 0x02 }, - { "slo", AM_ABS, 0x02 }, - { "bpl", AM_BRANCH, 0x01 }, - { "ora", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "slo", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "ora", AM_ZP_X, 0x01 }, - { "asl", AM_ZP_X, 0x01 }, - { "slo", AM_ZP_X, 0x01 }, - { "clc", AM_NON, 0x00 }, - { "ora", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "slo", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "ora", AM_ABS_X, 0x02 }, - { "asl", AM_ABS_X, 0x02 }, - { "slo", AM_ABS_X, 0x02 }, - { "jsr", AM_ABS, 0x02 }, - { "and", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "rla", AM_ZP_REL_X, 0x01 }, - { "bit", AM_ZP, 0x01 }, - { "and", AM_ZP, 0x01 }, - { "rol", AM_ZP, 0x01 }, - { "rla", AM_ZP, 0x01 }, - { "plp", AM_NON, 0x00 }, - { "and", AM_IMM, 0x01 }, - { "rol", AM_NON, 0x00 }, - { "aac", AM_IMM, 0x01 }, - { "bit", AM_ABS, 0x02 }, - { "and", AM_ABS, 0x02 }, - { "rol", AM_ABS, 0x02 }, - { "rla", AM_ABS, 0x02 }, - { "bmi", AM_BRANCH, 0x01 }, - { "and", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "rla", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "and", AM_ZP_X, 0x01 }, - { "rol", AM_ZP_X, 0x01 }, - { "rla", AM_ZP_X, 0x01 }, - { "sec", AM_NON, 0x00 }, - { "and", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "rla", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "and", AM_ABS_X, 0x02 }, - { "rol", AM_ABS_X, 0x02 }, - { "rla", AM_ABS_X, 0x02 }, - { "rti", AM_NON, 0x00 }, - { "eor", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "sre", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "eor", AM_ZP, 0x01 }, - { "lsr", AM_ZP, 0x01 }, - { "sre", AM_ZP, 0x01 }, - { "pha", AM_NON, 0x00 }, - { "eor", AM_IMM, 0x01 }, - { "lsr", AM_NON, 0x00 }, - { "alr", AM_IMM, 0x01 }, - { "jmp", AM_ABS, 0x02 }, - { "eor", AM_ABS, 0x02 }, - { "lsr", AM_ABS, 0x02 }, - { "sre", AM_ABS, 0x02 }, - { "bvc", AM_BRANCH, 0x01 }, - { "eor", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "sre", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "eor", AM_ZP_X, 0x01 }, - { "lsr", AM_ZP_X, 0x01 }, - { "sre", AM_ZP_X, 0x01 }, - { "cli", AM_NON, 0x00 }, - { "eor", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "sre", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "eor", AM_ABS_X, 0x02 }, - { "lsr", AM_ABS_X, 0x02 }, - { "sre", AM_ABS_X, 0x02 }, - { "rts", AM_NON, 0x00 }, - { "adc", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "rra", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "adc", AM_ZP, 0x01 }, - { "ror", AM_ZP, 0x01 }, - { "rra", AM_ZP, 0x01 }, - { "pla", AM_NON, 0x00 }, - { "adc", AM_IMM, 0x01 }, - { "ror", AM_NON, 0x00 }, - { "arr", AM_IMM, 0x01 }, - { "jmp", AM_REL, 0x02 }, - { "adc", AM_ABS, 0x02 }, - { "ror", AM_ABS, 0x02 }, - { "rra", AM_ABS, 0x02 }, - { "bvs", AM_BRANCH, 0x01 }, - { "adc", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "rra", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "adc", AM_ZP_X, 0x01 }, - { "ror", AM_ZP_X, 0x01 }, - { "rra", AM_ZP_X, 0x01 }, - { "sei", AM_NON, 0x00 }, - { "adc", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "rra", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "adc", AM_ABS_X, 0x02 }, - { "ror", AM_ABS_X, 0x02 }, - { "rra", AM_ABS_X, 0x02 }, - { "???", AM_NON, 0x00 }, - { "sta", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "sax", AM_ZP_REL_Y, 0x01 }, - { "sty", AM_ZP, 0x01 }, - { "sta", AM_ZP, 0x01 }, - { "stx", AM_ZP, 0x01 }, - { "sax", AM_ZP, 0x01 }, - { "dey", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "txa", AM_NON, 0x00 }, - { "xaa", AM_IMM, 0x01 }, - { "sty", AM_ABS, 0x02 }, - { "sta", AM_ABS, 0x02 }, - { "stx", AM_ABS, 0x02 }, - { "sax", AM_ABS, 0x02 }, - { "bcc", AM_BRANCH, 0x01 }, - { "sta", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "ahx", AM_ZP_REL_Y, 0x01 }, - { "sty", AM_ZP_X, 0x01 }, - { "sta", AM_ZP_X, 0x01 }, - { "stx", AM_ZP_Y, 0x01 }, - { "sax", AM_ZP_Y, 0x01 }, - { "tya", AM_NON, 0x00 }, - { "sta", AM_ABS_Y, 0x02 }, - { "txs", AM_NON, 0x00 }, - { "tas", AM_ABS_Y, 0x02 }, - { "shy", AM_ABS_X, 0x02 }, - { "sta", AM_ABS_X, 0x02 }, - { "shx", AM_ABS_Y, 0x02 }, - { "ahx", AM_ABS_Y, 0x02 }, - { "ldy", AM_IMM, 0x01 }, - { "lda", AM_ZP_REL_X, 0x01 }, - { "ldx", AM_IMM, 0x01 }, - { "lax", AM_ZP_REL_Y, 0x01 }, - { "ldy", AM_ZP, 0x01 }, - { "lda", AM_ZP, 0x01 }, - { "ldx", AM_ZP, 0x01 }, - { "lax", AM_ZP, 0x01 }, - { "tay", AM_NON, 0x00 }, - { "lda", AM_IMM, 0x01 }, - { "tax", AM_NON, 0x00 }, - { "lax2", AM_IMM, 0x01 }, - { "ldy", AM_ABS, 0x02 }, - { "lda", AM_ABS, 0x02 }, - { "ldx", AM_ABS, 0x02 }, - { "lax", AM_ABS, 0x02 }, - { "bcs", AM_BRANCH, 0x01 }, - { "lda", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "ldy", AM_ZP_X, 0x01 }, - { "lda", AM_ZP_X, 0x01 }, - { "ldx", AM_ZP_Y, 0x01 }, - { "lax", AM_ZP_Y, 0x01 }, - { "clv", AM_NON, 0x00 }, - { "lda", AM_ABS_Y, 0x02 }, - { "tsx", AM_NON, 0x00 }, - { "las", AM_ABS_Y, 0x02 }, - { "ldy", AM_ABS_X, 0x02 }, - { "lda", AM_ABS_X, 0x02 }, - { "ldx", AM_ABS_Y, 0x02 }, - { "lax", AM_ABS_Y, 0x02 }, - { "cpy", AM_IMM, 0x01 }, - { "cmp", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "dcp", AM_ZP_REL_X, 0x01 }, - { "cpy", AM_ZP, 0x01 }, - { "cmp", AM_ZP, 0x01 }, - { "dec", AM_ZP, 0x01 }, - { "dcp", AM_ZP, 0x01 }, - { "iny", AM_NON, 0x00 }, - { "cmp", AM_IMM, 0x01 }, - { "dex", AM_NON, 0x00 }, - { "axs", AM_IMM, 0x01 }, - { "cpy", AM_ABS, 0x02 }, - { "cmp", AM_ABS, 0x02 }, - { "dec", AM_ABS, 0x02 }, - { "dcp", AM_ABS, 0x02 }, - { "bne", AM_BRANCH, 0x01 }, - { "cmp", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "dcp", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "cmp", AM_ZP_X, 0x01 }, - { "dec", AM_ZP_X, 0x01 }, - { "dcp", AM_ZP_X, 0x01 }, - { "cld", AM_NON, 0x00 }, - { "cmp", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "dcp", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "cmp", AM_ABS_X, 0x02 }, - { "dec", AM_ABS_X, 0x02 }, - { "dcp", AM_ABS_X, 0x02 }, - { "cpx", AM_IMM, 0x01 }, - { "sbc", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "isc", AM_ZP_REL_X, 0x01 }, - { "cpx", AM_ZP, 0x01 }, - { "sbc", AM_ZP, 0x01 }, - { "inc", AM_ZP, 0x01 }, - { "isc", AM_ZP, 0x01 }, - { "inx", AM_NON, 0x00 }, - { "sbc", AM_IMM, 0x01 }, - { "nop", AM_NON, 0x00 }, - { "sbi", AM_IMM, 0x01 }, - { "cpx", AM_ABS, 0x02 }, - { "sbc", AM_ABS, 0x02 }, - { "inc", AM_ABS, 0x02 }, - { "isc", AM_ABS, 0x02 }, - { "beq", AM_BRANCH, 0x01 }, - { "sbc", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "isc", AM_ZP_Y_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "sbc", AM_ZP_X, 0x01 }, - { "inc", AM_ZP_X, 0x01 }, - { "isc", AM_ZP_X, 0x01 }, - { "sed", AM_NON, 0x00 }, - { "sbc", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "isc", AM_ABS_Y, 0x02 }, - { "???", AM_NON, 0x00 }, - { "sbc", AM_ABS_X, 0x02 }, - { "inc", AM_ABS_X, 0x02 }, - { "isc", AM_ABS_X, 0x02 }, + { mnm_brk, AM_NON, 0}, + { mnm_ora, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_slo, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ora, AM_ZP, 1 }, + { mnm_asl, AM_ZP, 1 }, + { mnm_slo, AM_ZP, 1 }, + { mnm_php, AM_NON, 0 }, + { mnm_ora, AM_IMM, 1 }, + { mnm_asl, AM_NON, 0 }, + { mnm_anc, AM_IMM, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ora, AM_ABS, 2 }, + { mnm_asl, AM_ABS, 2 }, + { mnm_slo, AM_ABS, 2 }, + { mnm_bpl, AM_BRANCH, 1 }, + { mnm_ora, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_slo, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ora, AM_ZP_X, 1 }, + { mnm_asl, AM_ZP_X, 1 }, + { mnm_slo, AM_ZP_X, 1 }, + { mnm_clc, AM_NON, 0 }, + { mnm_ora, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_slo, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ora, AM_ABS_X, 2 }, + { mnm_asl, AM_ABS_X, 2 }, + { mnm_slo, AM_ABS_X, 2 }, + { mnm_jsr, AM_ABS, 2 }, + { mnm_and, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_rla, AM_ZP_REL_X, 1 }, + { mnm_bit, AM_ZP, 1 }, + { mnm_and, AM_ZP, 1 }, + { mnm_rol, AM_ZP, 1 }, + { mnm_rla, AM_ZP, 1 }, + { mnm_plp, AM_NON, 0 }, + { mnm_and, AM_IMM, 1 }, + { mnm_rol, AM_NON, 0 }, + { mnm_aac, AM_IMM, 1 }, + { mnm_bit, AM_ABS, 2 }, + { mnm_and, AM_ABS, 2 }, + { mnm_rol, AM_ABS, 2 }, + { mnm_rla, AM_ABS, 2 }, + { mnm_bmi, AM_BRANCH, 1 }, + { mnm_and, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_rla, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_and, AM_ZP_X, 1 }, + { mnm_rol, AM_ZP_X, 1 }, + { mnm_rla, AM_ZP_X, 1 }, + { mnm_sec, AM_NON, 0 }, + { mnm_and, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_rla, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_and, AM_ABS_X, 2 }, + { mnm_rol, AM_ABS_X, 2 }, + { mnm_rla, AM_ABS_X, 2 }, + { mnm_rti, AM_NON, 0 }, + { mnm_eor, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sre, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_eor, AM_ZP, 1 }, + { mnm_lsr, AM_ZP, 1 }, + { mnm_sre, AM_ZP, 1 }, + { mnm_pha, AM_NON, 0 }, + { mnm_eor, AM_IMM, 1 }, + { mnm_lsr, AM_NON, 0 }, + { mnm_alr, AM_IMM, 1 }, + { mnm_jmp, AM_ABS, 2 }, + { mnm_eor, AM_ABS, 2 }, + { mnm_lsr, AM_ABS, 2 }, + { mnm_sre, AM_ABS, 2 }, + { mnm_bvc, AM_BRANCH, 1 }, + { mnm_eor, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sre, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_eor, AM_ZP_X, 1 }, + { mnm_lsr, AM_ZP_X, 1 }, + { mnm_sre, AM_ZP_X, 1 }, + { mnm_cli, AM_NON, 0 }, + { mnm_eor, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sre, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_eor, AM_ABS_X, 2 }, + { mnm_lsr, AM_ABS_X, 2 }, + { mnm_sre, AM_ABS_X, 2 }, + { mnm_rts, AM_NON, 0 }, + { mnm_adc, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_rra, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_adc, AM_ZP, 1 }, + { mnm_ror, AM_ZP, 1 }, + { mnm_rra, AM_ZP, 1 }, + { mnm_pla, AM_NON, 0 }, + { mnm_adc, AM_IMM, 1 }, + { mnm_ror, AM_NON, 0 }, + { mnm_arr, AM_IMM, 1 }, + { mnm_jmp, AM_REL, 2 }, + { mnm_adc, AM_ABS, 2 }, + { mnm_ror, AM_ABS, 2 }, + { mnm_rra, AM_ABS, 2 }, + { mnm_bvs, AM_BRANCH, 1 }, + { mnm_adc, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_rra, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_adc, AM_ZP_X, 1 }, + { mnm_ror, AM_ZP_X, 1 }, + { mnm_rra, AM_ZP_X, 1 }, + { mnm_sei, AM_NON, 0 }, + { mnm_adc, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_rra, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_adc, AM_ABS_X, 2 }, + { mnm_ror, AM_ABS_X, 2 }, + { mnm_rra, AM_ABS_X, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sta, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sax, AM_ZP_REL_Y, 1 }, + { mnm_sty, AM_ZP, 1 }, + { mnm_sta, AM_ZP, 1 }, + { mnm_stx, AM_ZP, 1 }, + { mnm_sax, AM_ZP, 1 }, + { mnm_dey, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_txa, AM_NON, 0 }, + { mnm_xaa, AM_IMM, 1 }, + { mnm_sty, AM_ABS, 2 }, + { mnm_sta, AM_ABS, 2 }, + { mnm_stx, AM_ABS, 2 }, + { mnm_sax, AM_ABS, 2 }, + { mnm_bcc, AM_BRANCH, 1 }, + { mnm_sta, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ahx, AM_ZP_REL_Y, 1 }, + { mnm_sty, AM_ZP_X, 1 }, + { mnm_sta, AM_ZP_X, 1 }, + { mnm_stx, AM_ZP_Y, 1 }, + { mnm_sax, AM_ZP_Y, 1 }, + { mnm_tya, AM_NON, 0 }, + { mnm_sta, AM_ABS_Y, 2 }, + { mnm_txs, AM_NON, 0 }, + { mnm_tas, AM_ABS_Y, 2 }, + { mnm_shy, AM_ABS_X, 2 }, + { mnm_sta, AM_ABS_X, 2 }, + { mnm_shx, AM_ABS_Y, 2 }, + { mnm_ahx, AM_ABS_Y, 2 }, + { mnm_ldy, AM_IMM, 1 }, + { mnm_lda, AM_ZP_REL_X, 1 }, + { mnm_ldx, AM_IMM, 1 }, + { mnm_lax, AM_ZP_REL_Y, 1 }, + { mnm_ldy, AM_ZP, 1 }, + { mnm_lda, AM_ZP, 1 }, + { mnm_ldx, AM_ZP, 1 }, + { mnm_lax, AM_ZP, 1 }, + { mnm_tay, AM_NON, 0 }, + { mnm_lda, AM_IMM, 1 }, + { mnm_tax, AM_NON, 0 }, + { mnm_lax2, AM_IMM, 1 }, + { mnm_ldy, AM_ABS, 2 }, + { mnm_lda, AM_ABS, 2 }, + { mnm_ldx, AM_ABS, 2 }, + { mnm_lax, AM_ABS, 2 }, + { mnm_bcs, AM_BRANCH, 1 }, + { mnm_lda, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ldy, AM_ZP_X, 1 }, + { mnm_lda, AM_ZP_X, 1 }, + { mnm_ldx, AM_ZP_Y, 1 }, + { mnm_lax, AM_ZP_Y, 1 }, + { mnm_clv, AM_NON, 0 }, + { mnm_lda, AM_ABS_Y, 2 }, + { mnm_tsx, AM_NON, 0 }, + { mnm_las, AM_ABS_Y, 2 }, + { mnm_ldy, AM_ABS_X, 2 }, + { mnm_lda, AM_ABS_X, 2 }, + { mnm_ldx, AM_ABS_Y, 2 }, + { mnm_lax, AM_ABS_Y, 2 }, + { mnm_cpy, AM_IMM, 1 }, + { mnm_cmp, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_dcp, AM_ZP_REL_X, 1 }, + { mnm_cpy, AM_ZP, 1 }, + { mnm_cmp, AM_ZP, 1 }, + { mnm_dec, AM_ZP, 1 }, + { mnm_dcp, AM_ZP, 1 }, + { mnm_iny, AM_NON, 0 }, + { mnm_cmp, AM_IMM, 1 }, + { mnm_dex, AM_NON, 0 }, + { mnm_axs, AM_IMM, 1 }, + { mnm_cpy, AM_ABS, 2 }, + { mnm_cmp, AM_ABS, 2 }, + { mnm_dec, AM_ABS, 2 }, + { mnm_dcp, AM_ABS, 2 }, + { mnm_bne, AM_BRANCH, 1 }, + { mnm_cmp, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_dcp, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_cmp, AM_ZP_X, 1 }, + { mnm_dec, AM_ZP_X, 1 }, + { mnm_dcp, AM_ZP_X, 1 }, + { mnm_cld, AM_NON, 0 }, + { mnm_cmp, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_dcp, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_cmp, AM_ABS_X, 2 }, + { mnm_dec, AM_ABS_X, 2 }, + { mnm_dcp, AM_ABS_X, 2 }, + { mnm_cpx, AM_IMM, 1 }, + { mnm_sbc, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_isc, AM_ZP_REL_X, 1 }, + { mnm_cpx, AM_ZP, 1 }, + { mnm_sbc, AM_ZP, 1 }, + { mnm_inc, AM_ZP, 1 }, + { mnm_isc, AM_ZP, 1 }, + { mnm_inx, AM_NON, 0 }, + { mnm_sbc, AM_IMM, 1 }, + { mnm_nop, AM_NON, 0 }, + { mnm_sbi, AM_IMM, 1 }, + { mnm_cpx, AM_ABS, 2 }, + { mnm_sbc, AM_ABS, 2 }, + { mnm_inc, AM_ABS, 2 }, + { mnm_isc, AM_ABS, 2 }, + { mnm_beq, AM_BRANCH, 1 }, + { mnm_sbc, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_isc, AM_ZP_Y_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sbc, AM_ZP_X, 1 }, + { mnm_inc, AM_ZP_X, 1 }, + { mnm_isc, AM_ZP_X, 1 }, + { mnm_sed, AM_NON, 0 }, + { mnm_sbc, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_isc, AM_ABS_Y, 2 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sbc, AM_ABS_X, 2 }, + { mnm_inc, AM_ABS_X, 2 }, + { mnm_isc, AM_ABS_X, 2 }, }; struct dismnm a65C02_ops[256] = { - { "brk", AM_NON, 0x00 }, - { "ora", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "tsb", AM_ZP, 0x01 }, - { "ora", AM_ZP, 0x01 }, - { "asl", AM_ZP, 0x01 }, - { "???", AM_NON, 0x00 }, - { "php", AM_NON, 0x00 }, - { "ora", AM_IMM, 0x01 }, - { "asl", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "tsb", AM_ABS, 0x02 }, - { "ora", AM_ABS, 0x02 }, - { "asl", AM_ABS, 0x02 }, - { "bbr0", AM_ZP_ABS, 0x02 }, - { "bpl", AM_BRANCH, 0x01 }, - { "ora", AM_ZP_Y_REL, 0x01 }, - { "ora", AM_ZP_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "trb", AM_ZP, 0x01 }, - { "ora", AM_ZP_X, 0x01 }, - { "asl", AM_ZP_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "clc", AM_NON, 0x00 }, - { "ora", AM_ABS_Y, 0x02 }, - { "inc", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "trb", AM_ABS, 0x02 }, - { "ora", AM_ABS_X, 0x02 }, - { "asl", AM_ABS_X, 0x02 }, - { "bbr1", AM_ZP_ABS, 0x02 }, - { "jsr", AM_ABS, 0x02 }, - { "and", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "bit", AM_ZP, 0x01 }, - { "and", AM_ZP, 0x01 }, - { "rol", AM_ZP, 0x01 }, - { "???", AM_NON, 0x00 }, - { "plp", AM_NON, 0x00 }, - { "and", AM_IMM, 0x01 }, - { "rol", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "bit", AM_ABS, 0x02 }, - { "and", AM_ABS, 0x02 }, - { "rol", AM_ABS, 0x02 }, - { "bbr2", AM_ZP_ABS, 0x02 }, - { "bmi", AM_BRANCH, 0x01 }, - { "and", AM_ZP_Y_REL, 0x01 }, - { "and", AM_ZP_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "bit", AM_ZP_X, 0x01 }, - { "and", AM_ZP_X, 0x01 }, - { "rol", AM_ZP_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "sec", AM_NON, 0x00 }, - { "and", AM_ABS_Y, 0x02 }, - { "dec", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "bit", AM_ABS_X, 0x02 }, - { "and", AM_ABS_X, 0x02 }, - { "rol", AM_ABS_X, 0x02 }, - { "bbr3", AM_ZP_ABS, 0x02 }, - { "rti", AM_NON, 0x00 }, - { "eor", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "eor", AM_ZP, 0x01 }, - { "lsr", AM_ZP, 0x01 }, - { "???", AM_NON, 0x00 }, - { "pha", AM_NON, 0x00 }, - { "eor", AM_IMM, 0x01 }, - { "lsr", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "jmp", AM_ABS, 0x02 }, - { "eor", AM_ABS, 0x02 }, - { "lsr", AM_ABS, 0x02 }, - { "bbr4", AM_ZP_ABS, 0x02 }, - { "bvc", AM_BRANCH, 0x01 }, - { "eor", AM_ZP_Y_REL, 0x01 }, - { "eor", AM_ZP_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "eor", AM_ZP_X, 0x01 }, - { "lsr", AM_ZP_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "cli", AM_NON, 0x00 }, - { "eor", AM_ABS_Y, 0x02 }, - { "phy", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "eor", AM_ABS_X, 0x02 }, - { "lsr", AM_ABS_X, 0x02 }, - { "bbr5", AM_ZP_ABS, 0x02 }, - { "rts", AM_NON, 0x00 }, - { "adc", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "stz", AM_ZP, 0x01 }, - { "adc", AM_ZP, 0x01 }, - { "ror", AM_ZP, 0x01 }, - { "???", AM_NON, 0x00 }, - { "pla", AM_NON, 0x00 }, - { "adc", AM_IMM, 0x01 }, - { "ror", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "jmp", AM_REL, 0x02 }, - { "adc", AM_ABS, 0x02 }, - { "ror", AM_ABS, 0x02 }, - { "bbr6", AM_ZP_ABS, 0x02 }, - { "bvs", AM_BRANCH, 0x01 }, - { "adc", AM_ZP_Y_REL, 0x01 }, - { "adc", AM_ZP_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "stz", AM_ZP_X, 0x01 }, - { "adc", AM_ZP_X, 0x01 }, - { "ror", AM_ZP_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "sei", AM_NON, 0x00 }, - { "adc", AM_ABS_Y, 0x02 }, - { "ply", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "jmp", AM_REL_X, 0x02 }, - { "adc", AM_ABS_X, 0x02 }, - { "ror", AM_ABS_X, 0x02 }, - { "bbr7", AM_ZP_ABS, 0x02 }, - { "bra", AM_BRANCH, 0x01 }, - { "sta", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "sty", AM_ZP, 0x01 }, - { "sta", AM_ZP, 0x01 }, - { "stx", AM_ZP, 0x01 }, - { "???", AM_NON, 0x00 }, - { "dey", AM_NON, 0x00 }, - { "bit", AM_IMM, 0x01 }, - { "txa", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "sty", AM_ABS, 0x02 }, - { "sta", AM_ABS, 0x02 }, - { "stx", AM_ABS, 0x02 }, - { "bbs0", AM_ZP_ABS, 0x02 }, - { "bcc", AM_BRANCH, 0x01 }, - { "sta", AM_ZP_Y_REL, 0x01 }, - { "sta", AM_ZP_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "sty", AM_ZP_X, 0x01 }, - { "sta", AM_ZP_X, 0x01 }, - { "stx", AM_ZP_Y, 0x01 }, - { "???", AM_NON, 0x00 }, - { "tya", AM_NON, 0x00 }, - { "sta", AM_ABS_Y, 0x02 }, - { "txs", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "stz", AM_ABS, 0x02 }, - { "sta", AM_ABS_X, 0x02 }, - { "stz", AM_ABS_X, 0x02 }, - { "bbs1", AM_ZP_ABS, 0x02 }, - { "ldy", AM_IMM, 0x01 }, - { "lda", AM_ZP_REL_X, 0x01 }, - { "ldx", AM_IMM, 0x01 }, - { "???", AM_NON, 0x00 }, - { "ldy", AM_ZP, 0x01 }, - { "lda", AM_ZP, 0x01 }, - { "ldx", AM_ZP, 0x01 }, - { "???", AM_NON, 0x00 }, - { "tay", AM_NON, 0x00 }, - { "lda", AM_IMM, 0x01 }, - { "tax", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "ldy", AM_ABS, 0x02 }, - { "lda", AM_ABS, 0x02 }, - { "ldx", AM_ABS, 0x02 }, - { "bbs2", AM_ZP_ABS, 0x02 }, - { "bcs", AM_BRANCH, 0x01 }, - { "lda", AM_ZP_Y_REL, 0x01 }, - { "lda", AM_ZP_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "ldy", AM_ZP_X, 0x01 }, - { "lda", AM_ZP_X, 0x01 }, - { "ldx", AM_ZP_Y, 0x01 }, - { "???", AM_NON, 0x00 }, - { "clv", AM_NON, 0x00 }, - { "lda", AM_ABS_Y, 0x02 }, - { "tsx", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "ldy", AM_ABS_X, 0x02 }, - { "lda", AM_ABS_X, 0x02 }, - { "ldx", AM_ABS_Y, 0x02 }, - { "bbs3", AM_ZP_ABS, 0x02 }, - { "cpy", AM_IMM, 0x01 }, - { "cmp", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "cpy", AM_ZP, 0x01 }, - { "cmp", AM_ZP, 0x01 }, - { "dec", AM_ZP, 0x01 }, - { "???", AM_NON, 0x00 }, - { "iny", AM_NON, 0x00 }, - { "cmp", AM_IMM, 0x01 }, - { "dex", AM_NON, 0x00 }, - { "wai", AM_NON, 0x00 }, - { "cpy", AM_ABS, 0x02 }, - { "cmp", AM_ABS, 0x02 }, - { "dec", AM_ABS, 0x02 }, - { "bbs4", AM_ZP_ABS, 0x02 }, - { "bne", AM_BRANCH, 0x01 }, - { "cmp", AM_ZP_Y_REL, 0x01 }, - { "cmp", AM_ZP_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "cmp", AM_ZP_X, 0x01 }, - { "dec", AM_ZP_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "cld", AM_NON, 0x00 }, - { "cmp", AM_ABS_Y, 0x02 }, - { "phx", AM_NON, 0x00 }, - { "stp", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "cmp", AM_ABS_X, 0x02 }, - { "dec", AM_ABS_X, 0x02 }, - { "bbs5", AM_ZP_ABS, 0x02 }, - { "cpx", AM_IMM, 0x01 }, - { "sbc", AM_ZP_REL_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "cpx", AM_ZP, 0x01 }, - { "sbc", AM_ZP, 0x01 }, - { "inc", AM_ZP, 0x01 }, - { "???", AM_NON, 0x00 }, - { "inx", AM_NON, 0x00 }, - { "sbc", AM_IMM, 0x01 }, - { "nop", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "cpx", AM_ABS, 0x02 }, - { "sbc", AM_ABS, 0x02 }, - { "inc", AM_ABS, 0x02 }, - { "bbs6", AM_ZP_ABS, 0x02 }, - { "beq", AM_BRANCH, 0x01 }, - { "sbc", AM_ZP_Y_REL, 0x01 }, - { "sbc", AM_ZP_REL, 0x01 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "sbc", AM_ZP_X, 0x01 }, - { "inc", AM_ZP_X, 0x01 }, - { "???", AM_NON, 0x00 }, - { "sed", AM_NON, 0x00 }, - { "sbc", AM_ABS_Y, 0x02 }, - { "plx", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "???", AM_NON, 0x00 }, - { "sbc", AM_ABS_X, 0x02 }, - { "inc", AM_ABS_X, 0x02 }, - { "bbs7", AM_ZP_ABS, 0x02 }, + { mnm_brk, AM_NON, 0}, + { mnm_ora, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_tsb, AM_ZP, 1 }, + { mnm_ora, AM_ZP, 1 }, + { mnm_asl, AM_ZP, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_php, AM_NON, 0 }, + { mnm_ora, AM_IMM, 1 }, + { mnm_asl, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_tsb, AM_ABS, 2 }, + { mnm_ora, AM_ABS, 2 }, + { mnm_asl, AM_ABS, 2 }, + { mnm_bbr0, AM_ZP_ABS, 2 }, + { mnm_bpl, AM_BRANCH, 1 }, + { mnm_ora, AM_ZP_Y_REL, 1 }, + { mnm_ora, AM_ZP_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_trb, AM_ZP, 1 }, + { mnm_ora, AM_ZP_X, 1 }, + { mnm_asl, AM_ZP_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_clc, AM_NON, 0 }, + { mnm_ora, AM_ABS_Y, 2 }, + { mnm_inc, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_trb, AM_ABS, 2 }, + { mnm_ora, AM_ABS_X, 2 }, + { mnm_asl, AM_ABS_X, 2 }, + { mnm_bbr1, AM_ZP_ABS, 2 }, + { mnm_jsr, AM_ABS, 2 }, + { mnm_and, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_bit, AM_ZP, 1 }, + { mnm_and, AM_ZP, 1 }, + { mnm_rol, AM_ZP, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_plp, AM_NON, 0 }, + { mnm_and, AM_IMM, 1 }, + { mnm_rol, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_bit, AM_ABS, 2 }, + { mnm_and, AM_ABS, 2 }, + { mnm_rol, AM_ABS, 2 }, + { mnm_bbr2, AM_ZP_ABS, 2 }, + { mnm_bmi, AM_BRANCH, 1 }, + { mnm_and, AM_ZP_Y_REL, 1 }, + { mnm_and, AM_ZP_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_bit, AM_ZP_X, 1 }, + { mnm_and, AM_ZP_X, 1 }, + { mnm_rol, AM_ZP_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sec, AM_NON, 0 }, + { mnm_and, AM_ABS_Y, 2 }, + { mnm_dec, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_bit, AM_ABS_X, 2 }, + { mnm_and, AM_ABS_X, 2 }, + { mnm_rol, AM_ABS_X, 2 }, + { mnm_bbr3, AM_ZP_ABS, 2 }, + { mnm_rti, AM_NON, 0 }, + { mnm_eor, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_eor, AM_ZP, 1 }, + { mnm_lsr, AM_ZP, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_pha, AM_NON, 0 }, + { mnm_eor, AM_IMM, 1 }, + { mnm_lsr, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_jmp, AM_ABS, 2 }, + { mnm_eor, AM_ABS, 2 }, + { mnm_lsr, AM_ABS, 2 }, + { mnm_bbr4, AM_ZP_ABS, 2 }, + { mnm_bvc, AM_BRANCH, 1 }, + { mnm_eor, AM_ZP_Y_REL, 1 }, + { mnm_eor, AM_ZP_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_eor, AM_ZP_X, 1 }, + { mnm_lsr, AM_ZP_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_cli, AM_NON, 0 }, + { mnm_eor, AM_ABS_Y, 2 }, + { mnm_phy, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_eor, AM_ABS_X, 2 }, + { mnm_lsr, AM_ABS_X, 2 }, + { mnm_bbr5, AM_ZP_ABS, 2 }, + { mnm_rts, AM_NON, 0 }, + { mnm_adc, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_stz, AM_ZP, 1 }, + { mnm_adc, AM_ZP, 1 }, + { mnm_ror, AM_ZP, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_pla, AM_NON, 0 }, + { mnm_adc, AM_IMM, 1 }, + { mnm_ror, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_jmp, AM_REL, 2 }, + { mnm_adc, AM_ABS, 2 }, + { mnm_ror, AM_ABS, 2 }, + { mnm_bbr6, AM_ZP_ABS, 2 }, + { mnm_bvs, AM_BRANCH, 1 }, + { mnm_adc, AM_ZP_Y_REL, 1 }, + { mnm_adc, AM_ZP_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_stz, AM_ZP_X, 1 }, + { mnm_adc, AM_ZP_X, 1 }, + { mnm_ror, AM_ZP_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sei, AM_NON, 0 }, + { mnm_adc, AM_ABS_Y, 2 }, + { mnm_ply, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_jmp, AM_REL_X, 2 }, + { mnm_adc, AM_ABS_X, 2 }, + { mnm_ror, AM_ABS_X, 2 }, + { mnm_bbr7, AM_ZP_ABS, 2 }, + { mnm_bra, AM_BRANCH, 1 }, + { mnm_sta, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sty, AM_ZP, 1 }, + { mnm_sta, AM_ZP, 1 }, + { mnm_stx, AM_ZP, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_dey, AM_NON, 0 }, + { mnm_bit, AM_IMM, 1 }, + { mnm_txa, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sty, AM_ABS, 2 }, + { mnm_sta, AM_ABS, 2 }, + { mnm_stx, AM_ABS, 2 }, + { mnm_bbs0, AM_ZP_ABS, 2 }, + { mnm_bcc, AM_BRANCH, 1 }, + { mnm_sta, AM_ZP_Y_REL, 1 }, + { mnm_sta, AM_ZP_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sty, AM_ZP_X, 1 }, + { mnm_sta, AM_ZP_X, 1 }, + { mnm_stx, AM_ZP_Y, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_tya, AM_NON, 0 }, + { mnm_sta, AM_ABS_Y, 2 }, + { mnm_txs, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_stz, AM_ABS, 2 }, + { mnm_sta, AM_ABS_X, 2 }, + { mnm_stz, AM_ABS_X, 2 }, + { mnm_bbs1, AM_ZP_ABS, 2 }, + { mnm_ldy, AM_IMM, 1 }, + { mnm_lda, AM_ZP_REL_X, 1 }, + { mnm_ldx, AM_IMM, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ldy, AM_ZP, 1 }, + { mnm_lda, AM_ZP, 1 }, + { mnm_ldx, AM_ZP, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_tay, AM_NON, 0 }, + { mnm_lda, AM_IMM, 1 }, + { mnm_tax, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ldy, AM_ABS, 2 }, + { mnm_lda, AM_ABS, 2 }, + { mnm_ldx, AM_ABS, 2 }, + { mnm_bbs2, AM_ZP_ABS, 2 }, + { mnm_bcs, AM_BRANCH, 1 }, + { mnm_lda, AM_ZP_Y_REL, 1 }, + { mnm_lda, AM_ZP_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ldy, AM_ZP_X, 1 }, + { mnm_lda, AM_ZP_X, 1 }, + { mnm_ldx, AM_ZP_Y, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_clv, AM_NON, 0 }, + { mnm_lda, AM_ABS_Y, 2 }, + { mnm_tsx, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_ldy, AM_ABS_X, 2 }, + { mnm_lda, AM_ABS_X, 2 }, + { mnm_ldx, AM_ABS_Y, 2 }, + { mnm_bbs3, AM_ZP_ABS, 2 }, + { mnm_cpy, AM_IMM, 1 }, + { mnm_cmp, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_cpy, AM_ZP, 1 }, + { mnm_cmp, AM_ZP, 1 }, + { mnm_dec, AM_ZP, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_iny, AM_NON, 0 }, + { mnm_cmp, AM_IMM, 1 }, + { mnm_dex, AM_NON, 0 }, + { mnm_wai, AM_NON, 0 }, + { mnm_cpy, AM_ABS, 2 }, + { mnm_cmp, AM_ABS, 2 }, + { mnm_dec, AM_ABS, 2 }, + { mnm_bbs4, AM_ZP_ABS, 2 }, + { mnm_bne, AM_BRANCH, 1 }, + { mnm_cmp, AM_ZP_Y_REL, 1 }, + { mnm_cmp, AM_ZP_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_cmp, AM_ZP_X, 1 }, + { mnm_dec, AM_ZP_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_cld, AM_NON, 0 }, + { mnm_cmp, AM_ABS_Y, 2 }, + { mnm_phx, AM_NON, 0 }, + { mnm_stp, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_cmp, AM_ABS_X, 2 }, + { mnm_dec, AM_ABS_X, 2 }, + { mnm_bbs5, AM_ZP_ABS, 2 }, + { mnm_cpx, AM_IMM, 1 }, + { mnm_sbc, AM_ZP_REL_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_cpx, AM_ZP, 1 }, + { mnm_sbc, AM_ZP, 1 }, + { mnm_inc, AM_ZP, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inx, AM_NON, 0 }, + { mnm_sbc, AM_IMM, 1 }, + { mnm_nop, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_cpx, AM_ABS, 2 }, + { mnm_sbc, AM_ABS, 2 }, + { mnm_inc, AM_ABS, 2 }, + { mnm_bbs6, AM_ZP_ABS, 2 }, + { mnm_beq, AM_BRANCH, 1 }, + { mnm_sbc, AM_ZP_Y_REL, 1 }, + { mnm_sbc, AM_ZP_REL, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sbc, AM_ZP_X, 1 }, + { mnm_inc, AM_ZP_X, 1 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sed, AM_NON, 0 }, + { mnm_sbc, AM_ABS_Y, 2 }, + { mnm_plx, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_inv, AM_NON, 0 }, + { mnm_sbc, AM_ABS_X, 2 }, + { mnm_inc, AM_ABS_X, 2 }, + { mnm_bbs7, AM_ZP_ABS, 2 }, }; struct dismnm a65816_ops[256] = { - { "brk", AM_NON, 0x00 }, - { "ora", AM_ZP_REL_X, 0x01 }, - { "cop", AM_NON, 0x00 }, - { "ora", AM_STK, 0x01 }, - { "tsb", AM_ZP, 0x01 }, - { "ora", AM_ZP, 0x01 }, - { "asl", AM_ZP, 0x01 }, - { "ora", AM_ZP_REL_L, 0x01 }, - { "php", AM_NON, 0x00 }, - { "ora", AM_IMM_DBL_A, 0x01 }, - { "asl", AM_NON, 0x00 }, - { "phd", AM_NON, 0x00 }, - { "tsb", AM_ABS, 0x02 }, - { "ora", AM_ABS, 0x02 }, - { "asl", AM_ABS, 0x02 }, - { "ora", AM_ABS_L, 0x03 }, - { "bpl", AM_BRANCH, 0x01 }, - { "ora", AM_ZP_Y_REL, 0x01 }, - { "ora", AM_ZP_REL, 0x01 }, - { "ora", AM_STK_REL_Y, 0x01 }, - { "trb", AM_ZP, 0x01 }, - { "ora", AM_ZP_X, 0x01 }, - { "asl", AM_ZP_X, 0x01 }, - { "ora", AM_ZP_REL_Y_L, 0x01 }, - { "clc", AM_NON, 0x00 }, - { "ora", AM_ABS_Y, 0x02 }, - { "inc", AM_NON, 0x00 }, - { "tcs", AM_NON, 0x00 }, - { "trb", AM_ABS, 0x02 }, - { "ora", AM_ABS_X, 0x02 }, - { "asl", AM_ABS_X, 0x02 }, - { "ora", AM_ABS_L_X, 0x03 }, - { "jsr", AM_ABS, 0x02 }, - { "and", AM_ZP_REL_X, 0x01 }, - { "jsr", AM_ABS_L, 0x03 }, - { "and", AM_STK, 0x01 }, - { "bit", AM_ZP, 0x01 }, - { "and", AM_ZP, 0x01 }, - { "rol", AM_ZP, 0x01 }, - { "and", AM_ZP_REL_L, 0x01 }, - { "plp", AM_NON, 0x00 }, - { "and", AM_IMM_DBL_A, 0x01 }, - { "rol", AM_NON, 0x00 }, - { "pld", AM_NON, 0x00 }, - { "bit", AM_ABS, 0x02 }, - { "and", AM_ABS, 0x02 }, - { "rol", AM_ABS, 0x02 }, - { "and", AM_ABS_L, 0x03 }, - { "bmi", AM_BRANCH, 0x01 }, - { "and", AM_ZP_Y_REL, 0x01 }, - { "and", AM_ZP_REL, 0x01 }, - { "and", AM_STK_REL_Y, 0x01 }, - { "bit", AM_ZP_X, 0x01 }, - { "and", AM_ZP_X, 0x01 }, - { "rol", AM_ZP_X, 0x01 }, - { "and", AM_ZP_REL_Y_L, 0x01 }, - { "sec", AM_NON, 0x00 }, - { "and", AM_ABS_Y, 0x02 }, - { "dec", AM_NON, 0x00 }, - { "tsc", AM_NON, 0x00 }, - { "bit", AM_ABS_X, 0x02 }, - { "and", AM_ABS_X, 0x02 }, - { "rol", AM_ABS_X, 0x02 }, - { "and", AM_ABS_L_X, 0x03 }, - { "rti", AM_NON, 0x00 }, - { "eor", AM_ZP_REL_X, 0x01 }, - { "wdm", AM_NON, 0x00 }, - { "eor", AM_STK, 0x01 }, - { "mvp", AM_BLK_MOV, 0x02 }, - { "eor", AM_ZP, 0x01 }, - { "lsr", AM_ZP, 0x01 }, - { "eor", AM_ZP_REL_L, 0x01 }, - { "pha", AM_NON, 0x00 }, - { "eor", AM_IMM_DBL_A, 0x01 }, - { "lsr", AM_NON, 0x00 }, - { "phk", AM_NON, 0x00 }, - { "jmp", AM_ABS, 0x02 }, - { "eor", AM_ABS, 0x02 }, - { "lsr", AM_ABS, 0x02 }, - { "eor", AM_ABS_L, 0x03 }, - { "bvc", AM_BRANCH, 0x01 }, - { "eor", AM_ZP_Y_REL, 0x01 }, - { "eor", AM_ZP_REL, 0x01 }, - { "eor", AM_STK_REL_Y, 0x01 }, - { "mvn", AM_BLK_MOV, 0x02 }, - { "eor", AM_ZP_X, 0x01 }, - { "lsr", AM_ZP_X, 0x01 }, - { "eor", AM_ZP_REL_Y_L, 0x01 }, - { "cli", AM_NON, 0x00 }, - { "eor", AM_ABS_Y, 0x02 }, - { "phy", AM_NON, 0x00 }, - { "tcd", AM_NON, 0x00 }, - { "jmp", AM_ABS_L, 0x03 }, - { "eor", AM_ABS_X, 0x02 }, - { "lsr", AM_ABS_X, 0x02 }, - { "eor", AM_ABS_L_X, 0x03 }, - { "rts", AM_NON, 0x00 }, - { "adc", AM_ZP_REL_X, 0x01 }, - { "per", AM_BRANCH_L, 0x02 }, - { "adc", AM_STK, 0x01 }, - { "stz", AM_ZP, 0x01 }, - { "adc", AM_ZP, 0x01 }, - { "ror", AM_ZP, 0x01 }, - { "adc", AM_ZP_REL_L, 0x01 }, - { "rtl", AM_NON, 0x00 }, - { "adc", AM_IMM_DBL_A, 0x01 }, - { "ror", AM_NON, 0x00 }, - { "rtl", AM_NON, 0x00 }, - { "jmp", AM_REL, 0x02 }, - { "adc", AM_ABS, 0x02 }, - { "ror", AM_ABS, 0x02 }, - { "adc", AM_ABS_L, 0x03 }, - { "bvs", AM_BRANCH, 0x01 }, - { "adc", AM_ZP_Y_REL, 0x01 }, - { "adc", AM_ZP_REL, 0x01 }, - { "adc", AM_STK_REL_Y, 0x01 }, - { "stz", AM_ZP_X, 0x01 }, - { "adc", AM_ZP_X, 0x01 }, - { "ror", AM_ZP_X, 0x01 }, - { "adc", AM_ZP_REL_Y_L, 0x01 }, - { "sei", AM_NON, 0x00 }, - { "adc", AM_ABS_Y, 0x02 }, - { "ply", AM_NON, 0x00 }, - { "tdc", AM_NON, 0x00 }, - { "jmp", AM_REL_X, 0x02 }, - { "adc", AM_ABS_X, 0x02 }, - { "ror", AM_ABS_X, 0x02 }, - { "adc", AM_ABS_L_X, 0x03 }, - { "bra", AM_BRANCH, 0x01 }, - { "sta", AM_ZP_REL_X, 0x01 }, - { "brl", AM_BRANCH_L, 0x02 }, - { "sta", AM_STK, 0x01 }, - { "sty", AM_ZP, 0x01 }, - { "sta", AM_ZP, 0x01 }, - { "stx", AM_ZP, 0x01 }, - { "sta", AM_ZP_REL_L, 0x01 }, - { "dey", AM_NON, 0x00 }, - { "bit", AM_IMM_DBL_A, 0x01 }, - { "txa", AM_NON, 0x00 }, - { "phb", AM_NON, 0x00 }, - { "sty", AM_ABS, 0x02 }, - { "sta", AM_ABS, 0x02 }, - { "stx", AM_ABS, 0x02 }, - { "sta", AM_ABS_L, 0x03 }, - { "bcc", AM_BRANCH, 0x01 }, - { "sta", AM_ZP_Y_REL, 0x01 }, - { "sta", AM_ZP_REL, 0x01 }, - { "sta", AM_STK_REL_Y, 0x01 }, - { "sty", AM_ZP_X, 0x01 }, - { "sta", AM_ZP_X, 0x01 }, - { "stx", AM_ZP_Y, 0x01 }, - { "sta", AM_ZP_REL_Y_L, 0x01 }, - { "tya", AM_NON, 0x00 }, - { "sta", AM_ABS_Y, 0x02 }, - { "txs", AM_NON, 0x00 }, - { "txy", AM_NON, 0x00 }, - { "stz", AM_ABS, 0x02 }, - { "sta", AM_ABS_X, 0x02 }, - { "stz", AM_ABS_X, 0x02 }, - { "sta", AM_ABS_L_X, 0x03 }, - { "ldy", AM_IMM_DBL_I, 0x01 }, - { "lda", AM_ZP_REL_X, 0x01 }, - { "ldx", AM_IMM_DBL_I, 0x01 }, - { "lda", AM_STK, 0x01 }, - { "ldy", AM_ZP, 0x01 }, - { "lda", AM_ZP, 0x01 }, - { "ldx", AM_ZP, 0x01 }, - { "lda", AM_ZP_REL_L, 0x01 }, - { "tay", AM_NON, 0x00 }, - { "lda", AM_IMM_DBL_A, 0x01 }, - { "tax", AM_NON, 0x00 }, - { "plb", AM_NON, 0x00 }, - { "ldy", AM_ABS, 0x02 }, - { "lda", AM_ABS, 0x02 }, - { "ldx", AM_ABS, 0x02 }, - { "lda", AM_ABS_L, 0x03 }, - { "bcs", AM_BRANCH, 0x01 }, - { "lda", AM_ZP_Y_REL, 0x01 }, - { "lda", AM_ZP_REL, 0x01 }, - { "lda", AM_STK_REL_Y, 0x01 }, - { "ldy", AM_ZP_X, 0x01 }, - { "lda", AM_ZP_X, 0x01 }, - { "ldx", AM_ZP_Y, 0x01 }, - { "lda", AM_ZP_REL_Y_L, 0x01 }, - { "clv", AM_NON, 0x00 }, - { "lda", AM_ABS_Y, 0x02 }, - { "tsx", AM_NON, 0x00 }, - { "tyx", AM_NON, 0x00 }, - { "ldy", AM_ABS_X, 0x02 }, - { "lda", AM_ABS_X, 0x02 }, - { "ldx", AM_ABS_Y, 0x02 }, - { "lda", AM_ABS_L_X, 0x03 }, - { "cpy", AM_IMM_DBL_I, 0x01 }, - { "cmp", AM_ZP_REL_X, 0x01 }, - { "rep", AM_IMM, 0x01 }, - { "cmp", AM_STK, 0x01 }, - { "cpy", AM_ZP, 0x01 }, - { "cmp", AM_ZP, 0x01 }, - { "dec", AM_ZP, 0x01 }, - { "cmp", AM_ZP_REL_L, 0x01 }, - { "iny", AM_NON, 0x00 }, - { "cmp", AM_IMM_DBL_A, 0x01 }, - { "dex", AM_NON, 0x00 }, - { "wai", AM_NON, 0x00 }, - { "cpy", AM_ABS, 0x02 }, - { "cmp", AM_ABS, 0x02 }, - { "dec", AM_ABS, 0x02 }, - { "cmp", AM_ABS_L, 0x03 }, - { "bne", AM_BRANCH, 0x01 }, - { "cmp", AM_ZP_Y_REL, 0x01 }, - { "cmp", AM_ZP_REL, 0x01 }, - { "cmp", AM_STK_REL_Y, 0x01 }, - { "pei", AM_ZP_REL, 0x01 }, - { "cmp", AM_ZP_X, 0x01 }, - { "dec", AM_ZP_X, 0x01 }, - { "cmp", AM_ZP_REL_Y_L, 0x01 }, - { "cld", AM_NON, 0x00 }, - { "cmp", AM_ABS_Y, 0x02 }, - { "phx", AM_NON, 0x00 }, - { "stp", AM_NON, 0x00 }, - { "jmp", AM_REL_L, 0x02 }, - { "cmp", AM_ABS_X, 0x02 }, - { "dec", AM_ABS_X, 0x02 }, - { "cmp", AM_ABS_L_X, 0x03 }, - { "cpx", AM_IMM_DBL_I, 0x01 }, - { "sbc", AM_ZP_REL_X, 0x01 }, - { "sep", AM_IMM, 0x01 }, - { "sbc", AM_STK, 0x01 }, - { "cpx", AM_ZP, 0x01 }, - { "sbc", AM_ZP, 0x01 }, - { "inc", AM_ZP, 0x01 }, - { "sbc", AM_ZP_REL_L, 0x01 }, - { "inx", AM_NON, 0x00 }, - { "sbc", AM_IMM_DBL_A, 0x01 }, - { "nop", AM_NON, 0x00 }, - { "xba", AM_NON, 0x00 }, - { "cpx", AM_ABS, 0x02 }, - { "sbc", AM_ABS, 0x02 }, - { "inc", AM_ABS, 0x02 }, - { "sbc", AM_ABS_L, 0x03 }, - { "beq", AM_BRANCH, 0x01 }, - { "sbc", AM_ZP_Y_REL, 0x01 }, - { "sbc", AM_ZP_REL, 0x01 }, - { "sbc", AM_STK_REL_Y, 0x01 }, - { "pea", AM_ABS, 0x02 }, - { "sbc", AM_ZP_X, 0x01 }, - { "inc", AM_ZP_X, 0x01 }, - { "sbc", AM_ZP_REL_Y_L, 0x01 }, - { "sed", AM_NON, 0x00 }, - { "sbc", AM_ABS_Y, 0x02 }, - { "plx", AM_NON, 0x00 }, - { "xce", AM_NON, 0x00 }, - { "jsr", AM_REL_X, 0x02 }, - { "sbc", AM_ABS_X, 0x02 }, - { "inc", AM_ABS_X, 0x02 }, - { "sbc", AM_ABS_L_X, 0x03 }, + { mnm_brk, AM_NON, 0}, + { mnm_ora, AM_ZP_REL_X, 1 }, + { mnm_cop, AM_NON, 0 }, + { mnm_ora, AM_STK, 1 }, + { mnm_tsb, AM_ZP, 1 }, + { mnm_ora, AM_ZP, 1 }, + { mnm_asl, AM_ZP, 1 }, + { mnm_ora, AM_ZP_REL_L, 1 }, + { mnm_php, AM_NON, 0 }, + { mnm_ora, AM_IMM_DBL_A, 1 }, + { mnm_asl, AM_NON, 0 }, + { mnm_phd, AM_NON, 0 }, + { mnm_tsb, AM_ABS, 2 }, + { mnm_ora, AM_ABS, 2 }, + { mnm_asl, AM_ABS, 2 }, + { mnm_ora, AM_ABS_L, 3 }, + { mnm_bpl, AM_BRANCH, 1 }, + { mnm_ora, AM_ZP_Y_REL, 1 }, + { mnm_ora, AM_ZP_REL, 1 }, + { mnm_ora, AM_STK_REL_Y, 1 }, + { mnm_trb, AM_ZP, 1 }, + { mnm_ora, AM_ZP_X, 1 }, + { mnm_asl, AM_ZP_X, 1 }, + { mnm_ora, AM_ZP_REL_Y_L, 1 }, + { mnm_clc, AM_NON, 0 }, + { mnm_ora, AM_ABS_Y, 2 }, + { mnm_inc, AM_NON, 0 }, + { mnm_tcs, AM_NON, 0 }, + { mnm_trb, AM_ABS, 2 }, + { mnm_ora, AM_ABS_X, 2 }, + { mnm_asl, AM_ABS_X, 2 }, + { mnm_ora, AM_ABS_L_X, 3 }, + { mnm_jsr, AM_ABS, 2 }, + { mnm_and, AM_ZP_REL_X, 1 }, + { mnm_jsr, AM_ABS_L, 3 }, + { mnm_and, AM_STK, 1 }, + { mnm_bit, AM_ZP, 1 }, + { mnm_and, AM_ZP, 1 }, + { mnm_rol, AM_ZP, 1 }, + { mnm_and, AM_ZP_REL_L, 1 }, + { mnm_plp, AM_NON, 0 }, + { mnm_and, AM_IMM_DBL_A, 1 }, + { mnm_rol, AM_NON, 0 }, + { mnm_pld, AM_NON, 0 }, + { mnm_bit, AM_ABS, 2 }, + { mnm_and, AM_ABS, 2 }, + { mnm_rol, AM_ABS, 2 }, + { mnm_and, AM_ABS_L, 3 }, + { mnm_bmi, AM_BRANCH, 1 }, + { mnm_and, AM_ZP_Y_REL, 1 }, + { mnm_and, AM_ZP_REL, 1 }, + { mnm_and, AM_STK_REL_Y, 1 }, + { mnm_bit, AM_ZP_X, 1 }, + { mnm_and, AM_ZP_X, 1 }, + { mnm_rol, AM_ZP_X, 1 }, + { mnm_and, AM_ZP_REL_Y_L, 1 }, + { mnm_sec, AM_NON, 0 }, + { mnm_and, AM_ABS_Y, 2 }, + { mnm_dec, AM_NON, 0 }, + { mnm_tsc, AM_NON, 0 }, + { mnm_bit, AM_ABS_X, 2 }, + { mnm_and, AM_ABS_X, 2 }, + { mnm_rol, AM_ABS_X, 2 }, + { mnm_and, AM_ABS_L_X, 3 }, + { mnm_rti, AM_NON, 0 }, + { mnm_eor, AM_ZP_REL_X, 1 }, + { mnm_wdm, AM_NON, 0 }, + { mnm_eor, AM_STK, 1 }, + { mnm_mvp, AM_BLK_MOV, 2 }, + { mnm_eor, AM_ZP, 1 }, + { mnm_lsr, AM_ZP, 1 }, + { mnm_eor, AM_ZP_REL_L, 1 }, + { mnm_pha, AM_NON, 0 }, + { mnm_eor, AM_IMM_DBL_A, 1 }, + { mnm_lsr, AM_NON, 0 }, + { mnm_phk, AM_NON, 0 }, + { mnm_jmp, AM_ABS, 2 }, + { mnm_eor, AM_ABS, 2 }, + { mnm_lsr, AM_ABS, 2 }, + { mnm_eor, AM_ABS_L, 3 }, + { mnm_bvc, AM_BRANCH, 1 }, + { mnm_eor, AM_ZP_Y_REL, 1 }, + { mnm_eor, AM_ZP_REL, 1 }, + { mnm_eor, AM_STK_REL_Y, 1 }, + { mnm_mvn, AM_BLK_MOV, 2 }, + { mnm_eor, AM_ZP_X, 1 }, + { mnm_lsr, AM_ZP_X, 1 }, + { mnm_eor, AM_ZP_REL_Y_L, 1 }, + { mnm_cli, AM_NON, 0 }, + { mnm_eor, AM_ABS_Y, 2 }, + { mnm_phy, AM_NON, 0 }, + { mnm_tcd, AM_NON, 0 }, + { mnm_jmp, AM_ABS_L, 3 }, + { mnm_eor, AM_ABS_X, 2 }, + { mnm_lsr, AM_ABS_X, 2 }, + { mnm_eor, AM_ABS_L_X, 3 }, + { mnm_rts, AM_NON, 0 }, + { mnm_adc, AM_ZP_REL_X, 1 }, + { mnm_per, AM_BRANCH_L, 2 }, + { mnm_adc, AM_STK, 1 }, + { mnm_stz, AM_ZP, 1 }, + { mnm_adc, AM_ZP, 1 }, + { mnm_ror, AM_ZP, 1 }, + { mnm_adc, AM_ZP_REL_L, 1 }, + { mnm_pla, AM_NON, 0 }, + { mnm_adc, AM_IMM_DBL_A, 1 }, + { mnm_ror, AM_NON, 0 }, + { mnm_rtl, AM_NON, 0 }, + { mnm_jmp, AM_REL, 2 }, + { mnm_adc, AM_ABS, 2 }, + { mnm_ror, AM_ABS, 2 }, + { mnm_adc, AM_ABS_L, 3 }, + { mnm_bvs, AM_BRANCH, 1 }, + { mnm_adc, AM_ZP_Y_REL, 1 }, + { mnm_adc, AM_ZP_REL, 1 }, + { mnm_adc, AM_STK_REL_Y, 1 }, + { mnm_stz, AM_ZP_X, 1 }, + { mnm_adc, AM_ZP_X, 1 }, + { mnm_ror, AM_ZP_X, 1 }, + { mnm_adc, AM_ZP_REL_Y_L, 1 }, + { mnm_sei, AM_NON, 0 }, + { mnm_adc, AM_ABS_Y, 2 }, + { mnm_ply, AM_NON, 0 }, + { mnm_tdc, AM_NON, 0 }, + { mnm_jmp, AM_REL_X, 2 }, + { mnm_adc, AM_ABS_X, 2 }, + { mnm_ror, AM_ABS_X, 2 }, + { mnm_adc, AM_ABS_L_X, 3 }, + { mnm_bra, AM_BRANCH, 1 }, + { mnm_sta, AM_ZP_REL_X, 1 }, + { mnm_brl, AM_BRANCH_L, 2 }, + { mnm_sta, AM_STK, 1 }, + { mnm_sty, AM_ZP, 1 }, + { mnm_sta, AM_ZP, 1 }, + { mnm_stx, AM_ZP, 1 }, + { mnm_sta, AM_ZP_REL_L, 1 }, + { mnm_dey, AM_NON, 0 }, + { mnm_bit, AM_IMM_DBL_A, 1 }, + { mnm_txa, AM_NON, 0 }, + { mnm_phb, AM_NON, 0 }, + { mnm_sty, AM_ABS, 2 }, + { mnm_sta, AM_ABS, 2 }, + { mnm_stx, AM_ABS, 2 }, + { mnm_sta, AM_ABS_L, 3 }, + { mnm_bcc, AM_BRANCH, 1 }, + { mnm_sta, AM_ZP_Y_REL, 1 }, + { mnm_sta, AM_ZP_REL, 1 }, + { mnm_sta, AM_STK_REL_Y, 1 }, + { mnm_sty, AM_ZP_X, 1 }, + { mnm_sta, AM_ZP_X, 1 }, + { mnm_stx, AM_ZP_Y, 1 }, + { mnm_sta, AM_ZP_REL_Y_L, 1 }, + { mnm_tya, AM_NON, 0 }, + { mnm_sta, AM_ABS_Y, 2 }, + { mnm_txs, AM_NON, 0 }, + { mnm_txy, AM_NON, 0 }, + { mnm_stz, AM_ABS, 2 }, + { mnm_sta, AM_ABS_X, 2 }, + { mnm_stz, AM_ABS_X, 2 }, + { mnm_sta, AM_ABS_L_X, 3 }, + { mnm_ldy, AM_IMM_DBL_I, 1 }, + { mnm_lda, AM_ZP_REL_X, 1 }, + { mnm_ldx, AM_IMM_DBL_I, 1 }, + { mnm_lda, AM_STK, 1 }, + { mnm_ldy, AM_ZP, 1 }, + { mnm_lda, AM_ZP, 1 }, + { mnm_ldx, AM_ZP, 1 }, + { mnm_lda, AM_ZP_REL_L, 1 }, + { mnm_tay, AM_NON, 0 }, + { mnm_lda, AM_IMM_DBL_A, 1 }, + { mnm_tax, AM_NON, 0 }, + { mnm_plb, AM_NON, 0 }, + { mnm_ldy, AM_ABS, 2 }, + { mnm_lda, AM_ABS, 2 }, + { mnm_ldx, AM_ABS, 2 }, + { mnm_lda, AM_ABS_L, 3 }, + { mnm_bcs, AM_BRANCH, 1 }, + { mnm_lda, AM_ZP_Y_REL, 1 }, + { mnm_lda, AM_ZP_REL, 1 }, + { mnm_lda, AM_STK_REL_Y, 1 }, + { mnm_ldy, AM_ZP_X, 1 }, + { mnm_lda, AM_ZP_X, 1 }, + { mnm_ldx, AM_ZP_Y, 1 }, + { mnm_lda, AM_ZP_REL_Y_L, 1 }, + { mnm_clv, AM_NON, 0 }, + { mnm_lda, AM_ABS_Y, 2 }, + { mnm_tsx, AM_NON, 0 }, + { mnm_tyx, AM_NON, 0 }, + { mnm_ldy, AM_ABS_X, 2 }, + { mnm_lda, AM_ABS_X, 2 }, + { mnm_ldx, AM_ABS_Y, 2 }, + { mnm_lda, AM_ABS_L_X, 3 }, + { mnm_cpy, AM_IMM_DBL_I, 1 }, + { mnm_cmp, AM_ZP_REL_X, 1 }, + { mnm_rep, AM_IMM, 1 }, + { mnm_cmp, AM_STK, 1 }, + { mnm_cpy, AM_ZP, 1 }, + { mnm_cmp, AM_ZP, 1 }, + { mnm_dec, AM_ZP, 1 }, + { mnm_cmp, AM_ZP_REL_L, 1 }, + { mnm_iny, AM_NON, 0 }, + { mnm_cmp, AM_IMM_DBL_A, 1 }, + { mnm_dex, AM_NON, 0 }, + { mnm_wai, AM_NON, 0 }, + { mnm_cpy, AM_ABS, 2 }, + { mnm_cmp, AM_ABS, 2 }, + { mnm_dec, AM_ABS, 2 }, + { mnm_cmp, AM_ABS_L, 3 }, + { mnm_bne, AM_BRANCH, 1 }, + { mnm_cmp, AM_ZP_Y_REL, 1 }, + { mnm_cmp, AM_ZP_REL, 1 }, + { mnm_cmp, AM_STK_REL_Y, 1 }, + { mnm_pei, AM_ZP_REL, 1 }, + { mnm_cmp, AM_ZP_X, 1 }, + { mnm_dec, AM_ZP_X, 1 }, + { mnm_cmp, AM_ZP_REL_Y_L, 1 }, + { mnm_cld, AM_NON, 0 }, + { mnm_cmp, AM_ABS_Y, 2 }, + { mnm_phx, AM_NON, 0 }, + { mnm_stp, AM_NON, 0 }, + { mnm_jmp, AM_REL_L, 2 }, + { mnm_cmp, AM_ABS_X, 2 }, + { mnm_dec, AM_ABS_X, 2 }, + { mnm_cmp, AM_ABS_L_X, 3 }, + { mnm_cpx, AM_IMM_DBL_I, 1 }, + { mnm_sbc, AM_ZP_REL_X, 1 }, + { mnm_sep, AM_IMM, 1 }, + { mnm_sbc, AM_STK, 1 }, + { mnm_cpx, AM_ZP, 1 }, + { mnm_sbc, AM_ZP, 1 }, + { mnm_inc, AM_ZP, 1 }, + { mnm_sbc, AM_ZP_REL_L, 1 }, + { mnm_inx, AM_NON, 0 }, + { mnm_sbc, AM_IMM_DBL_A, 1 }, + { mnm_nop, AM_NON, 0 }, + { mnm_xba, AM_NON, 0 }, + { mnm_cpx, AM_ABS, 2 }, + { mnm_sbc, AM_ABS, 2 }, + { mnm_inc, AM_ABS, 2 }, + { mnm_sbc, AM_ABS_L, 3 }, + { mnm_beq, AM_BRANCH, 1 }, + { mnm_sbc, AM_ZP_Y_REL, 1 }, + { mnm_sbc, AM_ZP_REL, 1 }, + { mnm_sbc, AM_STK_REL_Y, 1 }, + { mnm_pea, AM_ABS, 2 }, + { mnm_sbc, AM_ZP_X, 1 }, + { mnm_inc, AM_ZP_X, 1 }, + { mnm_sbc, AM_ZP_REL_Y_L, 1 }, + { mnm_sed, AM_NON, 0 }, + { mnm_sbc, AM_ABS_Y, 2 }, + { mnm_plx, AM_NON, 0 }, + { mnm_xce, AM_NON, 0 }, + { mnm_jsr, AM_REL_X, 2 }, + { mnm_sbc, AM_ABS_X, 2 }, + { mnm_inc, AM_ABS_X, 2 }, + { mnm_sbc, AM_ABS_L_X, 3 }, }; enum RefType { @@ -970,6 +1278,7 @@ struct RefAddr { int number:15; // label count strref label; // user defined label strref comment; + strref read_only_label; // for labels that have a different meaning between reading and writing std::vector *pRefs; // what is referencing this address RefAddr() : address(-1), data(0), size(0), local(0), separator(0), number(-1), pRefs(nullptr) {} @@ -985,6 +1294,7 @@ static int _sortRefs(const void *A, const void *B) static const strref kw_data("data"); static const strref kw_code("code"); +static const strref kw_read("read"); static const strref kw_pointers("pointers"); int GetLabelIndex(int addr) { @@ -1020,27 +1330,33 @@ void GetReferences(unsigned char *mem, size_t bytes, bool acc_16, bool ind_16, i ++lab_line; lab_line.skip_whitespace(); - refs.push_back(RefAddr(address)); - RefAddr &r = refs[refs.size()-1]; - r.pRefs = new std::vector(); - r.size = size; - if (kw_data.is_prefix_word(lab_line)) { - r.data = DT_DATA; - lab_line += kw_data.get_len(); - } else if (kw_code.is_prefix_word(lab_line)) { - r.data = DT_CODE; - lab_line += kw_code.get_len(); - } else if (kw_pointers.is_prefix_word(lab_line)) { - lab_line += kw_pointers.get_len(); - lab_line.skip_whitespace(); - if (kw_data.is_prefix_word(lab_line)) - r.data = DT_PTRS_DATA; - else - r.data = DT_PTRS; + if (kw_read.is_prefix_word(lab_line)) { + int label_index = GetLabelIndex(address); + if (label_index>=0) + refs[label_index].read_only_label = name; + } else { + refs.push_back(RefAddr(address)); + RefAddr &r = refs[refs.size()-1]; + r.pRefs = new std::vector(); + r.size = size; + if (kw_data.is_prefix_word(lab_line)) { + r.data = DT_DATA; + lab_line += kw_data.get_len(); + } else if (kw_code.is_prefix_word(lab_line)) { + r.data = DT_CODE; + lab_line += kw_code.get_len(); + } else if (kw_pointers.is_prefix_word(lab_line)) { + lab_line += kw_pointers.get_len(); + lab_line.skip_whitespace(); + if (kw_data.is_prefix_word(lab_line)) + r.data = DT_PTRS_DATA; + else + r.data = DT_PTRS; + } + lab_line.trim_whitespace(); + r.label = name; + r.comment = lab_line; } - lab_line.trim_whitespace(); - r.label = name; - r.comment = lab_line; } if (GetLabelIndex(start_addr)<0) { @@ -1105,10 +1421,8 @@ void GetReferences(unsigned char *mem, size_t bytes, bool acc_16, bool ind_16, i else break; } - } else if (curr_label && addr>(refs[curr_label-1].address + refs[curr_label-1].size)) { + } else if (curr_label && addr>(refs[curr_label-1].address + refs[curr_label-1].size)) curr_data = false; - curr_label++; - } } else curr_data = false; @@ -1536,6 +1850,29 @@ void GetReferences(unsigned char *mem, size_t bytes, bool acc_16, bool ind_16, i } } +// returns true if the instruction accessing memory can ONLY read that memory, not write back or jump to it +// used to distinguish read-only labels when there is a different definition between reading and writing to the +// same physical address +bool IsReadOnlyInstruction(MNM_Base op_base) +{ + switch (op_base) { + case mnm_ora: + case mnm_and: + case mnm_bit: + case mnm_eor: + case mnm_adc: + case mnm_sbc: + case mnm_lda: + case mnm_ldx: + case mnm_ldy: + case mnm_cmp: + case mnm_cpy: + case mnm_cpx: + return true; + } + return false; +} + static const char spacing[] = " "; void Disassemble(strref filename, unsigned char *mem, size_t bytes, bool acc_16, bool ind_16, int addr, const dismnm *opcodes, bool src, int init_data, strref labels) { @@ -1664,12 +2001,13 @@ void Disassemble(strref filename, unsigned char *mem, size_t bytes, bool acc_16, blk -= 2; } } + int addr_line = addr; + out.copy(" dc.b "); for (int i = 0; i=16) { + out.sprintf_append(" ; $%04x-$%04x\n", addr_line, addr); + addr_line = addr; + fputs(out.c_str(), f); out.copy(" dc.b "); } out.sprintf_append("$%02x", *mem++); @@ -1678,8 +2016,8 @@ void Disassemble(strref filename, unsigned char *mem, size_t bytes, bool acc_16, addr++; bytes--; } - if (left&0xf) { - out.append("\n"); + if (addr!=addr_line) { + out.sprintf_append(" ; $%04x-$%04x\n", addr_line, addr); fputs(out.c_str(), f); } separator = false; @@ -1748,25 +2086,30 @@ void Disassemble(strref filename, unsigned char *mem, size_t bytes, bool acc_16, } } + bool read_only_instruction = false; + if (mode == AM_BRANCH) reference = addr + (char)*mem; else if (mode == AM_BRANCH_L) reference = addr + (short)(unsigned short)mem[0] + ((unsigned short)mem[1]<<8); - else if (mode == AM_ABS || mode == AM_ABS_Y || mode == AM_ABS_X || mode == AM_REL || mode == AM_REL_X || mode == AM_REL_L) + else if (mode == AM_ABS || mode == AM_ABS_Y || mode == AM_ABS_X || mode == AM_REL || mode == AM_REL_X || mode == AM_REL_L) { + read_only_instruction = IsReadOnlyInstruction(opcodes[op].mnemonic); reference = (int)mem[0] | ((int)mem[1])<<8; - else if (mode == AM_ZP || mode == AM_ZP_REL || mode == AM_ZP_REL_L || mode == AM_ZP_REL_X || mode == AM_ZP_Y_REL || - mode == AM_ZP_REL_Y || mode == AM_ZP_X || mode == AM_ZP_Y || mode == AM_ZP_REL_Y_L) + } else if (mode == AM_ZP || mode == AM_ZP_REL || mode == AM_ZP_REL_L || mode == AM_ZP_REL_X || mode == AM_ZP_Y_REL || + mode == AM_ZP_REL_Y || mode == AM_ZP_X || mode == AM_ZP_Y || mode == AM_ZP_REL_Y_L) { + read_only_instruction = IsReadOnlyInstruction(opcodes[op].mnemonic); reference = mem[0]; + } strown<64> lblname; strref lblcmt; for (size_t i = 0; i=start_addr &&reference<=end_addr && reference>=refs[i].address)) { + (reference>=start_addr && reference<=end_addr && reference>=refs[i].address)) { if (i==(refs.size()-1) || reference