Apple-1-HW/Apple1CartridgePcb
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flowenol 2021-03-01 01:05:14 +01:00
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116
44pin.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 44pin_edge
#
DEF 44pin_edge U 0 40 Y Y 1 F N
F0 "U" 0 -1250 50 H V C CNN
F1 "44pin_edge" 0 300 50 H V C CNN
F2 "" 950 1050 50 H I C CNN
F3 "" 950 1050 50 H I C CNN
DRAW
S -500 1050 500 -3350 0 1 0 N
X 1 1 600 1000 100 L 50 50 1 1 B
X 10 10 600 100 100 L 50 50 1 1 B
X 11 11 600 0 100 L 50 50 1 1 B
X 12 12 600 -100 100 L 50 50 1 1 B
X 13 13 600 -200 100 L 50 50 1 1 B
X 14 14 600 -300 100 L 50 50 1 1 B
X 15 15 600 -400 100 L 50 50 1 1 B
X 16 16 600 -500 100 L 50 50 1 1 B
X 17 17 600 -600 100 L 50 50 1 1 B
X 18 18 600 -700 100 L 50 50 1 1 B
X 19 19 600 -800 100 L 50 50 1 1 B
X 2 2 600 900 100 L 50 50 1 1 B
X 20 20 600 -900 100 L 50 50 1 1 B
X 21 21 600 -1000 100 L 50 50 1 1 B
X 22 22 600 -1100 100 L 50 50 1 1 B
X 3 3 600 800 100 L 50 50 1 1 B
X 4 4 600 700 100 L 50 50 1 1 B
X 5 5 600 600 100 L 50 50 1 1 B
X 6 6 600 500 100 L 50 50 1 1 B
X 7 7 600 400 100 L 50 50 1 1 B
X 8 8 600 300 100 L 50 50 1 1 B
X 9 9 600 200 100 L 50 50 1 1 B
X A A 600 -1200 100 L 50 50 1 1 B
X B B 600 -1300 100 L 50 50 1 1 B
X C C 600 -1400 100 L 50 50 1 1 B
X D D 600 -1500 100 L 50 50 1 1 B
X E E 600 -1600 100 L 50 50 1 1 B
X F F 600 -1700 100 L 50 50 1 1 B
X H H 600 -1800 100 L 50 50 1 1 B
X J J 600 -1900 100 L 50 50 1 1 B
X K K 600 -2000 100 L 50 50 1 1 B
X L L 600 -2100 100 L 50 50 1 1 B
X M M 600 -2200 100 L 50 50 1 1 B
X N N 600 -2300 100 L 50 50 1 1 B
X P P 600 -2400 100 L 50 50 1 1 B
X R R 600 -2500 100 L 50 50 1 1 B
X S S 600 -2600 100 L 50 50 1 1 B
X T T 600 -2700 100 L 50 50 1 1 B
X U U 600 -2800 100 L 50 50 1 1 B
X V V 600 -2900 100 L 50 50 1 1 B
X W W 600 -3000 100 L 50 50 1 1 B
X X X 600 -3100 100 L 50 50 1 1 B
X Y Y 600 -3200 100 L 50 50 1 1 B
X Z Z 600 -3300 100 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# 44pin_tht
#
DEF 44pin_tht U 0 40 Y Y 1 F N
F0 "U" 0 -1250 50 H V C CNN
F1 "44pin_tht" 0 300 50 H V C CNN
F2 "" 950 1050 50 H I C CNN
F3 "" 950 1050 50 H I C CNN
DRAW
S -500 1050 500 -1200 0 1 0 N
X 1 1 -600 1000 100 R 50 50 1 1 B
X 10 10 -600 100 100 R 50 50 1 1 B
X 11 11 -600 0 100 R 50 50 1 1 B
X 12 12 -600 -100 100 R 50 50 1 1 B
X 13 13 -600 -200 100 R 50 50 1 1 B
X 14 14 -600 -300 100 R 50 50 1 1 B
X 15 15 -600 -400 100 R 50 50 1 1 B
X 16 16 -600 -500 100 R 50 50 1 1 B
X 17 17 -600 -600 100 R 50 50 1 1 B
X 18 18 -600 -700 100 R 50 50 1 1 B
X 19 19 -600 -800 100 R 50 50 1 1 B
X 2 2 -600 900 100 R 50 50 1 1 B
X 20 20 -600 -900 100 R 50 50 1 1 B
X 21 21 -600 -1000 100 R 50 50 1 1 B
X 22 22 -600 -1100 100 R 50 50 1 1 B
X 3 3 -600 800 100 R 50 50 1 1 B
X 4 4 -600 700 100 R 50 50 1 1 B
X 5 5 -600 600 100 R 50 50 1 1 B
X 6 6 -600 500 100 R 50 50 1 1 B
X 7 7 -600 400 100 R 50 50 1 1 B
X 8 8 -600 300 100 R 50 50 1 1 B
X 9 9 -600 200 100 R 50 50 1 1 B
X A A 600 1000 100 L 50 50 1 1 B
X B B 600 900 100 L 50 50 1 1 B
X C C 600 800 100 L 50 50 1 1 B
X D D 600 700 100 L 50 50 1 1 B
X E E 600 600 100 L 50 50 1 1 B
X F F 600 500 100 L 50 50 1 1 B
X H H 600 400 100 L 50 50 1 1 B
X J J 600 300 100 L 50 50 1 1 B
X K K 600 200 100 L 50 50 1 1 B
X L L 600 100 100 L 50 50 1 1 B
X M M 600 0 100 L 50 50 1 1 B
X N N 600 -100 100 L 50 50 1 1 B
X P P 600 -200 100 L 50 50 1 1 B
X R R 600 -300 100 L 50 50 1 1 B
X S S 600 -400 100 L 50 50 1 1 B
X T T 600 -500 100 L 50 50 1 1 B
X U U 600 -600 100 L 50 50 1 1 B
X V V 600 -700 100 L 50 50 1 1 B
X W W 600 -800 100 L 50 50 1 1 B
X X X 600 -900 100 L 50 50 1 1 B
X Y Y 600 -1000 100 L 50 50 1 1 B
X Z Z 600 -1100 100 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
#End Library

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44pin.pretty/44pin1.kicad_mod Normal file
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(module 44pin1 (layer F.Cu) (tedit 5EE9F43B)
(fp_text reference REF** (at 0 -7.92) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 44pin1 (at 0 -5.38) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad Z connect roundrect (at 43.56 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad Y connect roundrect (at 39.6 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad X connect roundrect (at 35.64 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad W connect roundrect (at 31.68 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad V connect roundrect (at 27.72 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad U connect roundrect (at 23.76 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad T connect roundrect (at 19.8 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad S connect roundrect (at 15.84 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad R connect roundrect (at 11.88 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad P connect roundrect (at 7.92 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad N connect roundrect (at 3.96 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad M connect roundrect (at 0 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad L connect roundrect (at -3.96 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad K connect roundrect (at -7.92 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad J connect roundrect (at -11.88 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad H connect roundrect (at -15.84 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad F connect roundrect (at -19.8 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad E connect roundrect (at -23.76 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad D connect roundrect (at -27.72 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad C connect roundrect (at -31.68 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad B connect roundrect (at -35.64 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad A connect roundrect (at -39.6 0 90) (size 8.9916 2.794) (layers B.Cu B.Mask) (roundrect_rratio 0.25))
(pad 1 connect roundrect (at -39.6 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 2 connect roundrect (at -35.64 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 3 connect roundrect (at -31.68 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 4 connect roundrect (at -27.72 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 5 connect roundrect (at -23.76 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 6 connect roundrect (at -19.8 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 7 connect roundrect (at -15.84 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 8 connect roundrect (at -11.88 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 9 connect roundrect (at -7.92 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 10 connect roundrect (at -3.96 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 11 connect roundrect (at 0 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 12 connect roundrect (at 3.96 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 13 connect roundrect (at 7.92 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 14 connect roundrect (at 11.88 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 15 connect roundrect (at 15.84 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 16 connect roundrect (at 19.8 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 17 connect roundrect (at 23.76 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 18 connect roundrect (at 27.72 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 19 connect roundrect (at 31.68 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 20 connect roundrect (at 35.64 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 21 connect roundrect (at 39.6 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
(pad 22 connect roundrect (at 43.56 0 90) (size 8.9916 2.794) (layers F.Cu F.Mask) (roundrect_rratio 0.25))
)

54
44pin.pretty/44pin_socket.kicad_mod Normal file
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(module 44pin_socket (layer F.Cu) (tedit 5F07705C)
(fp_text reference REF** (at 0 3.96) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 44pin_socket (at 0 7.92) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at -31.68 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -27.72 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at -23.76 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at -19.8 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at -15.84 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 6 thru_hole circle (at -11.88 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 7 thru_hole circle (at -7.92 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 8 thru_hole circle (at -3.96 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 9 thru_hole circle (at 0 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 10 thru_hole circle (at 3.96 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 11 thru_hole circle (at 7.92 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 12 thru_hole circle (at 11.88 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 13 thru_hole circle (at 15.84 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 14 thru_hole circle (at 19.8 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 15 thru_hole circle (at 23.76 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 16 thru_hole circle (at 27.72 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 17 thru_hole circle (at 31.68 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 18 thru_hole circle (at 35.64 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 19 thru_hole circle (at 39.6 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 20 thru_hole circle (at 43.56 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 21 thru_hole circle (at 47.52 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad 22 thru_hole circle (at 51.48 0) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad A thru_hole circle (at -31.68 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad B thru_hole circle (at -27.72 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad C thru_hole circle (at -23.76 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad D thru_hole circle (at -19.8 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad E thru_hole circle (at -15.84 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad F thru_hole circle (at -11.88 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad H thru_hole circle (at -7.92 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad J thru_hole circle (at -3.96 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad K thru_hole circle (at 0 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad L thru_hole circle (at 3.96 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad M thru_hole circle (at 7.92 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad N thru_hole circle (at 11.88 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad P thru_hole circle (at 15.84 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad R thru_hole circle (at 19.8 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad S thru_hole circle (at 23.76 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad T thru_hole circle (at 27.72 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad U thru_hole circle (at 31.68 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad V thru_hole circle (at 35.64 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad W thru_hole circle (at 39.6 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad X thru_hole circle (at 43.56 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad Y thru_hole circle (at 47.52 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad Z thru_hole circle (at 51.48 -5.08) (size 2.54 2.54) (drill 1.65) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -41.2 -2.54) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 61 -2.54) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask))
)

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
<title>KiCad BOM Example 5</title>
</head>
<body>
<h1>/Users/piotrek/Projects/Apple1CartridgePcbV2/Apple1Cartridge.sch</h1>
<p>2020 December 21, Monday 18:46:05</p>
<p>Eeschema (5.1.5-0)</p>
<p><b>Component Count:</b>17</p>
<table>
<tr><th style='width:640px'>Ref</th><th>Qnty</th><th>Value</th><th>Part</th><th>Footprint</th><th>Description</th><th>Vendor</th></tr>
<tr><td>BANK1</td><td>1</td><td>74LS74</td><td>74xx:74LS74</td><td>Package_DIP:DIP-14_W7.62mm_Socket_LongPads</td><td>Dual D Flip-flop, Set & Reset</td><td></td></tr>
<tr><td>C1, C2, C3, C4</td><td>4</td><td>0.1uF</td><td>Device:C</td><td>Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P2.50mm</td><td>Unpolarized capacitor</td><td></td></tr>
<tr><td>C5</td><td>1</td><td>22uF</td><td>Device:CP1</td><td>Capacitor_THT:CP_Radial_D4.0mm_P2.00mm</td><td>Polarized capacitor, US symbol</td><td></td></tr>
<tr><td>CONNECTOR1</td><td>1</td><td>44pin_edge</td><td>44pin:44pin_edge</td><td>44pin:44pin1</td><td></td><td></td></tr>
<tr><td>DECODER1</td><td>1</td><td>GAL22V10</td><td>GAL22V10-15LP:GAL22V10-15LP</td><td>Package_DIP:DIP-24_W7.62mm_Socket_LongPads</td><td>Lattice Semiconductor GAL20V8B-15LP, SPLD GAL, GAL20V8B 8 Macro Cells, 8 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP</td><td></td></tr>
<tr><td>MODE_SWITCH1</td><td>1</td><td>SW_SPDT</td><td>Switch:SW_SPDT</td><td>Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical</td><td>Switch, single pole double throw</td><td></td></tr>
<tr><td>R1, R2, R3</td><td>3</td><td>1K</td><td>Device:R_US</td><td>Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal</td><td>Resistor, US symbol</td><td></td></tr>
<tr><td>RAM1</td><td>1</td><td>62256</td><td>AT28C64B-15PU:AT28C256</td><td>Package_DIP:DIP-28_W15.24mm_Socket_LongPads</td><td>AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP</td><td></td></tr>
<tr><td>RAM2</td><td>1</td><td>62256</td><td>AT28C64B-15PU:AT28C256</td><td>Package_DIP:DIP-28_W15.24mm_Socket</td><td>AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP</td><td></td></tr>
<tr><td>ROM1</td><td>1</td><td>28C256</td><td>AT28C64B-15PU:AT28C256</td><td>Package_DIP:DIP-28_W15.24mm_Socket_LongPads</td><td>AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP</td><td></td></tr>
<tr><td>ROM_PWR_REG1</td><td>1</td><td>L7805</td><td>Regulator_Linear:L7805</td><td>Package_TO_SOT_THT:TO-220-3_Horizontal_TabDown</td><td>Positive 1.5A 35V Linear Regulator, Fixed Output 5V, TO-220/TO-263/TO-252</td><td></td></tr>
<tr><td>ROM_PWR_SEL1</td><td>1</td><td>ROM_PWR_SEL</td><td>Connector:Conn_01x03_Male</td><td>Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical</td><td>Generic connector, single row, 01x03, script generated (kicad-library-utils/schlib/autogen/connector/)</td><td></td></tr><!--TABLEROW-->
</table>
</body>
</html>

290
Apple1Cartridge-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 44pin_44pin_edge
#
DEF 44pin_44pin_edge U 0 40 Y Y 1 F N
F0 "U" 0 -1250 50 H V C CNN
F1 "44pin_44pin_edge" 0 300 50 H V C CNN
F2 "" 950 1050 50 H I C CNN
F3 "" 950 1050 50 H I C CNN
DRAW
S -500 1050 500 -3350 0 1 0 N
X 1 1 600 1000 100 L 50 50 1 1 B
X 10 10 600 100 100 L 50 50 1 1 B
X 11 11 600 0 100 L 50 50 1 1 B
X 12 12 600 -100 100 L 50 50 1 1 B
X 13 13 600 -200 100 L 50 50 1 1 B
X 14 14 600 -300 100 L 50 50 1 1 B
X 15 15 600 -400 100 L 50 50 1 1 B
X 16 16 600 -500 100 L 50 50 1 1 B
X 17 17 600 -600 100 L 50 50 1 1 B
X 18 18 600 -700 100 L 50 50 1 1 B
X 19 19 600 -800 100 L 50 50 1 1 B
X 2 2 600 900 100 L 50 50 1 1 B
X 20 20 600 -900 100 L 50 50 1 1 B
X 21 21 600 -1000 100 L 50 50 1 1 B
X 22 22 600 -1100 100 L 50 50 1 1 B
X 3 3 600 800 100 L 50 50 1 1 B
X 4 4 600 700 100 L 50 50 1 1 B
X 5 5 600 600 100 L 50 50 1 1 B
X 6 6 600 500 100 L 50 50 1 1 B
X 7 7 600 400 100 L 50 50 1 1 B
X 8 8 600 300 100 L 50 50 1 1 B
X 9 9 600 200 100 L 50 50 1 1 B
X A A 600 -1200 100 L 50 50 1 1 B
X B B 600 -1300 100 L 50 50 1 1 B
X C C 600 -1400 100 L 50 50 1 1 B
X D D 600 -1500 100 L 50 50 1 1 B
X E E 600 -1600 100 L 50 50 1 1 B
X F F 600 -1700 100 L 50 50 1 1 B
X H H 600 -1800 100 L 50 50 1 1 B
X J J 600 -1900 100 L 50 50 1 1 B
X K K 600 -2000 100 L 50 50 1 1 B
X L L 600 -2100 100 L 50 50 1 1 B
X M M 600 -2200 100 L 50 50 1 1 B
X N N 600 -2300 100 L 50 50 1 1 B
X P P 600 -2400 100 L 50 50 1 1 B
X R R 600 -2500 100 L 50 50 1 1 B
X S S 600 -2600 100 L 50 50 1 1 B
X T T 600 -2700 100 L 50 50 1 1 B
X U U 600 -2800 100 L 50 50 1 1 B
X V V 600 -2900 100 L 50 50 1 1 B
X W W 600 -3000 100 L 50 50 1 1 B
X X X 600 -3100 100 L 50 50 1 1 B
X Y Y 600 -3200 100 L 50 50 1 1 B
X Z Z 600 -3300 100 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# 74xx_74LS74
#
DEF 74xx_74LS74 U 0 40 Y Y 3 L N
F0 "U" -300 350 50 H V C CNN
F1 "74xx_74LS74" -300 -350 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74HC74
$FPLIST
DIP*W7.62mm*
$ENDFPLIST
DRAW
S -200 200 200 -200 1 1 10 f
S -200 200 200 -200 2 1 10 f
S -200 300 200 -300 3 1 10 f
X ~R 1 0 -300 100 U 50 50 1 0 I
X D 2 -300 100 100 R 50 50 1 0 I
X C 3 -300 0 100 R 50 50 1 0 I C
X ~S 4 0 300 100 D 50 50 1 0 I
X Q 5 300 100 100 L 50 50 1 0 O
X ~Q 6 300 -100 100 L 50 50 1 0 O
X ~S 10 0 300 100 D 50 50 2 0 I
X C 11 -300 0 100 R 50 50 2 0 I C
X D 12 -300 100 100 R 50 50 2 0 I
X ~R 13 0 -300 100 U 50 50 2 0 I
X ~Q 8 300 -100 100 L 50 50 2 0 O
X Q 9 300 100 100 L 50 50 2 0 O
X VCC 14 0 400 100 D 50 50 3 0 W
X GND 7 0 -400 100 U 50 50 3 0 W
ENDDRAW
ENDDEF
#
# AT28C64B-15PU_AT28C256
#
DEF AT28C64B-15PU_AT28C256 IC 0 30 Y Y 1 F N
F0 "IC" 950 300 50 H V L CNN
F1 "AT28C64B-15PU_AT28C256" 950 200 50 H V L CNN
F2 "DIP1556W56P254L3702H483Q28N" 950 100 50 H I L CNN
F3 "http://www.atmel.com/images/doc0270.pdf" 950 0 50 H I L CNN
DRAW
P 5 0 1 6 200 100 900 100 900 -1400 200 -1400 200 100 N
X A14 1 0 0 200 R 50 50 0 0 I
X A0 10 0 -900 200 R 50 50 0 0 I
X I/O0 11 0 -1000 200 R 50 50 0 0 B
X I/O1 12 0 -1100 200 R 50 50 0 0 B
X I/O2 13 0 -1200 200 R 50 50 0 0 B
X GND 14 0 -1300 200 R 50 50 0 0 W
X I/O3 15 1100 -1300 200 L 50 50 0 0 B
X I/O4 16 1100 -1200 200 L 50 50 0 0 B
X I/O5 17 1100 -1100 200 L 50 50 0 0 B
X I/O6 18 1100 -1000 200 L 50 50 0 0 B
X I/O7 19 1100 -900 200 L 50 50 0 0 B
X A12 2 0 -100 200 R 50 50 0 0 I
X ~CE 20 1100 -800 200 L 50 50 0 0 I
X A10 21 1100 -700 200 L 50 50 0 0 I
X ~OE 22 1100 -600 200 L 50 50 0 0 I
X A11 23 1100 -500 200 L 50 50 0 0 I
X A9 24 1100 -400 200 L 50 50 0 0 I
X A8 25 1100 -300 200 L 50 50 0 0 I
X A13 26 1100 -200 200 L 50 50 0 0 I
X ~WE 27 1100 -100 200 L 50 50 0 0 I
X VCC 28 1100 0 200 L 50 50 0 0 W
X A7 3 0 -200 200 R 50 50 0 0 I
X A6 4 0 -300 200 R 50 50 0 0 I
X A5 5 0 -400 200 R 50 50 0 0 I
X A4 6 0 -500 200 R 50 50 0 0 I
X A3 7 0 -600 200 R 50 50 0 0 I
X A2 8 0 -700 200 R 50 50 0 0 I
X A1 9 0 -800 200 R 50 50 0 0 I
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP1
#
DEF Device_CP1 C 0 10 N N 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP1" 25 -100 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
P 2 0 1 20 -80 30 80 30 N
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 70 -50 110 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 130 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_US
#
DEF Device_R_US R 0 0 N Y 1 F N
F0 "R" 100 0 50 V V C CNN
F1 "Device_R_US" -100 0 50 V V C CNN
F2 "" 40 -10 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
P 2 0 1 0 0 -90 0 -100 N
P 2 0 1 0 0 90 0 100 N
P 5 0 1 0 0 -30 40 -45 0 -60 -40 -75 0 -90 N
P 5 0 1 0 0 30 40 15 0 0 -40 -15 0 -30 N
P 5 0 1 0 0 90 40 75 0 60 -40 45 0 30 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GAL22V10-15LP_GAL22V10-15LP
#
DEF GAL22V10-15LP_GAL22V10-15LP IC 0 30 Y Y 1 F N
F0 "IC" 950 300 50 H V L CNN
F1 "GAL22V10-15LP_GAL22V10-15LP" 950 200 50 H V L CNN
F2 "DIP760W45P254L3187H533Q24N" 1550 450 50 H I L CNN
F3 "http://uk.rs-online.com/web/p/products/4142962" 1550 650 50 H I L CNN
F4 "Lattice Semiconductor GAL22V10-15LP, SPLD GAL, 10 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP" 1550 550 50 H I L CNN "Description"
F5 "5.33" 950 -200 50 H I L CNN "Height"
DRAW
P 5 0 1 6 200 100 900 100 900 -1200 200 -1200 200 100 N
X CLK 1 0 0 200 R 50 50 0 0 I
X I_9 10 0 -900 200 R 50 50 0 0 I
X I_10 11 0 -1000 200 R 50 50 0 0 I
X GND 12 0 -1100 200 R 50 50 0 0 W
X I_11 13 1100 -1100 200 L 50 50 0 0 I
X IO_1 14 1100 -1000 200 L 50 50 0 0 B
X IO_2 15 1100 -900 200 L 50 50 0 0 B
X IO_3 16 1100 -800 200 L 50 50 0 0 B
X IO_4 17 1100 -700 200 L 50 50 0 0 B
X IO_5 18 1100 -600 200 L 50 50 0 0 B
X IO_6 19 1100 -500 200 L 50 50 0 0 B
X I_1 2 0 -100 200 R 50 50 0 0 I
X IO_7 20 1100 -400 200 L 50 50 0 0 B
X IO_8 21 1100 -300 200 L 50 50 0 0 B
X IO_9 22 1100 -200 200 L 50 50 0 0 B
X IO_10 23 1100 -100 200 L 50 50 0 0 B
X VCC 24 1100 0 200 L 50 50 0 0 W
X I_2 3 0 -200 200 R 50 50 0 0 I
X I_3 4 0 -300 200 R 50 50 0 0 I
X I_4 5 0 -400 200 R 50 50 0 0 I
X I_5 6 0 -500 200 R 50 50 0 0 I
X I_6 7 0 -600 200 R 50 50 0 0 I
X I_7 8 0 -700 200 R 50 50 0 0 I
X I_8 9 0 -800 200 R 50 50 0 0 I
ENDDRAW
ENDDEF
#
# Switch_SW_SPDT
#
DEF Switch_SW_SPDT SW 0 0 Y N 1 F N
F0 "SW" 0 170 50 H V C CNN
F1 "Switch_SW_SPDT" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C -80 0 20 0 0 0 N
C 80 -100 20 0 0 0 N
C 80 100 20 0 1 0 N
P 2 0 1 0 -60 10 65 90 N
X A 1 200 100 100 L 50 50 1 1 P
X B 2 -200 0 100 R 50 50 1 1 P
X C 3 200 -100 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+12V
#
DEF power_+12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+12V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +12V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

2146
Apple1Cartridge.kicad_pcb Normal file
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Apple1Cartridge.kicad_pcb-bak Normal file
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Apple1Cartridge.pro Normal file
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@ -0,0 +1,244 @@
update=2020 September 20, Sunday 00:36:42
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.4
TrackWidth3=1.3
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter2=0.8
ViaDrill2=0.4
ViaDiameter3=1.5
ViaDrill3=0.6
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

1096
Apple1Cartridge.sch Normal file
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Apple1Cartridge.sch-bak Normal file
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753
Apple1Cartridge.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<export version="D">
<design>
<source>/Users/piotrek/Projects/Apple1CartridgePcbV2/Apple1Cartridge.sch</source>
<date>2020 December 21, Monday 18:46:05</date>
<tool>Eeschema (5.1.5-0)</tool>
<sheet number="1" name="/" tstamps="/">
<title_block>
<title/>
<company/>
<rev/>
<date/>
<source>Apple1Cartridge.sch</source>
<comment number="1" value=""/>
<comment number="2" value=""/>
<comment number="3" value=""/>
<comment number="4" value=""/>
</title_block>
</sheet>
</design>
<components>
<comp ref="CONNECTOR1">
<value>44pin_edge</value>
<footprint>44pin:44pin1</footprint>
<libsource lib="44pin" part="44pin_edge" description=""/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F0B9D20</tstamp>
</comp>
<comp ref="DECODER1">
<value>GAL22V10</value>
<footprint>Package_DIP:DIP-24_W7.62mm_Socket_LongPads</footprint>
<fields>
<field name="Arrow Part Number">GAL22V10-15LP</field>
<field name="Description">Lattice Semiconductor GAL22V10-15LP, SPLD GAL, GAL20V8B 8 Macro Cells, 8 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP</field>
<field name="Height">5.33</field>
<field name="Manufacturer_Name">Lattice Semiconductor</field>
<field name="Manufacturer_Part_Number">GAL22V10-15LP</field>
</fields>
<libsource lib="GAL22V10-15LP" part="GAL22V10-15LP" description="Lattice Semiconductor GAL20V8B-15LP, SPLD GAL, GAL20V8B 8 Macro Cells, 8 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F0BF122</tstamp>
</comp>
<comp ref="ROM1">
<value>28C256</value>
<footprint>Package_DIP:DIP-28_W15.24mm_Socket_LongPads</footprint>
<datasheet>http://www.atmel.com/images/doc0270.pdf</datasheet>
<libsource lib="AT28C64B-15PU" part="AT28C256" description="AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F0CDB91</tstamp>
</comp>
<comp ref="RAM1">
<value>62256</value>
<footprint>Package_DIP:DIP-28_W15.24mm_Socket_LongPads</footprint>
<datasheet>http://www.atmel.com/images/doc0270.pdf</datasheet>
<libsource lib="AT28C64B-15PU" part="AT28C256" description="AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F0CF4BD</tstamp>
</comp>
<comp ref="BANK1">
<value>74LS74</value>
<footprint>Package_DIP:DIP-14_W7.62mm_Socket_LongPads</footprint>
<datasheet>74xx/74hc_hct74.pdf</datasheet>
<libsource lib="74xx" part="74LS74" description="Dual D Flip-flop, Set &amp; Reset"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F0D1D39</tstamp>
</comp>
<comp ref="ROM_PWR_REG1">
<value>L7805</value>
<footprint>Package_TO_SOT_THT:TO-220-3_Horizontal_TabDown</footprint>
<datasheet>http://www.st.com/content/ccc/resource/technical/document/datasheet/41/4f/b3/b0/12/d4/47/88/CD00000444.pdf/files/CD00000444.pdf/jcr:content/translations/en.CD00000444.pdf</datasheet>
<libsource lib="Regulator_Linear" part="L7805" description="Positive 1.5A 35V Linear Regulator, Fixed Output 5V, TO-220/TO-263/TO-252"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F0D3161</tstamp>
</comp>
<comp ref="ROM_PWR_SEL1">
<value>ROM_PWR_SEL</value>
<footprint>Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical</footprint>
<datasheet>~</datasheet>
<libsource lib="Connector" part="Conn_01x03_Male" description="Generic connector, single row, 01x03, script generated (kicad-library-utils/schlib/autogen/connector/)"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F128532</tstamp>
</comp>
<comp ref="MODE_SWITCH1">
<value>SW_SPDT</value>
<footprint>Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical</footprint>
<datasheet>~</datasheet>
<libsource lib="Switch" part="SW_SPDT" description="Switch, single pole double throw"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F232F13</tstamp>
</comp>
<comp ref="R2">
<value>1K</value>
<footprint>Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal</footprint>
<datasheet>~</datasheet>
<libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F2352C6</tstamp>
</comp>
<comp ref="R3">
<value>1K</value>
<footprint>Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal</footprint>
<datasheet>~</datasheet>
<libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F262E4C</tstamp>
</comp>
<comp ref="C4">
<value>0.1uF</value>
<footprint>Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P2.50mm</footprint>
<datasheet>~</datasheet>
<libsource lib="Device" part="C" description="Unpolarized capacitor"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F298AA6</tstamp>
</comp>
<comp ref="C1">
<value>0.1uF</value>
<footprint>Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P2.50mm</footprint>
<datasheet>~</datasheet>
<libsource lib="Device" part="C" description="Unpolarized capacitor"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F2A6131</tstamp>
</comp>
<comp ref="C3">
<value>0.1uF</value>
<footprint>Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P2.50mm</footprint>
<datasheet>~</datasheet>
<libsource lib="Device" part="C" description="Unpolarized capacitor"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5F2CD5E5</tstamp>
</comp>
<comp ref="RAM2">
<value>62256</value>
<footprint>Package_DIP:DIP-28_W15.24mm_Socket</footprint>
<datasheet>http://www.atmel.com/images/doc0270.pdf</datasheet>
<libsource lib="AT28C64B-15PU" part="AT28C256" description="AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5FB88FB3</tstamp>
</comp>
<comp ref="R1">
<value>1K</value>
<footprint>Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal</footprint>
<datasheet>~</datasheet>
<libsource lib="Device" part="R_US" description="Resistor, US symbol"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5FB93F7B</tstamp>
</comp>
<comp ref="C5">
<value>22uF</value>
<footprint>Capacitor_THT:CP_Radial_D4.0mm_P2.00mm</footprint>
<datasheet>~</datasheet>
<libsource lib="Device" part="CP1" description="Polarized capacitor, US symbol"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5FDCDD2C</tstamp>
</comp>
<comp ref="C2">
<value>0.1uF</value>
<footprint>Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P2.50mm</footprint>
<datasheet>~</datasheet>
<libsource lib="Device" part="C" description="Unpolarized capacitor"/>
<sheetpath names="/" tstamps="/"/>
<tstamp>5FDEE950</tstamp>
</comp>
</components>
<libparts>
<libpart lib="44pin" part="44pin_edge">
<fields>
<field name="Reference">U</field>
<field name="Value">44pin_edge</field>
</fields>
<pins>
<pin num="1" name="1" type="BiDi"/>
<pin num="2" name="2" type="BiDi"/>
<pin num="3" name="3" type="BiDi"/>
<pin num="4" name="4" type="BiDi"/>
<pin num="5" name="5" type="BiDi"/>
<pin num="6" name="6" type="BiDi"/>
<pin num="7" name="7" type="BiDi"/>
<pin num="8" name="8" type="BiDi"/>
<pin num="9" name="9" type="BiDi"/>
<pin num="10" name="10" type="BiDi"/>
<pin num="11" name="11" type="BiDi"/>
<pin num="12" name="12" type="BiDi"/>
<pin num="13" name="13" type="BiDi"/>
<pin num="14" name="14" type="BiDi"/>
<pin num="15" name="15" type="BiDi"/>
<pin num="16" name="16" type="BiDi"/>
<pin num="17" name="17" type="BiDi"/>
<pin num="18" name="18" type="BiDi"/>
<pin num="19" name="19" type="BiDi"/>
<pin num="20" name="20" type="BiDi"/>
<pin num="21" name="21" type="BiDi"/>
<pin num="22" name="22" type="BiDi"/>
<pin num="A" name="A" type="BiDi"/>
<pin num="B" name="B" type="BiDi"/>
<pin num="C" name="C" type="BiDi"/>
<pin num="D" name="D" type="BiDi"/>
<pin num="E" name="E" type="BiDi"/>
<pin num="F" name="F" type="BiDi"/>
<pin num="H" name="H" type="BiDi"/>
<pin num="J" name="J" type="BiDi"/>
<pin num="K" name="K" type="BiDi"/>
<pin num="L" name="L" type="BiDi"/>
<pin num="M" name="M" type="BiDi"/>
<pin num="N" name="N" type="BiDi"/>
<pin num="P" name="P" type="BiDi"/>
<pin num="R" name="R" type="BiDi"/>
<pin num="S" name="S" type="BiDi"/>
<pin num="T" name="T" type="BiDi"/>
<pin num="U" name="U" type="BiDi"/>
<pin num="V" name="V" type="BiDi"/>
<pin num="W" name="W" type="BiDi"/>
<pin num="X" name="X" type="BiDi"/>
<pin num="Y" name="Y" type="BiDi"/>
<pin num="Z" name="Z" type="BiDi"/>
</pins>
</libpart>
<libpart lib="74xx" part="74LS74">
<aliases>
<alias>74HC74</alias>
</aliases>
<description>Dual D Flip-flop, Set &amp; Reset</description>
<docs>74xx/74hc_hct74.pdf</docs>
<footprints>
<fp>DIP*W7.62mm*</fp>
</footprints>
<fields>
<field name="Reference">U</field>
<field name="Value">74LS74</field>
</fields>
<pins>
<pin num="1" name="~R" type="input"/>
<pin num="2" name="D" type="input"/>
<pin num="3" name="C" type="input"/>
<pin num="4" name="~S" type="input"/>
<pin num="5" name="Q" type="output"/>
<pin num="6" name="~Q" type="output"/>
<pin num="7" name="GND" type="power_in"/>
<pin num="8" name="~Q" type="output"/>
<pin num="9" name="Q" type="output"/>
<pin num="10" name="~S" type="input"/>
<pin num="11" name="C" type="input"/>
<pin num="12" name="D" type="input"/>
<pin num="13" name="~R" type="input"/>
<pin num="14" name="VCC" type="power_in"/>
</pins>
</libpart>
<libpart lib="AT28C64B-15PU" part="AT28C256">
<description>AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP</description>
<docs>http://www.atmel.com/images/doc0270.pdf</docs>
<fields>
<field name="Reference">IC</field>
<field name="Value">AT28C256</field>
<field name="Footprint">DIP1556W56P254L3702H483Q28N</field>
<field name="Datasheet">http://www.atmel.com/images/doc0270.pdf</field>
</fields>
<pins>
<pin num="1" name="A14" type="input"/>
<pin num="2" name="A12" type="input"/>
<pin num="3" name="A7" type="input"/>
<pin num="4" name="A6" type="input"/>
<pin num="5" name="A5" type="input"/>
<pin num="6" name="A4" type="input"/>
<pin num="7" name="A3" type="input"/>
<pin num="8" name="A2" type="input"/>
<pin num="9" name="A1" type="input"/>
<pin num="10" name="A0" type="input"/>
<pin num="11" name="I/O0" type="BiDi"/>
<pin num="12" name="I/O1" type="BiDi"/>
<pin num="13" name="I/O2" type="BiDi"/>
<pin num="14" name="GND" type="power_in"/>
<pin num="15" name="I/O3" type="BiDi"/>
<pin num="16" name="I/O4" type="BiDi"/>
<pin num="17" name="I/O5" type="BiDi"/>
<pin num="18" name="I/O6" type="BiDi"/>
<pin num="19" name="I/O7" type="BiDi"/>
<pin num="20" name="~CE" type="input"/>
<pin num="21" name="A10" type="input"/>
<pin num="22" name="~OE" type="input"/>
<pin num="23" name="A11" type="input"/>
<pin num="24" name="A9" type="input"/>
<pin num="25" name="A8" type="input"/>
<pin num="26" name="A13" type="input"/>
<pin num="27" name="~WE" type="input"/>
<pin num="28" name="VCC" type="power_in"/>
</pins>
</libpart>
<libpart lib="Connector" part="Conn_01x03_Male">
<description>Generic connector, single row, 01x03, script generated (kicad-library-utils/schlib/autogen/connector/)</description>
<docs>~</docs>
<footprints>
<fp>Connector*:*_1x??_*</fp>
</footprints>
<fields>
<field name="Reference">J</field>
<field name="Value">Conn_01x03_Male</field>
</fields>
<pins>
<pin num="1" name="Pin_1" type="passive"/>
<pin num="2" name="Pin_2" type="passive"/>
<pin num="3" name="Pin_3" type="passive"/>
</pins>
</libpart>
<libpart lib="Device" part="C">
<description>Unpolarized capacitor</description>
<docs>~</docs>
<footprints>
<fp>C_*</fp>
</footprints>
<fields>
<field name="Reference">C</field>
<field name="Value">C</field>
</fields>
<pins>
<pin num="1" name="~" type="passive"/>
<pin num="2" name="~" type="passive"/>
</pins>
</libpart>
<libpart lib="Device" part="CP1">
<description>Polarized capacitor, US symbol</description>
<docs>~</docs>
<footprints>
<fp>CP_*</fp>
</footprints>
<fields>
<field name="Reference">C</field>
<field name="Value">CP1</field>
</fields>
<pins>
<pin num="1" name="~" type="passive"/>
<pin num="2" name="~" type="passive"/>
</pins>
</libpart>
<libpart lib="Device" part="R_US">
<description>Resistor, US symbol</description>
<docs>~</docs>
<footprints>
<fp>R_*</fp>
</footprints>
<fields>
<field name="Reference">R</field>
<field name="Value">R_US</field>
</fields>
<pins>
<pin num="1" name="~" type="passive"/>
<pin num="2" name="~" type="passive"/>
</pins>
</libpart>
<libpart lib="GAL22V10-15LP" part="GAL22V10-15LP">
<description>Lattice Semiconductor GAL20V8B-15LP, SPLD GAL, GAL20V8B 8 Macro Cells, 8 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP</description>
<docs>http://uk.rs-online.com/web/p/products/4142962</docs>
<fields>
<field name="Reference">IC</field>
<field name="Value">GAL22V10-15LP</field>
<field name="Footprint">DIP760W45P254L3187H533Q24N</field>
<field name="Datasheet">http://uk.rs-online.com/web/p/products/4142962</field>
<field name="Description">Lattice Semiconductor GAL22V10-15LP, SPLD GAL, 10 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP</field>
<field name="Height">5.33</field>
</fields>
<pins>
<pin num="1" name="CLK" type="input"/>
<pin num="2" name="I_1" type="input"/>
<pin num="3" name="I_2" type="input"/>
<pin num="4" name="I_3" type="input"/>
<pin num="5" name="I_4" type="input"/>
<pin num="6" name="I_5" type="input"/>
<pin num="7" name="I_6" type="input"/>
<pin num="8" name="I_7" type="input"/>
<pin num="9" name="I_8" type="input"/>
<pin num="10" name="I_9" type="input"/>
<pin num="11" name="I_10" type="input"/>
<pin num="12" name="GND" type="power_in"/>
<pin num="13" name="I_11" type="input"/>
<pin num="14" name="IO_1" type="BiDi"/>
<pin num="15" name="IO_2" type="BiDi"/>
<pin num="16" name="IO_3" type="BiDi"/>
<pin num="17" name="IO_4" type="BiDi"/>
<pin num="18" name="IO_5" type="BiDi"/>
<pin num="19" name="IO_6" type="BiDi"/>
<pin num="20" name="IO_7" type="BiDi"/>
<pin num="21" name="IO_8" type="BiDi"/>
<pin num="22" name="IO_9" type="BiDi"/>
<pin num="23" name="IO_10" type="BiDi"/>
<pin num="24" name="VCC" type="power_in"/>
</pins>
</libpart>
<libpart lib="Regulator_Linear" part="L7805">
<aliases>
<alias>L7806</alias>
<alias>L7808</alias>
<alias>L7885</alias>
<alias>L7809</alias>
<alias>L7812</alias>
<alias>L7815</alias>
<alias>L7818</alias>
<alias>L7824</alias>
</aliases>
<description>Positive 1.5A 35V Linear Regulator, Fixed Output 5V, TO-220/TO-263/TO-252</description>
<docs>http://www.st.com/content/ccc/resource/technical/document/datasheet/41/4f/b3/b0/12/d4/47/88/CD00000444.pdf/files/CD00000444.pdf/jcr:content/translations/en.CD00000444.pdf</docs>
<footprints>
<fp>TO?252*</fp>
<fp>TO?263*</fp>
<fp>TO?220*</fp>
</footprints>
<fields>
<field name="Reference">U</field>
<field name="Value">L7805</field>
</fields>
<pins>
<pin num="1" name="IN" type="power_in"/>
<pin num="2" name="GND" type="power_in"/>
<pin num="3" name="OUT" type="power_out"/>
</pins>
</libpart>
<libpart lib="Switch" part="SW_SPDT">
<description>Switch, single pole double throw</description>
<docs>~</docs>
<fields>
<field name="Reference">SW</field>
<field name="Value">SW_SPDT</field>
</fields>
<pins>
<pin num="1" name="A" type="passive"/>
<pin num="2" name="B" type="passive"/>
<pin num="3" name="C" type="passive"/>
</pins>
</libpart>
</libparts>
<libraries>
<library logical="44pin">
<uri>/Users/piotrek/44pin/44pin.lib</uri>
</library>
<library logical="74xx">
<uri>/Library/Application Support/kicad/library/74xx.lib</uri>
</library>
<library logical="AT28C64B-15PU">
<uri>/Users/piotrek/Projects/Apple1CartridgePcbV2/at28c64b/AT28C64B-15PU.lib</uri>
</library>
<library logical="Connector">
<uri>/Library/Application Support/kicad/library/Connector.lib</uri>
</library>
<library logical="Device">
<uri>/Library/Application Support/kicad/library/Device.lib</uri>
</library>
<library logical="GAL22V10-15LP">
<uri>/Users/piotrek/Projects/Apple1CartridgePcbV2/gal22v10/GAL22V10-15LP.lib</uri>
</library>
<library logical="Regulator_Linear">
<uri>/Library/Application Support/kicad/library/Regulator_Linear.lib</uri>
</library>
<library logical="Switch">
<uri>/Library/Application Support/kicad/library/Switch.lib</uri>
</library>
</libraries>
<nets>
<net code="1" name="Net-(CONNECTOR1-Pad1)">
<node ref="CONNECTOR1" pin="1"/>
</net>
<net code="2" name="Net-(CONNECTOR1-Pad10)">
<node ref="CONNECTOR1" pin="10"/>
</net>
<net code="3" name="Net-(CONNECTOR1-Pad11)">
<node ref="CONNECTOR1" pin="11"/>
</net>
<net code="4" name="Net-(CONNECTOR1-Pad21)">
<node ref="CONNECTOR1" pin="21"/>
</net>
<net code="5" name="+5V">
<node ref="ROM_PWR_SEL1" pin="3"/>
<node ref="BANK1" pin="14"/>
<node ref="CONNECTOR1" pin="22"/>
<node ref="C5" pin="1"/>
<node ref="R2" pin="1"/>
<node ref="R3" pin="1"/>
<node ref="C4" pin="1"/>
<node ref="R1" pin="1"/>
<node ref="C1" pin="1"/>
<node ref="C3" pin="1"/>
<node ref="RAM1" pin="28"/>
<node ref="DECODER1" pin="24"/>
<node ref="RAM2" pin="28"/>
</net>
<net code="6" name="Net-(CONNECTOR1-Pad3)">
<node ref="CONNECTOR1" pin="3"/>
</net>
<net code="7" name="Net-(CONNECTOR1-Pad4)">
<node ref="CONNECTOR1" pin="4"/>
</net>
<net code="8" name="Net-(CONNECTOR1-Pad5)">
<node ref="CONNECTOR1" pin="5"/>
</net>
<net code="9" name="Net-(CONNECTOR1-PadB)">
<node ref="CONNECTOR1" pin="B"/>
</net>
<net code="10" name="Net-(CONNECTOR1-PadC)">
<node ref="CONNECTOR1" pin="C"/>
</net>
<net code="11" name="Net-(CONNECTOR1-PadD)">
<node ref="CONNECTOR1" pin="D"/>
</net>
<net code="12" name="Net-(CONNECTOR1-PadL)">
<node ref="CONNECTOR1" pin="L"/>
</net>
<net code="13" name="Net-(CONNECTOR1-PadM)">
<node ref="CONNECTOR1" pin="M"/>
</net>
<net code="14" name="Net-(CONNECTOR1-PadZ)">
<node ref="CONNECTOR1" pin="Z"/>
</net>
<net code="15" name="Net-(DECODER1-Pad1)">
<node ref="DECODER1" pin="1"/>
</net>
<net code="16" name="Net-(C2-Pad1)">
<node ref="ROM_PWR_SEL1" pin="2"/>
<node ref="C2" pin="1"/>
<node ref="ROM1" pin="28"/>
</net>
<net code="17" name="Net-(BANK1-Pad6)">
<node ref="BANK1" pin="6"/>
</net>
<net code="18" name="PHI2">
<node ref="CONNECTOR1" pin="A"/>
<node ref="DECODER1" pin="2"/>
</net>
<net code="19" name="RW">
<node ref="CONNECTOR1" pin="K"/>
<node ref="RAM2" pin="27"/>
<node ref="RAM1" pin="27"/>
<node ref="DECODER1" pin="3"/>
</net>
<net code="20" name="MODE">
<node ref="MODE_SWITCH1" pin="2"/>
<node ref="DECODER1" pin="4"/>
</net>
<net code="21" name="A9">
<node ref="RAM1" pin="24"/>
<node ref="CONNECTOR1" pin="15"/>
<node ref="DECODER1" pin="5"/>
<node ref="ROM1" pin="24"/>
<node ref="RAM2" pin="24"/>
</net>
<net code="22" name="A8">
<node ref="RAM2" pin="25"/>
<node ref="ROM1" pin="25"/>
<node ref="DECODER1" pin="6"/>
<node ref="CONNECTOR1" pin="S"/>
<node ref="RAM1" pin="25"/>
</net>
<net code="23" name="A7">
<node ref="ROM1" pin="3"/>
<node ref="DECODER1" pin="7"/>
<node ref="RAM2" pin="3"/>
<node ref="RAM1" pin="3"/>
<node ref="CONNECTOR1" pin="16"/>
</net>
<net code="24" name="A6">
<node ref="DECODER1" pin="8"/>
<node ref="CONNECTOR1" pin="T"/>
<node ref="ROM1" pin="4"/>
<node ref="RAM2" pin="4"/>
<node ref="RAM1" pin="4"/>
</net>
<net code="25" name="A5">
<node ref="ROM1" pin="5"/>
<node ref="RAM2" pin="5"/>
<node ref="DECODER1" pin="9"/>
<node ref="CONNECTOR1" pin="17"/>
<node ref="RAM1" pin="5"/>
</net>
<net code="26" name="A4">
<node ref="RAM2" pin="6"/>
<node ref="ROM1" pin="6"/>
<node ref="CONNECTOR1" pin="U"/>
<node ref="DECODER1" pin="10"/>
<node ref="RAM1" pin="6"/>
</net>
<net code="27" name="A3">
<node ref="RAM2" pin="7"/>
<node ref="DECODER1" pin="11"/>
<node ref="CONNECTOR1" pin="18"/>
<node ref="RAM1" pin="7"/>
<node ref="ROM1" pin="7"/>
</net>
<net code="28" name="A13">
<node ref="DECODER1" pin="14"/>
<node ref="CONNECTOR1" pin="13"/>
<node ref="RAM1" pin="26"/>
<node ref="RAM2" pin="26"/>
<node ref="ROM1" pin="26"/>
</net>
<net code="29" name="A14">
<node ref="CONNECTOR1" pin="N"/>
<node ref="DECODER1" pin="15"/>
</net>
<net code="30" name="A12">
<node ref="DECODER1" pin="16"/>
<node ref="RAM1" pin="2"/>
<node ref="RAM2" pin="2"/>
<node ref="CONNECTOR1" pin="P"/>
<node ref="ROM1" pin="2"/>
</net>
<net code="31" name="RAM1">
<node ref="RAM1" pin="20"/>
<node ref="DECODER1" pin="19"/>
</net>
<net code="32" name="A11">
<node ref="CONNECTOR1" pin="14"/>
<node ref="ROM1" pin="23"/>
<node ref="RAM2" pin="23"/>
<node ref="RAM1" pin="23"/>
<node ref="DECODER1" pin="17"/>
</net>
<net code="33" name="A10">
<node ref="ROM1" pin="21"/>
<node ref="RAM2" pin="21"/>
<node ref="DECODER1" pin="18"/>
<node ref="RAM1" pin="21"/>
<node ref="CONNECTOR1" pin="R"/>
</net>
<net code="34" name="FLIP_FLOP">
<node ref="BANK1" pin="3"/>
<node ref="DECODER1" pin="22"/>
</net>
<net code="35" name="BANK">
<node ref="BANK1" pin="5"/>
<node ref="DECODER1" pin="23"/>
</net>
<net code="36" name="ROM">
<node ref="ROM1" pin="20"/>
<node ref="DECODER1" pin="21"/>
</net>
<net code="37" name="RAM2">
<node ref="RAM2" pin="20"/>
<node ref="DECODER1" pin="20"/>
</net>
<net code="38" name="A0">
<node ref="RAM2" pin="10"/>
<node ref="CONNECTOR1" pin="W"/>
<node ref="BANK1" pin="2"/>
<node ref="RAM1" pin="10"/>
<node ref="ROM1" pin="10"/>
</net>
<net code="39" name="RES">
<node ref="BANK1" pin="1"/>
<node ref="CONNECTOR1" pin="2"/>
</net>
<net code="40" name="D0">
<node ref="RAM2" pin="11"/>
<node ref="CONNECTOR1" pin="9"/>
<node ref="ROM1" pin="11"/>
<node ref="RAM1" pin="11"/>
</net>
<net code="41" name="D2">
<node ref="RAM1" pin="13"/>
<node ref="RAM2" pin="13"/>
<node ref="CONNECTOR1" pin="8"/>
<node ref="ROM1" pin="13"/>
</net>
<net code="42" name="D4">
<node ref="RAM1" pin="16"/>
<node ref="ROM1" pin="16"/>
<node ref="CONNECTOR1" pin="7"/>
<node ref="RAM2" pin="16"/>
</net>
<net code="43" name="D6">
<node ref="CONNECTOR1" pin="6"/>
<node ref="RAM2" pin="18"/>
<node ref="ROM1" pin="18"/>
<node ref="RAM1" pin="18"/>
</net>
<net code="44" name="D1">
<node ref="CONNECTOR1" pin="J"/>
<node ref="RAM1" pin="12"/>
<node ref="RAM2" pin="12"/>
<node ref="ROM1" pin="12"/>
</net>
<net code="45" name="D3">
<node ref="CONNECTOR1" pin="H"/>
<node ref="RAM2" pin="15"/>
<node ref="RAM1" pin="15"/>
<node ref="ROM1" pin="15"/>
</net>
<net code="46" name="D5">
<node ref="RAM2" pin="17"/>
<node ref="CONNECTOR1" pin="F"/>
<node ref="ROM1" pin="17"/>
<node ref="RAM1" pin="17"/>
</net>
<net code="47" name="D7">
<node ref="CONNECTOR1" pin="E"/>
<node ref="RAM1" pin="19"/>
<node ref="RAM2" pin="19"/>
<node ref="ROM1" pin="19"/>
</net>
<net code="48" name="A2">
<node ref="RAM1" pin="8"/>
<node ref="CONNECTOR1" pin="V"/>
<node ref="RAM2" pin="8"/>
<node ref="ROM1" pin="8"/>
</net>
<net code="49" name="A1">
<node ref="RAM2" pin="9"/>
<node ref="RAM1" pin="9"/>
<node ref="ROM1" pin="9"/>
<node ref="CONNECTOR1" pin="19"/>
</net>
<net code="50" name="A15">
<node ref="CONNECTOR1" pin="12"/>
<node ref="RAM2" pin="1"/>
<node ref="RAM1" pin="1"/>
<node ref="DECODER1" pin="13"/>
<node ref="ROM1" pin="1"/>
</net>
<net code="51" name="+12V">
<node ref="CONNECTOR1" pin="Y"/>
<node ref="ROM_PWR_REG1" pin="1"/>
</net>
<net code="52" name="Net-(ROM_PWR_REG1-Pad3)">
<node ref="ROM_PWR_SEL1" pin="1"/>
<node ref="ROM_PWR_REG1" pin="3"/>
</net>
<net code="53" name="Net-(MODE_SWITCH1-Pad1)">
<node ref="MODE_SWITCH1" pin="1"/>
<node ref="R2" pin="2"/>
</net>
<net code="54" name="Net-(BANK1-Pad4)">
<node ref="R3" pin="2"/>
<node ref="BANK1" pin="4"/>
</net>
<net code="55" name="Net-(R1-Pad2)">
<node ref="ROM1" pin="27"/>
<node ref="R1" pin="2"/>
</net>
<net code="56" name="GND">
<node ref="C1" pin="2"/>
<node ref="ROM1" pin="14"/>
<node ref="ROM_PWR_REG1" pin="2"/>
<node ref="ROM1" pin="22"/>
<node ref="C3" pin="2"/>
<node ref="RAM1" pin="22"/>
<node ref="MODE_SWITCH1" pin="3"/>
<node ref="DECODER1" pin="12"/>
<node ref="RAM2" pin="14"/>
<node ref="CONNECTOR1" pin="X"/>
<node ref="RAM2" pin="22"/>
<node ref="C5" pin="2"/>
<node ref="C2" pin="2"/>
<node ref="CONNECTOR1" pin="20"/>
<node ref="BANK1" pin="7"/>
<node ref="RAM1" pin="14"/>
<node ref="C4" pin="2"/>
</net>
</nets>
</export>

13
at28c64b/AT28C64B-15PU.bck Executable file
View File

@ -0,0 +1,13 @@
EESchema-DOCLIB Version 2.0
#
$CMP AT28C256
D AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP
F http://www.atmel.com/images/doc0270.pdf
$ENDCMP
#
$CMP AT28C64B-15PU
D AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP
F http://www.atmel.com/images/doc0270.pdf
$ENDCMP
#
#End Doc Library

13
at28c64b/AT28C64B-15PU.dcm Executable file
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@ -0,0 +1,13 @@
EESchema-DOCLIB Version 2.0
#
$CMP AT28C256
D AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP
F http://www.atmel.com/images/doc0270.pdf
$ENDCMP
#
$CMP AT28C64B-15PU
D AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP
F http://www.atmel.com/images/doc0270.pdf
$ENDCMP
#
#End Doc Library

90
at28c64b/AT28C64B-15PU.lib Executable file
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@ -0,0 +1,90 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# AT28C256
#
DEF AT28C256 IC 0 30 Y Y 1 F N
F0 "IC" 950 300 50 H V L CNN
F1 "AT28C256" 950 200 50 H V L CNN
F2 "DIP1556W56P254L3702H483Q28N" 950 100 50 H I L CNN
F3 "http://www.atmel.com/images/doc0270.pdf" 950 0 50 H I L CNN
DRAW
P 5 0 1 6 200 100 900 100 900 -1400 200 -1400 200 100 N
X A14 1 0 0 200 R 50 50 0 0 I
X A0 10 0 -900 200 R 50 50 0 0 I
X I/O0 11 0 -1000 200 R 50 50 0 0 B
X I/O1 12 0 -1100 200 R 50 50 0 0 B
X I/O2 13 0 -1200 200 R 50 50 0 0 B
X GND 14 0 -1300 200 R 50 50 0 0 W
X I/O3 15 1100 -1300 200 L 50 50 0 0 B
X I/O4 16 1100 -1200 200 L 50 50 0 0 B
X I/O5 17 1100 -1100 200 L 50 50 0 0 B
X I/O6 18 1100 -1000 200 L 50 50 0 0 B
X I/O7 19 1100 -900 200 L 50 50 0 0 B
X A12 2 0 -100 200 R 50 50 0 0 I
X ~CE 20 1100 -800 200 L 50 50 0 0 I
X A10 21 1100 -700 200 L 50 50 0 0 I
X ~OE 22 1100 -600 200 L 50 50 0 0 I
X A11 23 1100 -500 200 L 50 50 0 0 I
X A9 24 1100 -400 200 L 50 50 0 0 I
X A8 25 1100 -300 200 L 50 50 0 0 I
X A13 26 1100 -200 200 L 50 50 0 0 I
X ~WE 27 1100 -100 200 L 50 50 0 0 I
X VCC 28 1100 0 200 L 50 50 0 0 W
X A7 3 0 -200 200 R 50 50 0 0 I
X A6 4 0 -300 200 R 50 50 0 0 I
X A5 5 0 -400 200 R 50 50 0 0 I
X A4 6 0 -500 200 R 50 50 0 0 I
X A3 7 0 -600 200 R 50 50 0 0 I
X A2 8 0 -700 200 R 50 50 0 0 I
X A1 9 0 -800 200 R 50 50 0 0 I
ENDDRAW
ENDDEF
#
# AT28C64B-15PU
#
DEF AT28C64B-15PU IC 0 30 Y Y 1 F N
F0 "IC" 950 300 50 H V L CNN
F1 "AT28C64B-15PU" 950 200 50 H V L CNN
F2 "DIP1556W56P254L3702H483Q28N" 950 100 50 H I L CNN
F3 "http://www.atmel.com/images/doc0270.pdf" 950 0 50 H I L CNN
F4 "AT28C64B-15PU, Parallel EEPROM Memory 64kbit, Parallel, 150ns 4.5 5.5 V, 28-Pin PDIP" 950 -100 50 H I L CNN "Description"
F5 "4.826" 950 -200 50 H I L CNN "Height"
F6 "556-AT28C64B15PU" 950 -300 50 H I L CNN "Mouser Part Number"
F7 "https://www.mouser.co.uk/ProductDetail/Microchip-Technology-Atmel/AT28C64B-15PU?qs=2VKgqYuc3OvipbcAuBcLow%3D%3D" 950 -400 50 H I L CNN "Mouser Price/Stock"
F8 "Microchip" 950 -500 50 H I L CNN "Manufacturer_Name"
F9 "AT28C64B-15PU" 950 -600 50 H I L CNN "Manufacturer_Part_Number"
DRAW
P 5 0 1 6 200 100 900 100 900 -1400 200 -1400 200 100 N
X NC 1 0 0 200 R 50 50 0 0 N
X A0 10 0 -900 200 R 50 50 0 0 I
X I/O0 11 0 -1000 200 R 50 50 0 0 B
X I/O1 12 0 -1100 200 R 50 50 0 0 B
X I/O2 13 0 -1200 200 R 50 50 0 0 B
X GND 14 0 -1300 200 R 50 50 0 0 W
X I/O3 15 1100 -1300 200 L 50 50 0 0 B
X I/O4 16 1100 -1200 200 L 50 50 0 0 B
X I/O5 17 1100 -1100 200 L 50 50 0 0 B
X I/O6 18 1100 -1000 200 L 50 50 0 0 B
X I/O7 19 1100 -900 200 L 50 50 0 0 B
X A12 2 0 -100 200 R 50 50 0 0 I
X ~CE 20 1100 -800 200 L 50 50 0 0 I
X A10 21 1100 -700 200 L 50 50 0 0 I
X ~OE 22 1100 -600 200 L 50 50 0 0 I
X A11 23 1100 -500 200 L 50 50 0 0 I
X A9 24 1100 -400 200 L 50 50 0 0 I
X A8 25 1100 -300 200 L 50 50 0 0 I
X NC_1 26 1100 -200 200 L 50 50 0 0 P
X ~WE 27 1100 -100 200 L 50 50 0 0 I
X VCC 28 1100 0 200 L 50 50 0 0 W
X A7 3 0 -200 200 R 50 50 0 0 I
X A6 4 0 -300 200 R 50 50 0 0 I
X A5 5 0 -400 200 R 50 50 0 0 I
X A4 6 0 -500 200 R 50 50 0 0 I
X A3 7 0 -600 200 R 50 50 0 0 I
X A2 8 0 -700 200 R 50 50 0 0 I
X A1 9 0 -800 200 R 50 50 0 0 I
ENDDRAW
ENDDEF
#
#End Library

226
at28c64b/AT28C64B-15PU.mod Executable file
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@ -0,0 +1,226 @@
PCBNEW-LibModule-V1 2020-06-12 17:07:03
# encoding utf-8
Units mm
$INDEX
DIP1556W56P254L3702H483Q28N
$EndINDEX
$MODULE DIP1556W56P254L3702H483Q28N
Po 0 0 0 15 5ee3a827 00000000 ~~
Li DIP1556W56P254L3702H483Q28N
Cd 28P6
Kw Integrated Circuit
Sc 0
At STD
AR
Op 0 0 0
T0 0 0 1.27 1.27 0 0.254 N V 21 N "IC**"
T1 0 0 1.27 1.27 0 0.254 N I 21 N "DIP1556W56P254L3702H483Q28N"
DS -8.767 -18.919 8.767 -18.919 0.05 24
DS 8.767 -18.919 8.767 18.919 0.05 24
DS 8.767 18.919 -8.767 18.919 0.05 24
DS -8.767 18.919 -8.767 -18.919 0.05 24
DS -6.985 -18.669 6.985 -18.669 0.1 24
DS 6.985 -18.669 6.985 18.669 0.1 24
DS 6.985 18.669 -6.985 18.669 0.1 24
DS -6.985 18.669 -6.985 -18.669 0.1 24
DS -6.985 -17.399 -5.715 -18.669 0.1 24
DS -8.358 -18.669 6.985 -18.669 0.2 21
DS -6.985 18.669 6.985 18.669 0.2 21
$PAD
Po -7.779 -16.51
Sh "1" R 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 -13.97
Sh "2" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 -11.43
Sh "3" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 -8.89
Sh "4" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 -6.35
Sh "5" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 -3.81
Sh "6" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 -1.27
Sh "7" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 1.27
Sh "8" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 3.81
Sh "9" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 6.35
Sh "10" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 8.89
Sh "11" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 11.43
Sh "12" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 13.97
Sh "13" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po -7.779 16.51
Sh "14" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 16.51
Sh "15" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 13.97
Sh "16" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 11.43
Sh "17" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 8.89
Sh "18" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 6.35
Sh "19" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 3.81
Sh "20" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 1.27
Sh "21" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 -1.27
Sh "22" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 -3.81
Sh "23" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 -6.35
Sh "24" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 -8.89
Sh "25" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 -11.43
Sh "26" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 -13.97
Sh "27" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$PAD
Po 7.779 -16.51
Sh "28" C 1.159 1.159 0 0 900
Dr 0.759 0 0
At STD N 00E0FFFF
Ne 0 ""
$EndPAD
$EndMODULE DIP1556W56P254L3702H483Q28N
$EndLIBRARY

57
at28c64b/DIP1556W56P254L3702H483Q28N.kicad_mod Executable file
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@ -0,0 +1,57 @@
(module "DIP1556W56P254L3702H483Q28N" (layer F.Cu)
(descr "28P6")
(tags "Integrated Circuit")
(fp_text reference IC** (at 0 0) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
(fp_text value "DIP1556W56P254L3702H483Q28N" (at 0 0) (layer F.SilkS) hide
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
(fp_line (start -8.767 -18.919) (end 8.767 -18.919) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.767 -18.919) (end 8.767 18.919) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.767 18.919) (end -8.767 18.919) (layer F.CrtYd) (width 0.05))
(fp_line (start -8.767 18.919) (end -8.767 -18.919) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.985 -18.669) (end 6.985 -18.669) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -18.669) (end 6.985 18.669) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 18.669) (end -6.985 18.669) (layer F.Fab) (width 0.1))
(fp_line (start -6.985 18.669) (end -6.985 -18.669) (layer F.Fab) (width 0.1))
(fp_line (start -6.985 -17.399) (end -5.715 -18.669) (layer F.Fab) (width 0.1))
(fp_line (start -8.358 -18.669) (end 6.985 -18.669) (layer F.SilkS) (width 0.2))
(fp_line (start -6.985 18.669) (end 6.985 18.669) (layer F.SilkS) (width 0.2))
(pad 1 thru_hole rect (at -7.779 -16.51) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -7.779 -13.97) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at -7.779 -11.43) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at -7.779 -8.89) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at -7.779 -6.35) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 6 thru_hole circle (at -7.779 -3.81) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 7 thru_hole circle (at -7.779 -1.27) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 8 thru_hole circle (at -7.779 1.27) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 9 thru_hole circle (at -7.779 3.81) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 10 thru_hole circle (at -7.779 6.35) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 11 thru_hole circle (at -7.779 8.89) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 12 thru_hole circle (at -7.779 11.43) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 13 thru_hole circle (at -7.779 13.97) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 14 thru_hole circle (at -7.779 16.51) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 15 thru_hole circle (at 7.779 16.51) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 16 thru_hole circle (at 7.779 13.97) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 17 thru_hole circle (at 7.779 11.43) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 18 thru_hole circle (at 7.779 8.89) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 19 thru_hole circle (at 7.779 6.35) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 20 thru_hole circle (at 7.779 3.81) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 21 thru_hole circle (at 7.779 1.27) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 22 thru_hole circle (at 7.779 -1.27) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 23 thru_hole circle (at 7.779 -3.81) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 24 thru_hole circle (at 7.779 -6.35) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 25 thru_hole circle (at 7.779 -8.89) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 26 thru_hole circle (at 7.779 -11.43) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 27 thru_hole circle (at 7.779 -13.97) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(pad 28 thru_hole circle (at 7.779 -16.51) (size 1.159 1.159) (drill 0.759) (layers *.Cu *.Mask))
(model AT28C64B-15PU.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

75279
fp-info-cache Normal file
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File diff suppressed because it is too large Load Diff

3
fp-lib-table Normal file
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@ -0,0 +1,3 @@
(fp_lib_table
(lib (name 44pin)(type KiCad)(uri ${KIPRJMOD}/44pin.pretty)(options "")(descr "44 pin edge connector"))
)

13
gal22v10/GAL22V10-15LP.bck Normal file
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@ -0,0 +1,13 @@
EESchema-DOCLIB Version 2.0
#
$CMP GAL20V8B-15LP
D Lattice Semiconductor GAL20V8B-15LP, SPLD GAL, GAL20V8B 8 Macro Cells, 8 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP
F http://uk.rs-online.com/web/p/products/4142962
$ENDCMP
#
$CMP GAL22V10-15LP
D Lattice Semiconductor GAL20V8B-15LP, SPLD GAL, GAL20V8B 8 Macro Cells, 8 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP
F http://uk.rs-online.com/web/p/products/4142962
$ENDCMP
#
#End Doc Library

8
gal22v10/GAL22V10-15LP.dcm Normal file
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@ -0,0 +1,8 @@
EESchema-DOCLIB Version 2.0
#
$CMP GAL22V10-15LP
D Lattice Semiconductor GAL20V8B-15LP, SPLD GAL, GAL20V8B 8 Macro Cells, 8 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP
F http://uk.rs-online.com/web/p/products/4142962
$ENDCMP
#
#End Doc Library

42
gal22v10/GAL22V10-15LP.lib Normal file
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@ -0,0 +1,42 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# GAL22V10-15LP
#
DEF GAL22V10-15LP IC 0 30 Y Y 1 F N
F0 "IC" 950 300 50 H V L CNN
F1 "GAL22V10-15LP" 950 200 50 H V L CNN
F2 "DIP760W45P254L3187H533Q24N" 1550 450 50 H I L CNN
F3 "http://uk.rs-online.com/web/p/products/4142962" 1550 650 50 H I L CNN
F4 "Lattice Semiconductor GAL22V10-15LP, SPLD GAL, 10 I/O, 62.5MHz External 15ns EECMOS 24-Pin PDIP" 1550 550 50 H I L CNN "Description"
F5 "5.33" 950 -200 50 H I L CNN "Height"
DRAW
P 5 0 1 6 200 100 900 100 900 -1200 200 -1200 200 100 N
X CLK 1 0 0 200 R 50 50 0 0 I
X I_9 10 0 -900 200 R 50 50 0 0 I
X I_10 11 0 -1000 200 R 50 50 0 0 I
X GND 12 0 -1100 200 R 50 50 0 0 W
X I_11 13 1100 -1100 200 L 50 50 0 0 I
X IO_1 14 1100 -1000 200 L 50 50 0 0 B
X IO_2 15 1100 -900 200 L 50 50 0 0 B
X IO_3 16 1100 -800 200 L 50 50 0 0 B
X IO_4 17 1100 -700 200 L 50 50 0 0 B
X IO_5 18 1100 -600 200 L 50 50 0 0 B
X IO_6 19 1100 -500 200 L 50 50 0 0 B
X I_1 2 0 -100 200 R 50 50 0 0 I
X IO_7 20 1100 -400 200 L 50 50 0 0 B
X IO_8 21 1100 -300 200 L 50 50 0 0 B
X IO_9 22 1100 -200 200 L 50 50 0 0 B
X IO_10 23 1100 -100 200 L 50 50 0 0 B
X VCC 24 1100 0 200 L 50 50 0 0 W
X I_2 3 0 -200 200 R 50 50 0 0 I
X I_3 4 0 -300 200 R 50 50 0 0 I
X I_4 5 0 -400 200 R 50 50 0 0 I
X I_5 6 0 -500 200 R 50 50 0 0 I
X I_6 7 0 -600 200 R 50 50 0 0 I
X I_7 8 0 -700 200 R 50 50 0 0 I
X I_8 9 0 -800 200 R 50 50 0 0 I
ENDDRAW
ENDDEF
#
#End Library

5
sym-lib-table Normal file
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@ -0,0 +1,5 @@
(sym_lib_table
(lib (name GAL22V10-15LP)(type Legacy)(uri ${KIPRJMOD}/gal22v10/GAL22V10-15LP.lib)(options "")(descr ""))
(lib (name AT28C64B-15PU)(type Legacy)(uri ${KIPRJMOD}/at28c64b/AT28C64B-15PU.lib)(options "")(descr ""))
(lib (name 44pin)(type Legacy)(uri ${KIPRJMOD}/44pin.lib)(options "")(descr ""))
)