@W: MT246 :"c:\dev\apple1display\impl1\master_clk.vhd":109:4:109:12|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock apple1display|line_clock_inferred_clock with period 6.07ns. Please declare a user-defined clock on object "n:apple_module.line_clock"
@W: MT420 |Found inferred clock apple1display|mem0_inferred_clock with period 3.71ns. Please declare a user-defined clock on object "n:apple_module.mem0"
@W: MT420 |Found inferred clock dm7400|y2_1_inferred_clock with period 3.76ns. Please declare a user-defined clock on object "n:apple_module.D10.y2_1"
