    --------------------------------------------------------------------------------
    Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.10.2.115
    Mon Aug 05 08:38:33 2019

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Design file:     FleaFPGA_Uno_E1
    Device,speed:    LCMXO2-7000HC,M
    Report level:    verbose report, limited to 10 items per preference
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
                0 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
                10 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/D6/count[1]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/D6/count[1]  (to circuit_clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay apple_module/D6/SLICE_23 to apple_module/D6/SLICE_23 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path apple_module/D6/SLICE_23 to apple_module/D6/SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R16C17D.CLK to     R16C17D.Q1 apple_module/D6/SLICE_23 (from circuit_clk)
    ROUTE         4     0.132     R16C17D.Q1 to R16C17D.A1     apple_module/D6/count[1]
    CTOF_DEL    ---     0.101     R16C17D.A1 to     R16C17D.F1 apple_module/D6/SLICE_23
    ROUTE         1     0.000     R16C17D.F1 to R16C17D.DI1    apple_module/D6/count_n1 (to circuit_clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/D6/SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R16C17D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/D6/SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R16C17D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/D15/count[2]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/D15/count[2]  (to circuit_clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay apple_module/D15/SLICE_22 to apple_module/D15/SLICE_22 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path apple_module/D15/SLICE_22 to apple_module/D15/SLICE_22:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R15C17A.CLK to     R15C17A.Q1 apple_module/D15/SLICE_22 (from circuit_clk)
    ROUTE         3     0.132     R15C17A.Q1 to R15C17A.A1     apple_module/D15/count[2]
    CTOF_DEL    ---     0.101     R15C17A.A1 to     R15C17A.F1 apple_module/D15/SLICE_22
    ROUTE         1     0.000     R15C17A.F1 to R15C17A.DI1    apple_module/D15/count_n2 (to circuit_clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/D15/SLICE_22:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R15C17A.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/D15/SLICE_22:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R15C17A.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/C13/states_ret  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/C13/states_ret  (to circuit_clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay apple_module/SLICE_48 to apple_module/SLICE_48 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path apple_module/SLICE_48 to apple_module/SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R16C15B.CLK to     R16C15B.Q0 apple_module/SLICE_48 (from circuit_clk)
    ROUTE        12     0.132     R16C15B.Q0 to R16C15B.A0     apple_module/states_ret_Q
    CTOF_DEL    ---     0.101     R16C15B.A0 to     R16C15B.F0 apple_module/SLICE_48
    ROUTE         1     0.000     R16C15B.F0 to R16C15B.DI0    apple_module/dot_rate_0_i (to circuit_clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R16C15B.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/SLICE_48:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R16C15B.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/D11/count[1]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/D11/count[1]  (to circuit_clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay apple_module/D11/SLICE_21 to apple_module/D11/SLICE_21 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path apple_module/D11/SLICE_21 to apple_module/D11/SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C19A.CLK to     R14C19A.Q1 apple_module/D11/SLICE_21 (from circuit_clk)
    ROUTE         4     0.132     R14C19A.Q1 to R14C19A.A1     apple_module/D11/count[1]
    CTOF_DEL    ---     0.101     R14C19A.A1 to     R14C19A.F1 apple_module/D11/SLICE_21
    ROUTE         1     0.000     R14C19A.F1 to R14C19A.DI1    apple_module/D11/count_5[1] (to circuit_clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/D11/SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R14C19A.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/D11/SLICE_21:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R14C19A.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/D9/count[3]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/D9/count[3]  (to circuit_clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay apple_module/D9/SLICE_34 to apple_module/D9/SLICE_34 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path apple_module/D9/SLICE_34 to apple_module/D9/SLICE_34:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C18D.CLK to     R14C18D.Q1 apple_module/D9/SLICE_34 (from circuit_clk)
    ROUTE         3     0.132     R14C18D.Q1 to R14C18D.A1     apple_module/count_0[3]
    CTOF_DEL    ---     0.101     R14C18D.A1 to     R14C18D.F1 apple_module/D9/SLICE_34
    ROUTE         1     0.000     R14C18D.F1 to R14C18D.DI1    apple_module/D9/N_39_i_i (to circuit_clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/D9/SLICE_34:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R14C18D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/D9/SLICE_34:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R14C18D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.379ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/D6/count[0]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/D6/count[0]  (to circuit_clk +)

       Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

     Constraint Details:

          0.366ns physical path delay apple_module/D6/SLICE_23 to apple_module/D6/SLICE_23 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.379ns

     Physical Path Details:

          Data path apple_module/D6/SLICE_23 to apple_module/D6/SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R16C17D.CLK to     R16C17D.Q0 apple_module/D6/SLICE_23 (from circuit_clk)
    ROUTE         5     0.132     R16C17D.Q0 to R16C17D.A0     apple_module/D6/count[0]
    CTOF_DEL    ---     0.101     R16C17D.A0 to     R16C17D.F0 apple_module/D6/SLICE_23
    ROUTE         1     0.000     R16C17D.F0 to R16C17D.DI0    apple_module/D6/count_n0 (to circuit_clk)
                      --------
                        0.366   (63.9% logic, 36.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/D6/SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R16C17D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/D6/SLICE_23:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R16C17D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.380ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/D7/count[3]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/D7/count[3]  (to circuit_clk +)

       Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

     Constraint Details:

          0.367ns physical path delay apple_module/D7/SLICE_42 to apple_module/D7/SLICE_42 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.380ns

     Physical Path Details:

          Data path apple_module/D7/SLICE_42 to apple_module/D7/SLICE_42:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R15C18B.CLK to     R15C18B.Q0 apple_module/D7/SLICE_42 (from circuit_clk)
    ROUTE        11     0.133     R15C18B.Q0 to R15C18B.A0     apple_module/horz_count_upper[3]
    CTOF_DEL    ---     0.101     R15C18B.A0 to     R15C18B.F0 apple_module/D7/SLICE_42
    ROUTE         1     0.000     R15C18B.F0 to R15C18B.DI0    apple_module/D7/count_n3 (to circuit_clk)
                      --------
                        0.367   (63.8% logic, 36.2% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/D7/SLICE_42:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R15C18B.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/D7/SLICE_42:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R15C18B.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.380ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/D9/count[2]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/D9/count[2]  (to circuit_clk +)

       Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

     Constraint Details:

          0.367ns physical path delay apple_module/D9/SLICE_34 to apple_module/D9/SLICE_34 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.380ns

     Physical Path Details:

          Data path apple_module/D9/SLICE_34 to apple_module/D9/SLICE_34:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C18D.CLK to     R14C18D.Q0 apple_module/D9/SLICE_34 (from circuit_clk)
    ROUTE         4     0.133     R14C18D.Q0 to R14C18D.A0     apple_module/count_0[2]
    CTOF_DEL    ---     0.101     R14C18D.A0 to     R14C18D.F0 apple_module/D9/SLICE_34
    ROUTE         1     0.000     R14C18D.F0 to R14C18D.DI0    apple_module/D9/N_44_i_i (to circuit_clk)
                      --------
                        0.367   (63.8% logic, 36.2% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/D9/SLICE_34:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R14C18D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/D9/SLICE_34:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R14C18D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.380ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/D7/count[0]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/D7/count[0]  (to circuit_clk +)

       Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

     Constraint Details:

          0.367ns physical path delay apple_module/D7/SLICE_41 to apple_module/D7/SLICE_41 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.380ns

     Physical Path Details:

          Data path apple_module/D7/SLICE_41 to apple_module/D7/SLICE_41:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R15C18D.CLK to     R15C18D.Q0 apple_module/D7/SLICE_41 (from circuit_clk)
    ROUTE         6     0.133     R15C18D.Q0 to R15C18D.A0     apple_module/horz_count_upper[0]
    CTOF_DEL    ---     0.101     R15C18D.A0 to     R15C18D.F0 apple_module/D7/SLICE_41
    ROUTE         1     0.000     R15C18D.F0 to R15C18D.DI0    apple_module/D7/N_12_i (to circuit_clk)
                      --------
                        0.367   (63.8% logic, 36.2% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/D7/SLICE_41:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/D7/SLICE_41:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    Passed: The following path meets requirements by 0.380ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/D11/count_0[3]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/D11/count_0[3]  (to circuit_clk +)

       Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

     Constraint Details:

          0.367ns physical path delay apple_module/D11/SLICE_35 to apple_module/D11/SLICE_35 meets
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
          0.000ns skew requirement (totaling -0.013ns) by 0.380ns

     Physical Path Details:

          Data path apple_module/D11/SLICE_35 to apple_module/D11/SLICE_35:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C19D.CLK to     R14C19D.Q0 apple_module/D11/SLICE_35 (from circuit_clk)
    ROUTE         8     0.133     R14C19D.Q0 to R14C19D.A0     apple_module/count_i[3]
    CTOF_DEL    ---     0.101     R14C19D.A0 to     R14C19D.F0 apple_module/D11/SLICE_35
    ROUTE         1     0.000     R14C19D.F0 to R14C19D.DI0    apple_module/D11/count_5_0_0[3] (to circuit_clk)
                      --------
                        0.367   (63.8% logic, 36.2% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path clock_module/PLLInst_0 to apple_module/D11/SLICE_35:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R14C19D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

          Destination Clock Path clock_module/PLLInst_0 to apple_module/D11/SLICE_35:

       Name    Fanout   Delay (ns)          Site               Resource
    ROUTE        26     0.707     RPLL.CLKOS to R14C19D.CLK    circuit_clk
                      --------
                        0.707   (0.0% logic, 100.0% route), 0 logic levels.

    ================================================================================
    Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
                10 items scored, 10 timing errors detected.
    --------------------------------------------------------------------------------

    Error: The following path exceeds requirements by 2.665ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/C13/states[3]  (from circuit_clk +)
       Destination:    FF         Data in        apple_module/C7/states[2]  (to apple_module/mem0 -)

       Delay:               0.375ns  (62.4% logic, 37.6% route), 2 logic levels.

     Constraint Details:

          0.375ns physical path delay apple_module/SLICE_47 to apple_module/SLICE_46 exceeds
          (delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
         -0.013ns DIN_HLD and
          0.000ns delay constraint less
         -3.053ns skew less
          0.000ns feedback compensation requirement (totaling 3.040ns) by 2.665ns

     Physical Path Details:

          Data path apple_module/SLICE_47 to apple_module/SLICE_46:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C14B.CLK to     R14C14B.Q1 apple_module/SLICE_47 (from circuit_clk)
    ROUTE         9     0.141     R14C14B.Q1 to R14C14C.D0     apple_module/states[3]
    CTOF_DEL    ---     0.101     R14C14C.D0 to     R14C14C.F0 apple_module/SLICE_46
    ROUTE         1     0.000     R14C14C.F0 to R14C14C.DI0    apple_module/C7/accept_char_i (to apple_module/mem0)
                      --------
                        0.375   (62.4% logic, 37.6% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_47:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C14B.CLK    circuit_clk
                      --------
                        1.420   (31.6% logic, 68.4% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/SLICE_46:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.348      R2C19C.F0 to R14C14C.CLK    apple_module/mem0
                      --------
                        4.473   (21.4% logic, 78.6% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Error: The following path exceeds requirements by 2.460ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/C13/states[3]  (from circuit_clk +)
       Destination:    DP8KC      Port           apple_module/ScreenBuffer/sram_1_0_0_0(ASIC)  (to apple_module/mem0 -)

       Delay:               0.698ns  (33.5% logic, 66.5% route), 2 logic levels.

     Constraint Details:

          0.698ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
          (delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
          0.051ns DATA_HLD and
          0.000ns delay constraint less
         -3.107ns skew less
          0.000ns feedback compensation requirement (totaling 3.158ns) by 2.460ns

     Physical Path Details:

          Data path apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C14B.CLK to     R14C14B.Q1 apple_module/SLICE_47 (from circuit_clk)
    ROUTE         9     0.144     R14C14B.Q1 to R14C14D.C0     apple_module/states[3]
    CTOF_DEL    ---     0.101     R14C14D.C0 to     R14C14D.F0 apple_module/SLICE_53
    ROUTE         2     0.320     R14C14D.F0 to EBR_R13C10.DIA5 apple_module/un1_a_1[0] (to apple_module/mem0)
                      --------
                        0.698   (33.5% logic, 66.5% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_47:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C14B.CLK    circuit_clk
                      --------
                        1.420   (31.6% logic, 68.4% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.402      R2C19C.F0 to EBR_R13C10.CLKA apple_module/mem0
                      --------
                        4.527   (21.1% logic, 78.9% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Error: The following path exceeds requirements by 2.305ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/C13/states[3]  (from circuit_clk +)
       Destination:    DP8KC      Port           apple_module/ScreenBuffer/sram_1_0_0_0(ASIC)  (to apple_module/mem0 -)

       Delay:               0.853ns  (27.4% logic, 72.6% route), 2 logic levels.

     Constraint Details:

          0.853ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
          (delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
          0.051ns DATA_HLD and
          0.000ns delay constraint less
         -3.107ns skew less
          0.000ns feedback compensation requirement (totaling 3.158ns) by 2.305ns

     Physical Path Details:

          Data path apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C14B.CLK to     R14C14B.Q1 apple_module/SLICE_47 (from circuit_clk)
    ROUTE         9     0.266     R14C14B.Q1 to R14C15D.D0     apple_module/states[3]
    CTOF_DEL    ---     0.101     R14C15D.D0 to     R14C15D.F0 apple_module/SLICE_55
    ROUTE         2     0.353     R14C15D.F0 to EBR_R13C10.DIA3 apple_module/buffer_char_in[3] (to apple_module/mem0)
                      --------
                        0.853   (27.4% logic, 72.6% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_47:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C14B.CLK    circuit_clk
                      --------
                        1.420   (31.6% logic, 68.4% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.402      R2C19C.F0 to EBR_R13C10.CLKA apple_module/mem0
                      --------
                        4.527   (21.1% logic, 78.9% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Error: The following path exceeds requirements by 2.257ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/C13/states[3]  (from circuit_clk +)
       Destination:    DP8KC      Port           apple_module/ScreenBuffer/sram_1_0_0_0(ASIC)  (to apple_module/mem0 -)

       Delay:               0.901ns  (26.0% logic, 74.0% route), 2 logic levels.

     Constraint Details:

          0.901ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
          (delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
          0.051ns DATA_HLD and
          0.000ns delay constraint less
         -3.107ns skew less
          0.000ns feedback compensation requirement (totaling 3.158ns) by 2.257ns

     Physical Path Details:

          Data path apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C14B.CLK to     R14C14B.Q1 apple_module/SLICE_47 (from circuit_clk)
    ROUTE         9     0.234     R14C14B.Q1 to R14C15A.B0     apple_module/states[3]
    CTOF_DEL    ---     0.101     R14C15A.B0 to     R14C15A.F0 apple_module/SLICE_54
    ROUTE         2     0.433     R14C15A.F0 to EBR_R13C10.DIA4 apple_module/un1_a_3[0] (to apple_module/mem0)
                      --------
                        0.901   (26.0% logic, 74.0% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_47:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C14B.CLK    circuit_clk
                      --------
                        1.420   (31.6% logic, 68.4% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.402      R2C19C.F0 to EBR_R13C10.CLKA apple_module/mem0
                      --------
                        4.527   (21.1% logic, 78.9% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Error: The following path exceeds requirements by 2.225ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/C13/states[3]  (from circuit_clk +)
       Destination:    DP8KC      Port           apple_module/ScreenBuffer/sram_1_0_0_0(ASIC)  (to apple_module/mem0 -)

       Delay:               0.933ns  (25.1% logic, 74.9% route), 2 logic levels.

     Constraint Details:

          0.933ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
          (delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
          0.051ns DATA_HLD and
          0.000ns delay constraint less
         -3.107ns skew less
          0.000ns feedback compensation requirement (totaling 3.158ns) by 2.225ns

     Physical Path Details:

          Data path apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C14B.CLK to     R14C14B.Q1 apple_module/SLICE_47 (from circuit_clk)
    ROUTE         9     0.266     R14C14B.Q1 to R14C15C.D0     apple_module/states[3]
    CTOF_DEL    ---     0.101     R14C15C.D0 to     R14C15C.F0 apple_module/SLICE_58
    ROUTE         2     0.433     R14C15C.F0 to EBR_R13C10.DIA0 apple_module/buffer_char_in[0] (to apple_module/mem0)
                      --------
                        0.933   (25.1% logic, 74.9% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_47:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C14B.CLK    circuit_clk
                      --------
                        1.420   (31.6% logic, 68.4% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.402      R2C19C.F0 to EBR_R13C10.CLKA apple_module/mem0
                      --------
                        4.527   (21.1% logic, 78.9% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Error: The following path exceeds requirements by 2.201ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/C13/states[2]  (from circuit_clk +)
       Destination:    DP8KC      Port           apple_module/CursorBuffer/sram_1_0_0_0(ASIC)  (to apple_module/mem0 -)

       Delay:               0.957ns  (24.5% logic, 75.5% route), 2 logic levels.

     Constraint Details:

          0.957ns physical path delay apple_module/SLICE_47 to apple_module/CursorBuffer/sram_1_0_0_0 exceeds
          (delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
          0.051ns DATA_HLD and
          0.000ns delay constraint less
         -3.107ns skew less
          0.000ns feedback compensation requirement (totaling 3.158ns) by 2.201ns

     Physical Path Details:

          Data path apple_module/SLICE_47 to apple_module/CursorBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C14B.CLK to     R14C14B.Q0 apple_module/SLICE_47 (from circuit_clk)
    ROUTE         1     0.222     R14C14B.Q0 to R14C14C.B1     apple_module/states[2]
    CTOF_DEL    ---     0.101     R14C14C.B1 to     R14C14C.F1 apple_module/SLICE_46
    ROUTE         1     0.501     R14C14C.F1 to EBR_R20C10.DIA1 apple_module/mem_curs_in[0] (to apple_module/mem0)
                      --------
                        0.957   (24.5% logic, 75.5% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_47:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C14B.CLK    circuit_clk
                      --------
                        1.420   (31.6% logic, 68.4% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/CursorBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.402      R2C19C.F0 to EBR_R20C10.CLKA apple_module/mem0
                      --------
                        4.527   (21.1% logic, 78.9% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Error: The following path exceeds requirements by 2.201ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/C13/states[3]  (from circuit_clk +)
       Destination:    DP8KC      Port           apple_module/ScreenBuffer/sram_1_0_0_0(ASIC)  (to apple_module/mem0 -)

       Delay:               0.957ns  (24.5% logic, 75.5% route), 2 logic levels.

     Constraint Details:

          0.957ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
          (delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
          0.051ns DATA_HLD and
          0.000ns delay constraint less
         -3.107ns skew less
          0.000ns feedback compensation requirement (totaling 3.158ns) by 2.201ns

     Physical Path Details:

          Data path apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C14B.CLK to     R14C14B.Q1 apple_module/SLICE_47 (from circuit_clk)
    ROUTE         9     0.266     R14C14B.Q1 to R14C15B.D0     apple_module/states[3]
    CTOF_DEL    ---     0.101     R14C15B.D0 to     R14C15B.F0 apple_module/SLICE_56
    ROUTE         2     0.457     R14C15B.F0 to EBR_R13C10.DIA2 apple_module/buffer_char_in[2] (to apple_module/mem0)
                      --------
                        0.957   (24.5% logic, 75.5% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_47:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C14B.CLK    circuit_clk
                      --------
                        1.420   (31.6% logic, 68.4% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.402      R2C19C.F0 to EBR_R13C10.CLKA apple_module/mem0
                      --------
                        4.527   (21.1% logic, 78.9% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Error: The following path exceeds requirements by 2.178ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/C13/states[3]  (from circuit_clk +)
       Destination:    DP8KC      Port           apple_module/ScreenBuffer/sram_1_0_0_0(ASIC)  (to apple_module/mem0 -)

       Delay:               0.980ns  (23.9% logic, 76.1% route), 2 logic levels.

     Constraint Details:

          0.980ns physical path delay apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
          (delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
          0.051ns DATA_HLD and
          0.000ns delay constraint less
         -3.107ns skew less
          0.000ns feedback compensation requirement (totaling 3.158ns) by 2.178ns

     Physical Path Details:

          Data path apple_module/SLICE_47 to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R14C14B.CLK to     R14C14B.Q1 apple_module/SLICE_47 (from circuit_clk)
    ROUTE         9     0.393     R14C14B.Q1 to R14C14A.D0     apple_module/states[3]
    CTOF_DEL    ---     0.101     R14C14A.D0 to     R14C14A.F0 apple_module/SLICE_57
    ROUTE         2     0.353     R14C14A.F0 to EBR_R13C10.DIA1 apple_module/buffer_char_in[1] (to apple_module/mem0)
                      --------
                        0.980   (23.9% logic, 76.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_47:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C14B.CLK    circuit_clk
                      --------
                        1.420   (31.6% logic, 68.4% route), 2 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.402      R2C19C.F0 to EBR_R13C10.CLKA apple_module/mem0
                      --------
                        4.527   (21.1% logic, 78.9% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Error: The following path exceeds requirements by 0.719ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/rd[7]  (from apple_module/y2_1 -)
       Destination:    DP8KC      Port           apple_module/ScreenBuffer/sram_1_0_0_0(ASIC)  (to apple_module/mem0 -)

       Delay:               0.808ns  (29.0% logic, 71.0% route), 2 logic levels.

     Constraint Details:

          0.808ns physical path delay apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
          0.051ns DATA_HLD and
          0.000ns delay constraint less
         -1.476ns skew less
          0.000ns feedback compensation requirement (totaling 1.527ns) by 0.719ns

     Physical Path Details:

          Data path apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R15C15B.CLK to     R15C15B.Q1 apple_module/SLICE_45 (from apple_module/y2_1)
    ROUTE         1     0.254     R15C15B.Q1 to R14C14D.D0     apple_module/rd[7]
    CTOF_DEL    ---     0.101     R14C14D.D0 to     R14C14D.F0 apple_module/SLICE_53
    ROUTE         2     0.320     R14C14D.F0 to EBR_R13C10.DIA5 apple_module/un1_a_1[0] (to apple_module/mem0)
                      --------
                        0.808   (29.0% logic, 71.0% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_45:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R14C18D.CLK to     R14C18D.Q1 apple_module/D9/SLICE_34
    ROUTE         3     0.269     R14C18D.Q1 to R14C18C.C1     apple_module/count_0[3]
    CTOF_DEL    ---     0.177     R14C18C.C1 to     R14C18C.F1 apple_module/D1/SLICE_52
    ROUTE        16     1.031     R14C18C.F1 to R15C15B.CLK    apple_module/y2_1
                      --------
                        3.051   (25.6% logic, 74.4% route), 4 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.402      R2C19C.F0 to EBR_R13C10.CLKA apple_module/mem0
                      --------
                        4.527   (21.1% logic, 78.9% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Error: The following path exceeds requirements by 0.689ns

     Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

       Source:         FF         Q              apple_module/rd[5]  (from apple_module/y2_1 -)
       Destination:    DP8KC      Port           apple_module/ScreenBuffer/sram_1_0_0_0(ASIC)  (to apple_module/mem0 -)

       Delay:               0.838ns  (27.9% logic, 72.1% route), 2 logic levels.

     Constraint Details:

          0.838ns physical path delay apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0 exceeds
          0.051ns DATA_HLD and
          0.000ns delay constraint less
         -1.476ns skew less
          0.000ns feedback compensation requirement (totaling 1.527ns) by 0.689ns

     Physical Path Details:

          Data path apple_module/SLICE_45 to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.133    R15C15B.CLK to     R15C15B.Q0 apple_module/SLICE_45 (from apple_module/y2_1)
    ROUTE         1     0.171     R15C15B.Q0 to R14C15A.D0     apple_module/rd[5]
    CTOF_DEL    ---     0.101     R14C15A.D0 to     R14C15A.F0 apple_module/SLICE_54
    ROUTE         2     0.433     R14C15A.F0 to EBR_R13C10.DIA4 apple_module/un1_a_3[0] (to apple_module/mem0)
                      --------
                        0.838   (27.9% logic, 72.1% route), 2 logic levels.

     Clock Skew Details:

          Source Clock Path sys_clock to apple_module/SLICE_45:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R14C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R14C18D.CLK to     R14C18D.Q1 apple_module/D9/SLICE_34
    ROUTE         3     0.269     R14C18D.Q1 to R14C18C.C1     apple_module/count_0[3]
    CTOF_DEL    ---     0.177     R14C18C.C1 to     R14C18C.F1 apple_module/D1/SLICE_52
    ROUTE        16     1.031     R14C18C.F1 to R15C15B.CLK    apple_module/y2_1
                      --------
                        3.051   (25.6% logic, 74.4% route), 4 logic levels.

          Source Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

          Destination Clock Path sys_clock to apple_module/ScreenBuffer/sram_1_0_0_0:

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.449        126.PAD to      126.PADDI sys_clock
    ROUTE         1     0.264      126.PADDI to RPLL.CLKI      sys_clock_c
    CLKI2OS_DE  ---     0.000      RPLL.CLKI to     RPLL.CLKOS clock_module/PLLInst_0
    ROUTE        26     0.707     RPLL.CLKOS to R15C18D.CLK    circuit_clk
    REG_DEL     ---     0.154    R15C18D.CLK to     R15C18D.Q1 apple_module/D7/SLICE_41
    ROUTE         7     0.432     R15C18D.Q1 to R14C19C.A1     apple_module/horz_count_upper[2]
    CTOF_DEL    ---     0.177     R14C19C.A1 to     R14C19C.F1 apple_module/SLICE_26
    ROUTE         5     0.765     R14C19C.F1 to R2C19C.B0      apple_module/line_clock
    CTOF_DEL    ---     0.177      R2C19C.B0 to      R2C19C.F0 apple_module/SLICE_64
    ROUTE        14     1.402      R2C19C.F0 to EBR_R13C10.CLKA apple_module/mem0
                      --------
                        4.527   (21.1% logic, 78.9% route), 5 logic levels.

          Destination Clock f/b:

       Name    Fanout   Delay (ns)          Site               Resource
    CLKFB2IFB_  ---     0.000     RPLL.CLKFB to  RPLL.CLKINTFB clock_module/PLLInst_0
    ROUTE         1     0.000  RPLL.CLKINTFB to RPLL.CLKFB     clock_module/CLKFB_t
                      --------
                        0.000   (0.0% logic, 0.0% route), 1 logic levels.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference(MIN Delays)                  |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY NET "sys_clock_c" 25.000000   |             |             |
    MHz ;                                   |            -|            -|   0
                                            |             |             |
    FREQUENCY NET "circuit_clk" 14.285714   |             |             |
    MHz ;                                   |     0.000 ns|     0.379 ns|   2
                                            |             |             |
    FREQUENCY PORT "sys_clock" 25.000000    |             |             |
    MHz ;                                   |            -|            -|   2 *
                                            |             |             |
    ----------------------------------------------------------------------------

    1 preference(marked by "*" above) not met.

    ----------------------------------------------------------------------------
    Critical Nets                           |   Loads|  Errors| % of total
    ----------------------------------------------------------------------------
    apple_module/states[3]                  |       9|       7|     70.00%
                                            |        |        |
    apple_module/un1_a_3[0]                 |       2|       2|     20.00%
                                            |        |        |
    apple_module/un1_a_1[0]                 |       2|       2|     20.00%
                                            |        |        |
    ----------------------------------------------------------------------------

    Clock Domains Analysis
    ------------------------

    Found 8 clocks:

    Clock Domain: apple_module/un1_rda_1   Source: apple_module/SLICE_68.F1   Loads: 1
       Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;

       Data transfers from:
       Clock Domain: apple_module/mem0   Source: apple_module/SLICE_64.F0
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 27

       Clock Domain: apple_module/mem0   Source: apple_module/SLICE_64.F0
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 2

       Clock Domain: apple_module/y2_1   Source: apple_module/D1/SLICE_52.F1
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 1

       Clock Domain: circuit_clk   Source: clock_module/PLLInst_0.CLKOS
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 2

    Clock Domain: apple_module/y2_1   Source: apple_module/D1/SLICE_52.F1   Loads: 16
       No transfer within this clock domain is found

    Clock Domain: apple_module/un1_rda_1   Source: apple_module/SLICE_68.F1   Loads: 1
       Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;

       Data transfers from:
       Clock Domain: apple_module/y2_1   Source: apple_module/D1/SLICE_52.F1
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 2

       Clock Domain: apple_module/y2_1   Source: apple_module/D1/SLICE_52.F1
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 2

       Clock Domain: apple_module/y2_1   Source: apple_module/D1/SLICE_52.F1
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 2

    Clock Domain: apple_module/y2_1   Source: apple_module/D1/SLICE_52.F1   Loads: 16
       Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;

       Data transfers from:
       Clock Domain: apple_module/mem0   Source: apple_module/SLICE_64.F0
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 9

       Clock Domain: apple_module/mem0   Source: apple_module/SLICE_64.F0
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 8

       Clock Domain: apple_module/line_clock   Source: apple_module/SLICE_26.F1
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 2

       Clock Domain: circuit_clk   Source: clock_module/PLLInst_0.CLKOS
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 5

    Clock Domain: apple_module/line_clock   Source: apple_module/SLICE_26.F1   Loads: 5
       No transfer within this clock domain is found

    Clock Domain: apple_module/y2_1   Source: apple_module/D1/SLICE_52.F1   Loads: 16
       No transfer within this clock domain is found

       Data transfers from:
       Clock Domain: apple_module/un1_rda_1   Source: apple_module/SLICE_68.F1
          Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ;   Transfers: 1

    Clock Domain: circuit_clk   Source: clock_module/PLLInst_0.CLKOS   Loads: 26
       Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;

       Data transfers from:
       Clock Domain: apple_module/line_clock   Source: apple_module/SLICE_26.F1
          Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;   Transfers: 6

       Clock Domain: apple_module/mem0   Source: apple_module/SLICE_64.F0
          Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;   Transfers: 1

       Clock Domain: apple_module/mem0   Source: apple_module/SLICE_64.F0
          Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;   Transfers: 1

    Clock Domain: sys_clock_c   Source: sys_clock.PAD   Loads: 1
       No transfer within this clock domain is found

    Timing summary (Hold):
    ---------------

    Timing errors: 10  Score: 19900
    Cumulative negative slack: 19900

    Constraints cover 786 paths, 10 nets, and 594 connections (98.84% coverage)

    Timing summary (Setup and Hold):
    ---------------

    Timing errors: 7 (setup), 10 (hold)
    Score: 76216 (setup), 19900 (hold)
    Cumulative negative slack: 96116 (76216+19900)