#--  Synopsys, Inc.
#--  Version M-2017.03L-SP1-1
#--  Project file C:\Dev\Apple1Display\impl1\run_options.txt
#--  Written on Thu Aug  8 18:40:09 2019


#project files
add_file -vhdl -lib work "C:/lscc/diamond/3.10_x64/cae_library/synthesis/vhdl/machxo2.vhd"
add_file -vhdl -lib work "source/FleaFPGA_Uno_Top.vhd"
add_file -vhdl -lib work "Apple1Display.vhd"
add_file -vhdl -lib work "source/ntsc.vhd"
add_file -vhdl -lib work "divider.vhd"
add_file -vhdl -lib work "master_clk.vhd"
add_file -vhdl -lib work "../ttl/dm7400.vhd"
add_file -vhdl -lib work "../ttl/dm7402.vhd"
add_file -vhdl -lib work "../ttl/dm7404.vhd"
add_file -vhdl -lib work "../ttl/dm7408.vhd"
add_file -vhdl -lib work "../ttl/dm7410.vhd"
add_file -vhdl -lib work "../ttl/dm7427.vhd"
add_file -vhdl -lib work "../ttl/dm7432.vhd"
add_file -vhdl -lib work "../ttl/dm7450.vhd"
add_file -vhdl -lib work "../ttl/dm74157.vhd"
add_file -vhdl -lib work "../ttl/dm74160.vhd"
add_file -vhdl -lib work "../ttl/dm74161.vhd"
add_file -vhdl -lib work "../ttl/dm74166.vhd"
add_file -vhdl -lib work "../ttl/dm74174.vhd"
add_file -vhdl -lib work "../ttl/dm74175.vhd"
add_file -vhdl -lib work "../ttl/2504.vhd"
add_file -vhdl -lib work "../ttl/2519.vhd"
add_file -vhdl -lib work "../ttl/dm2513.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/CharacterRom.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/ScreenRom.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/ShiftReg40.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/test_entity.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/ShiftReg1024.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/ScreenRom2.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/ScreenRam.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/CursorRam.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/UART_RX.vhd"
add_file -vhdl -lib work "../ttl/ne555.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/sig2504.vhd"
add_file -vhdl -lib work "C:/Dev/Apple1Display/sig2513.vhd"



#implementation: "impl1"
impl -add impl1 -type fpga

#
#implementation attributes

set_option -vlog_std sysv
set_option -project_relative_includes 1

#device options
set_option -technology MACHXO2
set_option -part LCMXO2_7000HC
set_option -package TG144C
set_option -speed_grade -4
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "FleaFPGA_Uno_E1"

# hdl_compiler_options
set_option -distributed_compile 0

# mapper_without_write_options
set_option -frequency auto
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# Lattice XP
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr no
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
set_option -syn_edif_array_rename 1
set_option -Write_declared_clocks_only 1

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./impl1.edi"
impl -active "impl1"
