@W: BN287 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Register states[3:0] with reset has an initial value of 1. Ignoring initial value.  
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: BN287 :"c:\dev\apple1display\ttl\dm74174.vhd":34:2:34:3|Register states[5:0] with reset has an initial value of 1. Ignoring initial value.  
@W: MT529 :"c:\dev\apple1display\uart_rx.vhd":37:36:37:38|Found inferred clock FleaFPGA_Uno_E1|sys_clock which controls 57 sequential elements including uart_module.r_RX_Data. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Found inferred clock master_clk|CLKOS_inferred_clock which controls 6 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Found inferred clock dm7400_1|y3_inferred_clock which controls 44 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"c:\dev\apple1display\sig2504.vhd":187:4:187:15|Found inferred clock dm7427|y1_inferred_clock which controls 83 sequential elements including apple_module.D5a.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"c:\dev\apple1display\shiftreg40.vhd":186:4:186:15|Found inferred clock dm7400_1|y1_inferred_clock which controls 7 sequential elements including apple_module.C3.LineBuffer.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Found inferred clock dm74175|q0_i_inferred_clock which controls 13 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
