@W: MT453 |clock period is too long for clock dm7400_1|y3_inferred_clock, changing period from 40622.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 20311.0 ns to 10000.0 ns. 
@W: MT453 |clock period is too long for clock dm7427|y1_inferred_clock, changing period from 40622.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 20311.0 ns to 10000.0 ns. 
@W: MT453 |clock period is too long for clock dm7400_1|y1_inferred_clock, changing period from 40622.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 20311.0 ns to 10000.0 ns. 
@W: MT246 :"c:\dev\apple1display\impl1\master_clk.vhd":109:4:109:12|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock FleaFPGA_Uno_E1|sys_clock with period 6.27ns. Please declare a user-defined clock on object "p:sys_clock"
@W: MT420 |Found inferred clock dm7427|y1_inferred_clock with period 3.42ns. Please declare a user-defined clock on object "n:apple_module.C5.y1"
@W: MT420 |Found inferred clock dm7400_1|y1_inferred_clock with period 6.07ns. Please declare a user-defined clock on object "n:apple_module.D10.y1"
@W: MT420 |Found inferred clock dm7400_1|y3_inferred_clock with period 3.18ns. Please declare a user-defined clock on object "n:apple_module.D10.y3"
