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    # Thu Aug  8 18:33:50 2019

    Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 11:10:16
    Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
    Product Version M-2017.03L-SP1-1

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    @A:MF827 :  | No constraint file specified.
    Linked File: impl1_scck.rpt
    Printing clock  summary report in "C:\Dev\Apple1Display\impl1\impl1_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)

    @W:BN287 : dm74175.vhd(29) | Register states[3:0] with reset has an initial value of 1. Ignoring initial value.
    @W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
    @W:BN287 : dm74174.vhd(34) | Register states[5:0] with reset has an initial value of 1. Ignoring initial value.
    @N:BN362 : uart_rx.vhd(62) | Removing sequential instance r_RX_Byte[7] (in view: work.UART_RX(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    ICG Latch Removal Summary:
    Number of ICG latches removed:	0
    Number of ICG latches not removed:	0
    syn_allowed_resources : blockrams=26  set on top level netlist FleaFPGA_Uno_E1

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

    Clock Summary
    ******************

              Start                                  Requested     Requested     Clock                                          Clock                     Clock
    Level     Clock                                  Frequency     Period        Type                                           Group                     Load
    -----------------------------------------------------------------------------------------------------------------------------------------------------------
    0 -       System                                 1.0 MHz       1000.000      system                                         system_clkgroup           0

    0 -       dm7427|y1_inferred_clock               259.2 MHz     3.858         inferred                                       Autoconstr_clkgroup_3     83

    0 -       FleaFPGA_Uno_E1|sys_clock              236.1 MHz     4.236         inferred                                       Autoconstr_clkgroup_0     57

    0 -       dm7400_1|y3_inferred_clock             483.5 MHz     2.068         inferred                                       Autoconstr_clkgroup_2     44

    0 -       dm74175|q0_i_inferred_clock            1.0 MHz       1000.000      inferred                                       Autoconstr_clkgroup_5     13
    1 .         dm74161_4|count_derived_clock[3]     1.0 MHz       1000.000      derived (from dm74175|q0_i_inferred_clock)     Autoconstr_clkgroup_5     21

    0 -       dm7400_1|y1_inferred_clock             329.3 MHz     3.037         inferred                                       Autoconstr_clkgroup_4     7

    0 -       master_clk|CLKOS_inferred_clock        285.4 MHz     3.504         inferred                                       Autoconstr_clkgroup_1     6
    ===========================================================================================================================================================

    @W:MT529 : uart_rx.vhd(37) | Found inferred clock FleaFPGA_Uno_E1|sys_clock which controls 57 sequential elements including uart_module.r_RX_Data. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
    @W:MT529 : dm74175.vhd(29) | Found inferred clock master_clk|CLKOS_inferred_clock which controls 6 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
    @W:MT529 : dm74175.vhd(29) | Found inferred clock dm7400_1|y3_inferred_clock which controls 44 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
    @W:MT529 : sig2504.vhd(187) | Found inferred clock dm7427|y1_inferred_clock which controls 83 sequential elements including apple_module.ScreenBuffer0.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
    @W:MT529 : shiftreg40.vhd(186) | Found inferred clock dm7400_1|y1_inferred_clock which controls 7 sequential elements including apple_module.C3.LineBuffer.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
    @W:MT529 : dm74175.vhd(29) | Found inferred clock dm74175|q0_i_inferred_clock which controls 13 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.

    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

    Encoding state machine r_SM_Main[0:4] (in view: work.UART_RX(rtl))
    original code -> new code
       00001 -> 000
       00010 -> 001
       00100 -> 010
       01000 -> 011
       10000 -> 100

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)

    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Aug  8 18:33:51 2019

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