    PAR: Place And Route Diamond (64-bit) 3.10.2.115.
    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
    Thu Aug 08 18:39:21 2019

    C:/lscc/diamond/3.10_x64/ispfpga\bin\nt64\par -f Apple1Display_impl1.p2t
    Apple1Display_impl1_map.ncd Apple1Display_impl1.dir Apple1Display_impl1.prf
    -gui -msgset C:/Dev/Apple1Display/promote.xml

    Preference file: Apple1Display_impl1.prf.

    Cost Table Summary
    Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
    Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
    ----------   --------     -----        ------       -----------  -----------  ----         ------
    5_1   *      0            -67.249      8347443      -3.228       79282        17           Success

    * : Design saved.

    Total (real) run time for 1-seed: 17 secs

    par done!

    Lattice Place and Route Report for Design "Apple1Display_impl1_map.ncd"
    Thu Aug 08 18:39:21 2019

    Best Par Run
    PAR: Place And Route Diamond (64-bit) 3.10.2.115.
    Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Dev/Apple1Display/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF Apple1Display_impl1_map.ncd Apple1Display_impl1.dir/5_1.ncd Apple1Display_impl1.prf
    Preference file: Apple1Display_impl1.prf.
    Placement level-cost: 5-1.
    Routing Iterations: 6

    Loading design for application par from file Apple1Display_impl1_map.ncd.
    Design name: FleaFPGA_Uno_E1
    NCD version: 3.3
    Vendor:      LATTICE
    Device:      LCMXO2-7000HC
    Package:     TQFP144
    Performance: 4
    Loading device for application par from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.10_x64/ispfpga.
    Package Status:                     Final          Version 1.39.
    Performance Hardware Data Status:   Final          Version 34.4.
    License checked out.

    Ignore Preference Error(s):  True

    Device utilization summary:

       PIO (prelim)   15+4(JTAG)/336     6% used
                      15+4(JTAG)/115     17% bonded
       IOLOGIC            1/336          <1% used

       SLICE            153/3432          4% used

       GSR                1/1           100% used
       EBR                9/26           34% used
       PLL                1/2            50% used

    INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
    INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
    Number of Signals: 528
    Number of Connections: 1242

    Pin Constraint Summary:
       13 out of 15 pins locked (86% locked).

    WARNING - par: RPLL must be put in reset state during background Flash programming. System design must take this into consideration when PLL is used during background Flash programming. Please see TN1204 MachXO2 Programming and Configuration Usage Guide for detailed information.
    The following 3 signals are selected to use the primary clock routing resources:
        circuit_clk (driver: clock_module/PLLInst_0, clk load #: 24)
        apple_module/C5/y1 (driver: apple_module/SLICE_127, clk load #: 47)
        sys_clock_c (driver: sys_clock, clk load #: 38)

    The following 1 signal is selected to use the secondary clock routing resources:
        un1_flash_countlt22 (driver: SLICE_122, clk load #: 0, sr load #: 4, ce load #: 11)

    Signal apple_module/horz_count_upper[3] is selected as Global Set/Reset.
    .
    Starting Placer Phase 0.
    ............
    Finished Placer Phase 0.  REAL time: 2 secs

    Starting Placer Phase 1.
    ...................
    Placer score = 67613.
    Finished Placer Phase 1.  REAL time: 8 secs

    Starting Placer Phase 2.
    .
    Placer score =  67327
    Finished Placer Phase 2.  REAL time: 8 secs

    Clock Report

    Global Clock Resources:
      CLK_PIN    : 1 out of 8 (12%)
      PLL        : 1 out of 2 (50%)
      DCM        : 0 out of 2 (0%)
      DCC        : 0 out of 8 (0%)

    Quadrants All (TL, TR, BL, BR) - Global Clocks:
      PRIMARY "circuit_clk" from CLKOS on comp "clock_module/PLLInst_0" on PLL site "RPLL", clk load = 24
      PRIMARY "apple_module/C5/y1" from F0 on comp "apple_module/SLICE_127" on site "R2C19D", clk load = 47
      PRIMARY "sys_clock_c" from comp "sys_clock" on CLK_PIN site "126 (PT22C)", clk load = 38
      SECONDARY "un1_flash_countlt22" from F1 on comp "SLICE_122" on site "R21C21B", clk load = 0, ce load = 11, sr load = 4

      PRIMARY  : 3 out of 8 (37%)
      SECONDARY: 1 out of 8 (12%)

    Edge Clocks:
      No edge clock selected.

    I/O Usage Summary (final):
       15 + 4(JTAG) out of 336 (5.7%) PIO sites used.
       15 + 4(JTAG) out of 115 (16.5%) bonded PIO sites used.
       Number of PIO comps: 15; differential: 0.
       Number of Vref pins used: 0.

    I/O Bank Usage Summary:
    +----------+---------------+------------+-----------+
    | I/O Bank | Usage         | Bank Vccio | Bank Vref |
    +----------+---------------+------------+-----------+
    | 0        | 4 / 28 ( 14%) | 3.3V       | -         |
    | 1        | 2 / 29 (  6%) | 3.3V       | -         |
    | 2        | 1 / 29 (  3%) | 2.5V       | -         |
    | 3        | 3 / 9 ( 33%)  | 3.3V       | -         |
    | 4        | 2 / 10 ( 20%) | 2.5V       | -         |
    | 5        | 3 / 10 ( 30%) | 3.3V       | -         |
    +----------+---------------+------------+-----------+

    Total placer CPU time: 7 secs

    Dumping design to file Apple1Display_impl1.dir/5_1.ncd.

    0 connections routed; 1242 unrouted.
    Starting router resource preassignment

    WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
       Signal=apple_module/D10/y3 loads=4 clock_loads=4
       Signal=apple_module/D10/y1 loads=4 clock_loads=4

    Completed router resource preassignment. Real time: 10 secs

    Start NBR router at 18:39:31 08/08/19

    *****************************************************************
    Info: NBR allows conflicts(one node used by more than one signal)
          in the earlier iterations. In each iteration, it tries to
          solve the conflicts while keeping the critical connections
          routed as short as possible. The routing process is said to
          be completed when no conflicts exist and all connections
          are routed.
    Note: NBR uses a different method to calculate timing slacks. The
          worst slack and total negative slack may not be the same as
          that in TRCE report. You should always run TRCE to verify
          your design.
    *****************************************************************

    Start NBR special constraint process at 18:39:31 08/08/19

    Start NBR section for initial routing at 18:39:32 08/08/19
    Level 1, iteration 1
    8(0.00%) conflicts; 853(68.68%) untouched conns; 3047471 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -64.043ns/-3047.471ns; real time: 11 secs
    Level 2, iteration 1
    3(0.00%) conflicts; 852(68.60%) untouched conns; 3049688 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -64.050ns/-3049.688ns; real time: 11 secs
    Level 3, iteration 1
    1(0.00%) conflict; 852(68.60%) untouched conns; 3070265 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -64.519ns/-3070.265ns; real time: 11 secs
    Level 4, iteration 1
    15(0.00%) conflicts; 0(0.00%) untouched conn; 3111371 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -65.450ns/-3111.372ns; real time: 12 secs

    Info: Initial congestion level at 75% usage is 0
    Info: Initial congestion area  at 75% usage is 0 (0.00%)

    Start NBR section for normal routing at 18:39:33 08/08/19
    Level 4, iteration 1
    13(0.00%) conflicts; 0(0.00%) untouched conn; 3090850 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -64.981ns/-3090.850ns; real time: 13 secs
    Level 4, iteration 2
    9(0.00%) conflicts; 0(0.00%) untouched conn; 3092562 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -64.981ns/-3092.562ns; real time: 13 secs
    Level 4, iteration 3
    7(0.00%) conflicts; 0(0.00%) untouched conn; 3112775 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -65.450ns/-3112.776ns; real time: 14 secs
    Level 4, iteration 4
    5(0.00%) conflicts; 0(0.00%) untouched conn; 3112775 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -65.450ns/-3112.776ns; real time: 14 secs
    Level 4, iteration 5
    2(0.00%) conflicts; 0(0.00%) untouched conn; 3200927 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -67.249ns/-3200.927ns; real time: 14 secs
    Level 4, iteration 6
    1(0.00%) conflict; 0(0.00%) untouched conn; 3200927 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -67.249ns/-3200.927ns; real time: 15 secs
    Level 4, iteration 7
    2(0.00%) conflicts; 0(0.00%) untouched conn; 3204119 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -67.249ns/-3204.119ns; real time: 15 secs
    Level 4, iteration 8
    1(0.00%) conflict; 0(0.00%) untouched conn; 3204119 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -67.249ns/-3204.119ns; real time: 15 secs
    Level 4, iteration 9
    0(0.00%) conflict; 0(0.00%) untouched conn; 3188906 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -67.249ns/-3188.906ns; real time: 15 secs

    Start NBR section for performance tuning (iteration 1) at 18:39:36 08/08/19
    Level 4, iteration 1
    0(0.00%) conflict; 0(0.00%) untouched conn; 3188906 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -67.249ns/-3188.906ns; real time: 15 secs

    Start NBR section for re-routing at 18:39:36 08/08/19
    Level 4, iteration 1
    0(0.00%) conflict; 0(0.00%) untouched conn; 3188906 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -67.249ns/-3188.906ns; real time: 15 secs

    Start NBR section for post-routing at 18:39:36 08/08/19

    End NBR router with 0 unrouted connection

    NBR Summary
    -----------
      Number of unrouted connections : 0 (0.00%)
      Number of connections with timing violations : 59 (4.75%)
      Estimated worst slack<setup> : -67.249ns
      Timing score<setup> : 8347444
    -----------
    Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.

    WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
       Signal=apple_module/D10/y3 loads=4 clock_loads=4
       Signal=apple_module/D10/y1 loads=4 clock_loads=4

    Total CPU time 15 secs
    Total REAL time: 17 secs
    Completely routed.
    End of route.  1242 routed (100.00%); 0 unrouted.

    Hold time timing score: 79, hold timing errors: 37

    Timing score: 8347443

    Dumping design to file Apple1Display_impl1.dir/5_1.ncd.

    All signals are completely routed.

    PAR_SUMMARY::Run status = Success
    PAR_SUMMARY::Number of unrouted conns = 0
    PAR_SUMMARY::Worst  slack<setup/<ns>> = -67.249
    PAR_SUMMARY::Timing score<setup/<ns>> = 8347.444
    PAR_SUMMARY::Worst  slack<hold /<ns>> = -3.228
    PAR_SUMMARY::Timing score<hold /<ns>> = 79.282
    PAR_SUMMARY::Number of errors = 0

    Total CPU  time to completion: 15 secs
    Total REAL time to completion: 17 secs

    par done!

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.