316 lines
15 KiB
VHDL
316 lines
15 KiB
VHDL
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-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.2.115
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-- Module Version: 5.2
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--C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n ShiftReg40 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type shiftreg -width 6 -depth 40 -mode 8 -memfile c:/dev/apple1display/docs/lut_2519.mem -memformat bin
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-- Mon Aug 05 13:43:30 2019
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library IEEE;
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use IEEE.std_logic_1164.all;
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-- synopsys translate_off
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library MACHXO2;
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use MACHXO2.components.all;
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-- synopsys translate_on
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entity ShiftReg40 is
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port (
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Din: in std_logic_vector(5 downto 0);
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Clock: in std_logic;
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ClockEn: in std_logic;
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Reset: in std_logic;
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Q: out std_logic_vector(5 downto 0));
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end ShiftReg40;
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architecture Structure of ShiftReg40 is
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-- internal signal declarations
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signal shreg_addr_w3_inv: std_logic;
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signal shreg_addr_w0_inv: std_logic;
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signal shreg_addr_w4_inv: std_logic;
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signal func_and_inet: std_logic;
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signal dec0_r102: std_logic;
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signal Reset_inv: std_logic;
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signal srrst_ctr: std_logic;
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signal scuba_vlo: std_logic;
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signal scuba_vhi: std_logic;
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signal ishreg_addr_w0: std_logic;
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signal ishreg_addr_w1: std_logic;
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signal sreg_0_ctr_1_ci: std_logic;
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signal shreg_addr_w0: std_logic;
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signal shreg_addr_w1: std_logic;
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signal ishreg_addr_w2: std_logic;
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signal ishreg_addr_w3: std_logic;
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signal co0: std_logic;
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signal shreg_addr_w2: std_logic;
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signal shreg_addr_w3: std_logic;
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signal ishreg_addr_w4: std_logic;
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signal ishreg_addr_w5: std_logic;
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signal co2: std_logic;
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signal co1: std_logic;
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signal shreg_addr_w4: std_logic;
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signal shreg_addr_w5: std_logic;
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-- local component declarations
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component CU2
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port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
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CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
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end component;
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component FADD2B
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port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
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B1: in std_logic; CI: in std_logic; COUT: out std_logic;
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S0: out std_logic; S1: out std_logic);
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end component;
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component FD1P3IX
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port (D: in std_logic; SP: in std_logic; CK: in std_logic;
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CD: in std_logic; Q: out std_logic);
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end component;
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component INV
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port (A: in std_logic; Z: out std_logic);
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end component;
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component OR2
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port (A: in std_logic; B: in std_logic; Z: out std_logic);
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end component;
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component ROM16X1A
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generic (INITVAL : in std_logic_vector(15 downto 0));
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port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
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AD0: in std_logic; DO0: out std_logic);
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end component;
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component VHI
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port (Z: out std_logic);
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end component;
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component VLO
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port (Z: out std_logic);
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end component;
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component DP8KC
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generic (INIT_DATA : in String; INITVAL_1F : in String;
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INITVAL_1E : in String; INITVAL_1D : in String;
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INITVAL_1C : in String; INITVAL_1B : in String;
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INITVAL_1A : in String; INITVAL_19 : in String;
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INITVAL_18 : in String; INITVAL_17 : in String;
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INITVAL_16 : in String; INITVAL_15 : in String;
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INITVAL_14 : in String; INITVAL_13 : in String;
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INITVAL_12 : in String; INITVAL_11 : in String;
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INITVAL_10 : in String; INITVAL_0F : in String;
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INITVAL_0E : in String; INITVAL_0D : in String;
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INITVAL_0C : in String; INITVAL_0B : in String;
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INITVAL_0A : in String; INITVAL_09 : in String;
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INITVAL_08 : in String; INITVAL_07 : in String;
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INITVAL_06 : in String; INITVAL_05 : in String;
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INITVAL_04 : in String; INITVAL_03 : in String;
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INITVAL_02 : in String; INITVAL_01 : in String;
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INITVAL_00 : in String; ASYNC_RESET_RELEASE : in String;
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RESETMODE : in String; GSR : in String;
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WRITEMODE_B : in String; WRITEMODE_A : in String;
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CSDECODE_B : in String; CSDECODE_A : in String;
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REGMODE_B : in String; REGMODE_A : in String;
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DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
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port (DIA8: in std_logic; DIA7: in std_logic;
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DIA6: in std_logic; DIA5: in std_logic;
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DIA4: in std_logic; DIA3: in std_logic;
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DIA2: in std_logic; DIA1: in std_logic;
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DIA0: in std_logic; ADA12: in std_logic;
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ADA11: in std_logic; ADA10: in std_logic;
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ADA9: in std_logic; ADA8: in std_logic;
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ADA7: in std_logic; ADA6: in std_logic;
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ADA5: in std_logic; ADA4: in std_logic;
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ADA3: in std_logic; ADA2: in std_logic;
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ADA1: in std_logic; ADA0: in std_logic; CEA: in std_logic;
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OCEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
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CSA2: in std_logic; CSA1: in std_logic;
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CSA0: in std_logic; RSTA: in std_logic;
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DIB8: in std_logic; DIB7: in std_logic;
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DIB6: in std_logic; DIB5: in std_logic;
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DIB4: in std_logic; DIB3: in std_logic;
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DIB2: in std_logic; DIB1: in std_logic;
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DIB0: in std_logic; ADB12: in std_logic;
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ADB11: in std_logic; ADB10: in std_logic;
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ADB9: in std_logic; ADB8: in std_logic;
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ADB7: in std_logic; ADB6: in std_logic;
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ADB5: in std_logic; ADB4: in std_logic;
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ADB3: in std_logic; ADB2: in std_logic;
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ADB1: in std_logic; ADB0: in std_logic; CEB: in std_logic;
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OCEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
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CSB2: in std_logic; CSB1: in std_logic;
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CSB0: in std_logic; RSTB: in std_logic;
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DOA8: out std_logic; DOA7: out std_logic;
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DOA6: out std_logic; DOA5: out std_logic;
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DOA4: out std_logic; DOA3: out std_logic;
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DOA2: out std_logic; DOA1: out std_logic;
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DOA0: out std_logic; DOB8: out std_logic;
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DOB7: out std_logic; DOB6: out std_logic;
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DOB5: out std_logic; DOB4: out std_logic;
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DOB3: out std_logic; DOB2: out std_logic;
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DOB1: out std_logic; DOB0: out std_logic);
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end component;
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attribute MEM_LPC_FILE : string;
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attribute MEM_INIT_FILE : string;
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attribute GSR : string;
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attribute MEM_LPC_FILE of sram_1_0_0_0 : label is "ShiftReg40.lpc";
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attribute MEM_INIT_FILE of sram_1_0_0_0 : label is "lut_2519.mem";
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attribute GSR of FF_5 : label is "ENABLED";
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attribute GSR of FF_4 : label is "ENABLED";
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attribute GSR of FF_3 : label is "ENABLED";
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attribute GSR of FF_2 : label is "ENABLED";
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attribute GSR of FF_1 : label is "ENABLED";
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attribute GSR of FF_0 : label is "ENABLED";
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attribute NGD_DRC_MASK : integer;
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attribute NGD_DRC_MASK of Structure : architecture is 1;
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begin
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-- component instantiation statements
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INV_3: INV
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port map (A=>shreg_addr_w0, Z=>shreg_addr_w0_inv);
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INV_2: INV
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port map (A=>shreg_addr_w3, Z=>shreg_addr_w3_inv);
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INV_1: INV
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port map (A=>shreg_addr_w4, Z=>shreg_addr_w4_inv);
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LUT4_1: ROM16X1A
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generic map (initval=> X"8000")
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port map (AD3=>shreg_addr_w0_inv, AD2=>shreg_addr_w1,
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AD1=>shreg_addr_w2, AD0=>shreg_addr_w3_inv,
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DO0=>func_and_inet);
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LUT4_0: ROM16X1A
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generic map (initval=> X"8000")
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port map (AD3=>func_and_inet, AD2=>shreg_addr_w4_inv,
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AD1=>shreg_addr_w5, AD0=>ClockEn, DO0=>dec0_r102);
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OR2_t0: OR2
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port map (A=>Reset, B=>dec0_r102, Z=>srrst_ctr);
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INV_0: INV
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port map (A=>Reset, Z=>Reset_inv);
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sram_1_0_0_0: DP8KC
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generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
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INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
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INITVAL_01=> "0x0000000000000000000000000000000000000000000000000000000000000002704C250482304421",
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INITVAL_00=> "0x0401F03C1D0381B034190301702C1502813024110200F01C0D0180B014090100700C050080300401",
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CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
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WRITEMODE_A=> "READBEFOREWRITE", GSR=> "ENABLED", RESETMODE=> "ASYNC",
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REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
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DATA_WIDTH_A=> 9)
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port map (DIA8=>scuba_vlo, DIA7=>scuba_vlo, DIA6=>scuba_vlo,
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DIA5=>Din(5), DIA4=>Din(4), DIA3=>Din(3), DIA2=>Din(2),
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DIA1=>Din(1), DIA0=>Din(0), ADA12=>scuba_vlo,
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ADA11=>scuba_vlo, ADA10=>scuba_vlo, ADA9=>scuba_vlo,
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ADA8=>shreg_addr_w5, ADA7=>shreg_addr_w4,
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ADA6=>shreg_addr_w3, ADA5=>shreg_addr_w2,
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ADA4=>shreg_addr_w1, ADA3=>shreg_addr_w0, ADA2=>scuba_vlo,
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ADA1=>scuba_vlo, ADA0=>scuba_vhi, CEA=>ClockEn,
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OCEA=>ClockEn, CLKA=>Clock, WEA=>Reset_inv, CSA2=>scuba_vlo,
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CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset,
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DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
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DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
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DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
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ADB12=>scuba_vlo, ADB11=>scuba_vlo, ADB10=>scuba_vlo,
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ADB9=>scuba_vlo, ADB8=>scuba_vlo, ADB7=>scuba_vlo,
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ADB6=>scuba_vlo, ADB5=>scuba_vlo, ADB4=>scuba_vlo,
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ADB3=>scuba_vlo, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
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ADB0=>scuba_vlo, CEB=>scuba_vhi, OCEB=>scuba_vhi,
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CLKB=>scuba_vlo, WEB=>scuba_vlo, CSB2=>scuba_vlo,
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CSB1=>scuba_vlo, CSB0=>scuba_vlo, RSTB=>scuba_vlo,
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DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>Q(5), DOA4=>Q(4),
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DOA3=>Q(3), DOA2=>Q(2), DOA1=>Q(1), DOA0=>Q(0), DOB8=>open,
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DOB7=>open, DOB6=>open, DOB5=>open, DOB4=>open, DOB3=>open,
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DOB2=>open, DOB1=>open, DOB0=>open);
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FF_5: FD1P3IX
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port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock,
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CD=>srrst_ctr, Q=>shreg_addr_w0);
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FF_4: FD1P3IX
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port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock,
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CD=>srrst_ctr, Q=>shreg_addr_w1);
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FF_3: FD1P3IX
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port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock,
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CD=>srrst_ctr, Q=>shreg_addr_w2);
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FF_2: FD1P3IX
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port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock,
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CD=>srrst_ctr, Q=>shreg_addr_w3);
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FF_1: FD1P3IX
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port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock,
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CD=>srrst_ctr, Q=>shreg_addr_w4);
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FF_0: FD1P3IX
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port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock,
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CD=>srrst_ctr, Q=>shreg_addr_w5);
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scuba_vlo_inst: VLO
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port map (Z=>scuba_vlo);
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scuba_vhi_inst: VHI
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port map (Z=>scuba_vhi);
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sreg_0_ctr_1_cia: FADD2B
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port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
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B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci,
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S0=>open, S1=>open);
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sreg_0_ctr_1_0: CU2
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port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0,
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PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0,
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NC1=>ishreg_addr_w1);
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sreg_0_ctr_1_1: CU2
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port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3,
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CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3);
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sreg_0_ctr_1_2: CU2
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port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5,
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CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5);
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end Structure;
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-- synopsys translate_off
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library MACHXO2;
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configuration Structure_CON of ShiftReg40 is
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for Structure
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for all:CU2 use entity MACHXO2.CU2(V); end for;
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for all:FADD2B use entity MACHXO2.FADD2B(V); end for;
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for all:FD1P3IX use entity MACHXO2.FD1P3IX(V); end for;
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for all:INV use entity MACHXO2.INV(V); end for;
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for all:OR2 use entity MACHXO2.OR2(V); end for;
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for all:ROM16X1A use entity MACHXO2.ROM16X1A(V); end for;
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for all:VHI use entity MACHXO2.VHI(V); end for;
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for all:VLO use entity MACHXO2.VLO(V); end for;
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for all:DP8KC use entity MACHXO2.DP8KC(V); end for;
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end for;
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end Structure_CON;
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-- synopsys translate_on
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