27 lines
1.2 KiB
Plaintext
27 lines
1.2 KiB
Plaintext
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SCUBA, Version Diamond (64-bit) 3.10.2.115
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Mon Aug 05 08:34:49 2019
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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Issued command : C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n master_clk -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 25 -fclkop 25 -fclkop_tol 0.0 -fclkos 14.31818 -fclkos_tol 0.5 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phase_cntl STATIC -fb_mode 5
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Circuit name : master_clk
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Module type : pll
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Module Version : 5.7
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Ports :
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Inputs : CLKI
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Outputs : CLKOP, CLKOS
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I/O buffer : not inserted
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EDIF output : master_clk.edn
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VHDL output : master_clk.vhd
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VHDL template : master_clk_tmpl.vhd
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VHDL purpose : for synthesis and simulation
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Bus notation : big endian
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Report output : master_clk.srp
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Element Usage :
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EHXPLLJ : 1
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Estimated Resource Usage:
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