mirror of
https://github.com/Myndale/Apple1Display.git
synced 2024-11-15 08:04:31 +00:00
259 lines
8.8 KiB
Plaintext
259 lines
8.8 KiB
Plaintext
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[ START MERGED ]
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apple_module/D13/CN apple_module/vbl_i
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apple_module/C11b/srrst_ctr apple_module/C11b/dec0_r2046
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apple_module/D14b/srrst_ctr apple_module/D14b/dec0_r2046
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apple_module/D14a/srrst_ctr apple_module/D14a/dec0_r2046
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apple_module/D4b/srrst_ctr apple_module/D4b/dec0_r2046
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apple_module/D4a/srrst_ctr apple_module/D4a/dec0_r2046
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apple_module/D5b/srrst_ctr apple_module/D5b/dec0_r2046
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apple_module/D5a/srrst_ctr apple_module/D5a/dec0_r2046
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apple_module/C3/LineBuffer/srrst_ctr apple_module/C3/LineBuffer/dec0_r102
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apple_module/horz_count_upper_i[3] apple_module/horz_count_upper[3]
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[ END MERGED ]
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[ START CLIPPED ]
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uart_module/r_RX_DV_1_bm
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clock_module/GND
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apple_module/D2/GND
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apple_module/C3/LineBuffer/GND
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apple_module/C3/LineBuffer/Reset_inv
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apple_module/C3/LineBuffer/VCC
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apple_module/D5a/GND
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apple_module/D5a/Reset_inv
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apple_module/D5a/VCC
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apple_module/D5b/GND
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apple_module/D5b/Reset_inv
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apple_module/D5b/VCC
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apple_module/D4a/GND
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apple_module/D4a/Reset_inv
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apple_module/D4a/VCC
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apple_module/D4b/GND
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apple_module/D4b/Reset_inv
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apple_module/D4b/VCC
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apple_module/D14a/GND
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apple_module/D14a/Reset_inv
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apple_module/D14a/VCC
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apple_module/D14b/GND
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apple_module/D14b/Reset_inv
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apple_module/D14b/VCC
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apple_module/C11b/GND
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apple_module/C11b/Reset_inv
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apple_module/C11b/VCC
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uart_module/GND
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un6_flash_count_s_21_0_S1
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un6_flash_count_s_21_0_COUT
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clock_module/DPHSRC
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clock_module/PLLACK
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clock_module/PLLDATO0
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clock_module/PLLDATO1
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clock_module/PLLDATO2
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clock_module/PLLDATO3
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clock_module/PLLDATO4
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clock_module/PLLDATO5
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clock_module/PLLDATO6
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clock_module/PLLDATO7
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clock_module/REFCLK
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clock_module/INTLOCK
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clock_module/LOCK
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clock_module/CLKOS3
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clock_module/CLKOS2
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clock_module/CLKOP
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apple_module/D2/sig2513_0_0_0_DOB8
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apple_module/D2/sig2513_0_0_0_DOB7
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apple_module/D2/sig2513_0_0_0_DOB6
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apple_module/D2/sig2513_0_0_0_DOB5
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apple_module/D2/sig2513_0_0_0_DOB4
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apple_module/D2/sig2513_0_0_0_DOB3
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apple_module/D2/sig2513_0_0_0_DOB2
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apple_module/D2/sig2513_0_0_0_DOB1
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apple_module/D2/sig2513_0_0_0_DOB0
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apple_module/D2/sig2513_0_0_0_DOA8
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apple_module/D2/sig2513_0_0_0_DOA7
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apple_module/D2/sig2513_0_0_0_DOA6
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apple_module/D2/sig2513_0_0_0_DOA5
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apple_module/C3/LineBuffer/co2
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apple_module/C3/LineBuffer/sreg_0_ctr_1_cia_S1
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apple_module/C3/LineBuffer/sreg_0_ctr_1_cia_S0
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOB8
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOB7
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOB6
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOB5
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOB4
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOB3
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOB2
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOB1
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOB0
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOA8
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOA7
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apple_module/C3/LineBuffer/sram_1_0_0_0_DOA6
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apple_module/D5a/sram_1_0_0_DOB8_0
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apple_module/D5a/sram_1_0_0_DOB7_0
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apple_module/D5a/sram_1_0_0_DOB6_0
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apple_module/D5a/sram_1_0_0_DOB5_0
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apple_module/D5a/sram_1_0_0_DOB4_0
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apple_module/D5a/sram_1_0_0_DOB3_0
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apple_module/D5a/sram_1_0_0_DOB2_0
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apple_module/D5a/sram_1_0_0_DOB1_0
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apple_module/D5a/sram_1_0_0_DOB0_0
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apple_module/D5a/sram_1_0_0_DOA8_0
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apple_module/D5a/sram_1_0_0_DOA7_0
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apple_module/D5a/sram_1_0_0_DOA6_0
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apple_module/D5a/sram_1_0_0_0_DOA5
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apple_module/D5a/sram_1_0_0_0_DOA4
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apple_module/D5a/sram_1_0_0_0_DOA3
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apple_module/D5a/sram_1_0_0_0_DOA2
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apple_module/D5a/sram_1_0_0_0_DOA1
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apple_module/D5a/sreg_0_ctr_1_cia_S1_0
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apple_module/D5a/sreg_0_ctr_1_cia_S0_0
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apple_module/D5a/co4
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apple_module/D5b/co4
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apple_module/D5b/sreg_0_ctr_1_cia_S1_1
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apple_module/D5b/sreg_0_ctr_1_cia_S0_1
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apple_module/D5b/sram_1_0_0_DOB8_1
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apple_module/D5b/sram_1_0_0_DOB7_1
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apple_module/D5b/sram_1_0_0_DOB6_1
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apple_module/D5b/sram_1_0_0_DOB5_1
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apple_module/D5b/sram_1_0_0_DOB4_1
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apple_module/D5b/sram_1_0_0_DOB3_1
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apple_module/D5b/sram_1_0_0_DOB2_1
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apple_module/D5b/sram_1_0_0_DOB1_1
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apple_module/D5b/sram_1_0_0_DOB0_1
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apple_module/D5b/sram_1_0_0_DOA8_1
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apple_module/D5b/sram_1_0_0_DOA7_1
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apple_module/D5b/sram_1_0_0_DOA6_1
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apple_module/D5b/sram_1_0_0_DOA5_0
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apple_module/D5b/sram_1_0_0_DOA4_0
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apple_module/D5b/sram_1_0_0_DOA3_0
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apple_module/D5b/sram_1_0_0_DOA2_0
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apple_module/D5b/sram_1_0_0_DOA1_0
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apple_module/D4a/co4
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apple_module/D4a/sreg_0_ctr_1_cia_S1_2
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apple_module/D4a/sreg_0_ctr_1_cia_S0_2
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apple_module/D4a/sram_1_0_0_DOB8_2
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apple_module/D4a/sram_1_0_0_DOB7_2
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apple_module/D4a/sram_1_0_0_DOB6_2
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apple_module/D4a/sram_1_0_0_DOB5_2
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apple_module/D4a/sram_1_0_0_DOB4_2
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apple_module/D4a/sram_1_0_0_DOB3_2
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apple_module/D4a/sram_1_0_0_DOB2_2
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apple_module/D4a/sram_1_0_0_DOB1_2
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apple_module/D4a/sram_1_0_0_DOB0_2
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apple_module/D4a/sram_1_0_0_DOA8_2
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apple_module/D4a/sram_1_0_0_DOA7_2
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apple_module/D4a/sram_1_0_0_DOA6_2
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apple_module/D4a/sram_1_0_0_DOA5_1
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apple_module/D4a/sram_1_0_0_DOA4_1
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apple_module/D4a/sram_1_0_0_DOA3_1
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apple_module/D4a/sram_1_0_0_DOA2_1
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apple_module/D4a/sram_1_0_0_DOA1_1
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apple_module/D4b/co4
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apple_module/D4b/sreg_0_ctr_1_cia_S1_3
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apple_module/D4b/sreg_0_ctr_1_cia_S0_3
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apple_module/D4b/sram_1_0_0_DOB8_3
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apple_module/D4b/sram_1_0_0_DOB7_3
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apple_module/D4b/sram_1_0_0_DOB6_3
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apple_module/D4b/sram_1_0_0_DOB5_3
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apple_module/D4b/sram_1_0_0_DOB4_3
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apple_module/D4b/sram_1_0_0_DOB3_3
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apple_module/D4b/sram_1_0_0_DOB2_3
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apple_module/D4b/sram_1_0_0_DOB1_3
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apple_module/D4b/sram_1_0_0_DOB0_3
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apple_module/D4b/sram_1_0_0_DOA8_3
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apple_module/D4b/sram_1_0_0_DOA7_3
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apple_module/D4b/sram_1_0_0_DOA6_3
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apple_module/D4b/sram_1_0_0_DOA5_2
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apple_module/D4b/sram_1_0_0_DOA4_2
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apple_module/D4b/sram_1_0_0_DOA3_2
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apple_module/D4b/sram_1_0_0_DOA2_2
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apple_module/D4b/sram_1_0_0_DOA1_2
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apple_module/D14a/co4
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apple_module/D14a/sreg_0_ctr_1_cia_S1_4
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apple_module/D14a/sreg_0_ctr_1_cia_S0_4
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apple_module/D14a/sram_1_0_0_DOB8_4
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apple_module/D14a/sram_1_0_0_DOB7_4
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apple_module/D14a/sram_1_0_0_DOB6_4
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apple_module/D14a/sram_1_0_0_DOB5_4
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apple_module/D14a/sram_1_0_0_DOB4_4
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apple_module/D14a/sram_1_0_0_DOB3_4
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apple_module/D14a/sram_1_0_0_DOB2_4
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apple_module/D14a/sram_1_0_0_DOB1_4
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apple_module/D14a/sram_1_0_0_DOB0_4
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apple_module/D14a/sram_1_0_0_DOA8_4
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apple_module/D14a/sram_1_0_0_DOA7_4
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apple_module/D14a/sram_1_0_0_DOA6_4
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apple_module/D14a/sram_1_0_0_DOA5_3
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apple_module/D14a/sram_1_0_0_DOA4_3
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apple_module/D14a/sram_1_0_0_DOA3_3
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apple_module/D14a/sram_1_0_0_DOA2_3
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apple_module/D14a/sram_1_0_0_DOA1_3
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apple_module/D14b/co4
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apple_module/D14b/sreg_0_ctr_1_cia_S1_5
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apple_module/D14b/sreg_0_ctr_1_cia_S0_5
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apple_module/D14b/sram_1_0_0_DOB8_5
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apple_module/D14b/sram_1_0_0_DOB7_5
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apple_module/D14b/sram_1_0_0_DOB6_5
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apple_module/D14b/sram_1_0_0_DOB5_5
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apple_module/D14b/sram_1_0_0_DOB4_5
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apple_module/D14b/sram_1_0_0_DOB3_5
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apple_module/D14b/sram_1_0_0_DOB2_5
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apple_module/D14b/sram_1_0_0_DOB1_5
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apple_module/D14b/sram_1_0_0_DOB0_5
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apple_module/D14b/sram_1_0_0_DOA8_5
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apple_module/D14b/sram_1_0_0_DOA7_5
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apple_module/D14b/sram_1_0_0_DOA6_5
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apple_module/D14b/sram_1_0_0_DOA5_4
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apple_module/D14b/sram_1_0_0_DOA4_4
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apple_module/D14b/sram_1_0_0_DOA3_4
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apple_module/D14b/sram_1_0_0_DOA2_4
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apple_module/D14b/sram_1_0_0_DOA1_4
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apple_module/C11b/co4
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apple_module/C11b/sreg_0_ctr_1_cia_S1_6
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apple_module/C11b/sreg_0_ctr_1_cia_S0_6
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apple_module/C11b/sram_1_0_0_DOB8_6
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apple_module/C11b/sram_1_0_0_DOB7_6
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apple_module/C11b/sram_1_0_0_DOB6_6
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apple_module/C11b/sram_1_0_0_DOB5_6
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apple_module/C11b/sram_1_0_0_DOB4_6
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apple_module/C11b/sram_1_0_0_DOB3_6
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apple_module/C11b/sram_1_0_0_DOB2_6
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apple_module/C11b/sram_1_0_0_DOB1_6
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apple_module/C11b/sram_1_0_0_DOB0_6
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apple_module/C11b/sram_1_0_0_DOA8_6
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apple_module/C11b/sram_1_0_0_DOA7_6
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apple_module/C11b/sram_1_0_0_DOA6_6
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apple_module/C11b/sram_1_0_0_DOA5_5
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apple_module/C11b/sram_1_0_0_DOA4_5
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apple_module/C11b/sram_1_0_0_DOA3_5
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apple_module/C11b/sram_1_0_0_DOA2_5
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apple_module/C11b/sram_1_0_0_DOA1_5
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uart_module/un1_r_Clk_Count_cry_0_0_S0
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uart_module/N_1
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uart_module/un1_r_Clk_Count_s_7_0_S1
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uart_module/un1_r_Clk_Count_s_7_0_COUT
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un6_flash_count_cry_0_0_S1
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un6_flash_count_cry_0_0_S0
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N_1
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[ END CLIPPED ]
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||
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[ START DESIGN PREFS ]
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SCHEMATIC START ;
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# map: version Diamond (64-bit) 3.10.2.115 -- WARNING: Map write only section -- Thu Aug 08 18:39:20 2019
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SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
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LOCATE COMP "User_LED1" SITE "1" ;
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LOCATE COMP "sys_clock" SITE "126" ;
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LOCATE COMP "slave_rx_i" SITE "141" ;
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LOCATE COMP "spi1_cs" SITE "125" ;
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LOCATE COMP "SRAM_n_cs" SITE "67" ;
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LOCATE COMP "User_PB1" SITE "11" ;
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||
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LOCATE COMP "sync" SITE "84" ;
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||
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LOCATE COMP "luma" SITE "86" ;
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||
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LOCATE COMP "NTSC_DAC[3]" SITE "27" ;
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||
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LOCATE COMP "NTSC_DAC[2]" SITE "28" ;
|
||
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LOCATE COMP "NTSC_DAC[1]" SITE "143" ;
|
||
|
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LOCATE COMP "NTSC_DAC[0]" SITE "31" ;
|
||
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LOCATE COMP "User_LED2" SITE "2" ;
|
||
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FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
|
||
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FREQUENCY NET "circuit_clk" 14.285714 MHz ;
|
||
|
|
FREQUENCY PORT "sys_clock" 25.000000 MHz ;
|
||
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SCHEMATIC END ;
|
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[ END DESIGN PREFS ]
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