# messages

id: CD326
link: "C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":122:23:122:37|
kind: warning
message:
Port clkop of entity work.master_clk is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":191:13:191:24|
kind: warning
message:
Port carry of entity work.dm74161 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":226:14:226:24|
kind: warning
message:
Port y2 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":226:14:226:24|
kind: warning
message:
Port y1 of entity work.dm7402 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":233:14:233:24|
kind: warning
message:
Port y5 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":233:14:233:24|
kind: warning
message:
Port y3 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":233:14:233:24|
kind: warning
message:
Port y2 of entity work.dm7404 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":241:14:241:24|
kind: warning
message:
Port y4 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|
kind: warning
message:
Port q0_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|
kind: warning
message:
Port q1_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|
kind: warning
message:
Port q2_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|
kind: warning
message:
Port q3_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|
kind: warning
message:
Port q4_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":321:12:322:7|
kind: warning
message:
Port q5_i of entity work.dm74174 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":354:12:355:4|
kind: warning
message:
Port y1 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":367:13:368:4|
kind: warning
message:
Port y4 of entity work.dm7408 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":367:13:368:4|
kind: warning
message:
Port y1 of entity work.dm7408 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":374:12:375:4|
kind: warning
message:
Port y3 of entity work.dm7432 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":381:12:382:4|
kind: warning
message:
Port y3 of entity work.dm7410 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":386:13:387:4|
kind: warning
message:
Port y2 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD326
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":386:13:387:4|
kind: warning
message:
Port y1 of entity work.dm7400 is unconnected. If a port needs to remain unconnected, use the keyword open.


id: CD638
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:7:47:22|
kind: warning
message:
Signal buffer_char_in_0 is undriven. Either assign the signal a value or remove the signal declaration.


id: CD638
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:25:47:40|
kind: warning
message:
Signal buffer_char_in_1 is undriven. Either assign the signal a value or remove the signal declaration.


id: CD638
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:43:47:58|
kind: warning
message:
Signal buffer_char_in_2 is undriven. Either assign the signal a value or remove the signal declaration.


id: CD638
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:61:47:76|
kind: warning
message:
Signal buffer_char_in_3 is undriven. Either assign the signal a value or remove the signal declaration.


id: CD638
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:79:47:94|
kind: warning
message:
Signal buffer_char_in_4 is undriven. Either assign the signal a value or remove the signal declaration.


id: CD638
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":47:97:47:112|
kind: warning
message:
Signal buffer_char_in_5 is undriven. Either assign the signal a value or remove the signal declaration.


id: CD638
link: "C:\Dev\Apple1Display\impl1\Apple1Display.vhd":65:7:65:19|
kind: warning
message:
Signal unconnected_1 is undriven. Either assign the signal a value or remove the signal declaration.


id: CL260
link: "C:\Dev\Apple1Display\impl1\source\FleaFPGA_Uno_Top.vhd":165:2:165:3|
kind: warning
message:
Pruning register bit 23 of flash_count(23 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.


id: MF666
kind: note
message:
Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)


id: FX474
kind: warning
message:
User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 


id: BN362
link: "c:\dev\apple1display\uart_rx.vhd":62:4:62:5
kind: note
message:
Removing sequential instance r_RX_Byte[7] (in view: work.UART_RX(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.


id: MT529
link: "c:\dev\apple1display\uart_rx.vhd":37:36:37:38
kind: warning
message:
Found inferred clock FleaFPGA_Uno_E1|sys_clock which controls 57 sequential elements including uart_module.r_RX_Data. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: warning
message:
Found inferred clock master_clk|CLKOS_inferred_clock which controls 6 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: warning
message:
Found inferred clock dm7400_1|y3_inferred_clock which controls 44 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\sig2504.vhd":187:4:187:15
kind: warning
message:
Found inferred clock dm7427|y1_inferred_clock which controls 83 sequential elements including apple_module.D5a.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\shiftreg40.vhd":186:4:186:15
kind: warning
message:
Found inferred clock dm7400_1|y1_inferred_clock which controls 7 sequential elements including apple_module.C3.LineBuffer.sram_1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: MT529
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: warning
message:
Found inferred clock dm74175|q0_i_inferred_clock which controls 13 sequential elements including apple_module.C13.states[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 


id: BN362
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: note
message:
Removing sequential instance flash_count[22] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.


id: BN362
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: note
message:
Removing sequential instance apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.


id: BN291
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: advice
message:
Boundary register apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_6_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_5_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_4_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_3_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_2_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_1_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_0_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: MT617
kind: note
message:
Automatically generated clock dm74161_4|count_derived_clock[3] has lost its master clock dm74175|q0_i_inferred_clock and is being removed


id: MT246
link: "c:\dev\apple1display\impl1\master_clk.vhd":109:4:109:12
kind: warning
message:
Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


id: MT420
kind: warning
message:
Found inferred clock FleaFPGA_Uno_E1|sys_clock with period 1000.00ns. Please declare a user-defined clock on object "p:sys_clock"


id: MT420
kind: warning
message:
Found inferred clock dm7427|y1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.C5.y1"


id: MT420
kind: warning
message:
Found inferred clock dm7400_1|y1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.D10.y1"


id: MT420
kind: warning
message:
Found inferred clock dm7400_1|y3_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.D10.y3"


id: MT320
kind: note
message:
This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.


