# messages

id: MF666
kind: note
message:
Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)


id: BN362
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: note
message:
Removing sequential instance flash_count[22] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.


id: BN362
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: note
message:
Removing sequential instance apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.


id: BN291
link: "c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3
kind: advice
message:
Boundary register apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_6_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_5_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_4_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_3_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_2_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_1_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3
kind: advice
message:
Boundary register rd_0_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: MT617
kind: note
message:
Automatically generated clock dm74161_4|count_derived_clock[3] has lost its master clock dm74175|q0_i_inferred_clock and is being removed


id: MT246
link: "c:\dev\apple1display\impl1\master_clk.vhd":109:4:109:12
kind: warning
message:
Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


id: MT420
kind: warning
message:
Found inferred clock FleaFPGA_Uno_E1|sys_clock with period 1000.00ns. Please declare a user-defined clock on object "p:sys_clock"


id: MT420
kind: warning
message:
Found inferred clock dm7427|y1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.C5.y1"


id: MT420
kind: warning
message:
Found inferred clock dm7400_1|y1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.D10.y1"


id: MT420
kind: warning
message:
Found inferred clock dm7400_1|y3_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.D10.y3"


id: MT320
kind: note
message:
This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.


