mirror of
https://github.com/Myndale/Apple1Display.git
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53 lines
1.3 KiB
Common Lisp
53 lines
1.3 KiB
Common Lisp
[ActiveSupport PAR]
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; Global primary clocks
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GLOBAL_PRIMARY_USED = 3;
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; Global primary clock #0
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GLOBAL_PRIMARY_0_SIGNALNAME = circuit_clk;
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GLOBAL_PRIMARY_0_DRIVERTYPE = PLL;
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GLOBAL_PRIMARY_0_LOADNUM = 24;
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; Global primary clock #1
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GLOBAL_PRIMARY_1_SIGNALNAME = apple_module/C5/y1;
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GLOBAL_PRIMARY_1_DRIVERTYPE = SLICE;
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GLOBAL_PRIMARY_1_LOADNUM = 47;
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; Global primary clock #2
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GLOBAL_PRIMARY_2_SIGNALNAME = sys_clock_c;
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GLOBAL_PRIMARY_2_DRIVERTYPE = CLK_PIN;
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GLOBAL_PRIMARY_2_LOADNUM = 38;
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; # of global secondary clocks
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GLOBAL_SECONDARY_USED = 1;
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; Global secondary clock #0
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GLOBAL_SECONDARY_0_SIGNALNAME = un1_flash_countlt22;
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GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
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GLOBAL_SECONDARY_0_LOADNUM = 19;
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GLOBAL_SECONDARY_0_SIGTYPE = CE+RST;
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; I/O Bank 0 Usage
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BANK_0_USED = 4;
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BANK_0_AVAIL = 28;
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BANK_0_VCCIO = 3.3V;
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BANK_0_VREF1 = NA;
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; I/O Bank 1 Usage
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BANK_1_USED = 2;
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BANK_1_AVAIL = 29;
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BANK_1_VCCIO = 3.3V;
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BANK_1_VREF1 = NA;
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; I/O Bank 2 Usage
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BANK_2_USED = 1;
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BANK_2_AVAIL = 29;
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BANK_2_VCCIO = 2.5V;
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BANK_2_VREF1 = NA;
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; I/O Bank 3 Usage
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BANK_3_USED = 3;
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BANK_3_AVAIL = 9;
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BANK_3_VCCIO = 3.3V;
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BANK_3_VREF1 = NA;
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; I/O Bank 4 Usage
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BANK_4_USED = 2;
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BANK_4_AVAIL = 10;
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BANK_4_VCCIO = 2.5V;
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BANK_4_VREF1 = NA;
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; I/O Bank 5 Usage
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BANK_5_USED = 3;
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BANK_5_AVAIL = 10;
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BANK_5_VCCIO = 3.3V;
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BANK_5_VREF1 = NA;
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