42 lines
3.6 KiB
Plaintext
42 lines
3.6 KiB
Plaintext
# Synopsys Constraint Checker(syntax only), version maplat, Build 1796R, built Aug 4 2017
|
|
# Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
|
|
|
# Written on Thu Aug 8 18:39:12 2019
|
|
|
|
|
|
##### DESIGN INFO #######################################################
|
|
|
|
Top View: "FleaFPGA_Uno_E1"
|
|
Constraint File(s): (none)
|
|
|
|
#Run constraint checker to find more issues with constraints.
|
|
#########################################################################
|
|
|
|
|
|
|
|
No issues found in constraint syntax.
|
|
|
|
|
|
|
|
Clock Summary
|
|
*************
|
|
|
|
Start Requested Requested Clock Clock Clock
|
|
Level Clock Frequency Period Type Group Load
|
|
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
0 - System 1.0 MHz 1000.000 system system_clkgroup 0
|
|
|
|
0 - dm7427|y1_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_3 83
|
|
|
|
0 - FleaFPGA_Uno_E1|sys_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_0 57
|
|
|
|
0 - dm7400_1|y3_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_2 44
|
|
|
|
0 - dm74175|q0_i_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_5 13
|
|
1 . dm74161_4|count_derived_clock[3] 1.0 MHz 1000.000 derived (from dm74175|q0_i_inferred_clock) Inferred_clkgroup_5 21
|
|
|
|
0 - dm7400_1|y1_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_4 7
|
|
|
|
0 - master_clk|CLKOS_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_1 6
|
|
=========================================================================================================================================================
|