684 lines
32 KiB
HTML
684 lines
32 KiB
HTML
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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
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Loading design for application trce from file apple1display_impl1_map.ncd.
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Design name: FleaFPGA_Uno_E1
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-7000HC
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Package: TQFP144
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Performance: 4
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Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.10_x64/ispfpga.
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Package Status: Final Version 1.39.
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Performance Hardware Data Status: Final Version 34.4.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.10.2.115</big></U></B>
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Thu Aug 08 18:39:21 2019
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o Apple1Display_impl1.tw1 -gui -msgset C:/Dev/Apple1Display/promote.xml Apple1Display_impl1_map.ncd Apple1Display_impl1.prf
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Design file: apple1display_impl1_map.ncd
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Preference file: apple1display_impl1.prf
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Device,speed: LCMXO2-7000HC,4
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
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<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY NET "sys_clock_c" 25.000000 MHz (0 errors)</A></LI> 1257 items scored, 0 timing errors detected.
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Report: 86.296MHz is the maximum frequency for this preference.
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<FONT COLOR=red><LI><A href='#map_twr_pref_0_1' Target='right'><FONT COLOR=red>FREQUENCY NET "circuit_clk" 14.285714 MHz (204 errors)</FONT></A></LI>
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</FONT> 899 items scored, 204 timing errors detected.
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Warning: 11.371MHz is the maximum frequency for this preference.
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<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "sys_clock" 25.000000 MHz (0 errors)</A></LI> 1120 items scored, 0 timing errors detected.
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Report: 28.500MHz is the maximum frequency for this preference.
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
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1257 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 28.412ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q flash_count[3] (from sys_clock_c +)
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Destination: FF Data in rd[5] (to sys_clock_c +)
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FF rd[4]
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Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
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Constraint Details:
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11.306ns physical path delay SLICE_61 to SLICE_121 meets
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40.000ns delay constraint less
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0.282ns CE_SET requirement (totaling 39.718ns) by 28.412ns
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Physical Path Details:
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Data path SLICE_61 to SLICE_121:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from sys_clock_c)
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ROUTE 2 e 1.234 SLICE_61.Q0 to SLICE_147.B1 flash_count[3]
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CTOF_DEL --- 0.495 SLICE_147.B1 to SLICE_147.F1 SLICE_147
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ROUTE 1 e 0.480 SLICE_147.F1 to SLICE_147.D0 un1_flash_countlto4_1
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CTOF_DEL --- 0.495 SLICE_147.D0 to SLICE_147.F0 SLICE_147
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ROUTE 1 e 1.234 SLICE_147.F0 to SLICE_120.B0 un1_flash_countlt9
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CTOF_DEL --- 0.495 SLICE_120.B0 to SLICE_120.F0 SLICE_120
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ROUTE 1 e 1.234 SLICE_120.F0 to SLICE_156.D1 un1_flash_countlt14
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CTOF_DEL --- 0.495 SLICE_156.D1 to SLICE_156.F1 SLICE_156
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ROUTE 1 e 1.234 SLICE_156.F1 to SLICE_122.C1 un1_flash_countlt21
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CTOF_DEL --- 0.495 SLICE_122.C1 to SLICE_122.F1 SLICE_122
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ROUTE 19 e 1.234 SLICE_122.F1 to SLICE_94.C1 un1_flash_countlt22
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CTOF_DEL --- 0.495 SLICE_94.C1 to SLICE_94.F1 SLICE_94
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ROUTE 4 e 1.234 SLICE_94.F1 to SLICE_121.CE un1_flash_count_1 (to sys_clock_c)
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--------
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11.306 (30.3% logic, 69.7% route), 7 logic levels.
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Report: 86.296MHz is the maximum frequency for this preference.
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================================================================================
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<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
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899 items scored, 204 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path exceeds requirements by 2.563ns (weighted slack = -17.941ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q rd[0] (from sys_clock_c +)
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Destination: FF Data in apple_module/D8/count[1] (to circuit_clk +)
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FF apple_module/D8/count[0]
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Delay: 12.281ns (31.9% logic, 68.1% route), 8 logic levels.
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Constraint Details:
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12.281ns physical path delay SLICE_122 to apple_module/D8/SLICE_78 exceeds
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(delay constraint based on source clock period of 40.000ns and destination clock period of 70.000ns)
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10.000ns delay constraint less
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0.282ns CE_SET requirement (totaling 9.718ns) by 2.563ns
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Physical Path Details:
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Data path SLICE_122 to apple_module/D8/SLICE_78:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 SLICE_122.CLK to SLICE_122.Q0 SLICE_122 (from sys_clock_c)
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ROUTE 2 e 1.234 SLICE_122.Q0 to */SLICE_126.A1 rd[0]
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CTOF_DEL --- 0.495 */SLICE_126.A1 to */SLICE_126.F1 apple_module/C8/SLICE_126
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ROUTE 1 e 0.480 */SLICE_126.F1 to */SLICE_126.A0 apple_module/C8/y2_1
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CTOF_DEL --- 0.495 */SLICE_126.A0 to */SLICE_126.F0 apple_module/C8/SLICE_126
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ROUTE 1 e 1.234 */SLICE_126.F0 to *e/SLICE_77.B0 apple_module/C8/y2_3
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CTOF_DEL --- 0.495 *e/SLICE_77.B0 to *e/SLICE_77.F0 apple_module/SLICE_77
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ROUTE 4 e 1.234 *e/SLICE_77.F0 to *e/SLICE_93.B1 apple_module/clear_char
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CTOF_DEL --- 0.495 *e/SLICE_93.B1 to *e/SLICE_93.F1 apple_module/SLICE_93
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ROUTE 1 e 0.480 *e/SLICE_93.F1 to *e/SLICE_93.A0 apple_module/un6_y1
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CTOF_DEL --- 0.495 *e/SLICE_93.A0 to *e/SLICE_93.F0 apple_module/SLICE_93
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ROUTE 5 e 1.234 *e/SLICE_93.F0 to */SLICE_152.D1 apple_module/wc1_i
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CTOF_DEL --- 0.495 */SLICE_152.D1 to */SLICE_152.F1 apple_module/SLICE_152
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ROUTE 5 e 1.234 */SLICE_152.F1 to */SLICE_141.C1 apple_module/load_v_i_0
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CTOF_DEL --- 0.495 */SLICE_141.C1 to */SLICE_141.F1 apple_module/SLICE_141
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ROUTE 2 e 1.234 */SLICE_141.F1 to *8/SLICE_78.CE apple_module/D8/count_cnv_0[0] (to circuit_clk)
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--------
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12.281 (31.9% logic, 68.1% route), 8 logic levels.
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Warning: 11.371MHz is the maximum frequency for this preference.
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================================================================================
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<A name="map_twr_pref_0_2"></A>Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
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1120 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 1.228ns (weighted slack = 4.912ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q apple_module/C13/states[3] (from circuit_clk +)
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Destination: DP8KC Port apple_module/C3/LineBuffer/sram_1_0_0_0(ASIC) (to apple_module/D10/y1 -)
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Delay: 8.823ns (33.2% logic, 66.8% route), 6 logic levels.
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Constraint Details:
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8.823ns physical path delay apple_module/SLICE_90 to apple_module/C3/LineBuffer/sram_1_0_0_0 meets
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(delay constraint based on source clock period of 70.000ns and destination clock period of 40.000ns)
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10.000ns delay constraint less
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-0.051ns DATA_SET requirement (totaling 10.051ns) by 1.228ns
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Physical Path Details:
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Data path apple_module/SLICE_90 to apple_module/C3/LineBuffer/sram_1_0_0_0:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 */SLICE_90.CLK to *e/SLICE_90.Q1 apple_module/SLICE_90 (from circuit_clk)
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ROUTE 5 e 0.480 *e/SLICE_90.Q1 to *e/SLICE_90.A1 apple_module/states[3]
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CTOF_DEL --- 0.495 *e/SLICE_90.A1 to *e/SLICE_90.F1 apple_module/SLICE_90
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ROUTE 2 e 1.234 *e/SLICE_90.F1 to *e/SLICE_77.A0 apple_module/y2_1
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CTOF_DEL --- 0.495 *e/SLICE_77.A0 to *e/SLICE_77.F0 apple_module/SLICE_77
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ROUTE 4 e 0.480 *e/SLICE_77.F0 to *e/SLICE_77.B1 apple_module/clear_char
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CTOF_DEL --- 0.495 *e/SLICE_77.B1 to *e/SLICE_77.F1 apple_module/SLICE_77
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ROUTE 8 e 1.234 *e/SLICE_77.F1 to */SLICE_117.C1 apple_module/clr
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CTOF_DEL --- 0.495 */SLICE_117.C1 to */SLICE_117.F1 apple_module/SLICE_117
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ROUTE 1 e 1.234 */SLICE_117.F1 to */SLICE_128.C1 apple_module/msb
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CTOF_DEL --- 0.495 */SLICE_128.C1 to */SLICE_128.F1 apple_module/SLICE_128
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ROUTE 1 e 1.234 */SLICE_128.F1 to *_1_0_0_0.DIA5 apple_module/C3/input[5] (to apple_module/D10/y1)
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--------
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8.823 (33.2% logic, 66.8% route), 6 logic levels.
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Report: 28.500MHz is the maximum frequency for this preference.
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<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY NET "sys_clock_c" 25.000000 | | |
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MHz ; | 25.000 MHz| 86.296 MHz| 7
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FREQUENCY NET "circuit_clk" 14.285714 | | |
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MHz ; | 14.286 MHz| 11.371 MHz| 8 *
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FREQUENCY PORT "sys_clock" 25.000000 | | |
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MHz ; | 25.000 MHz| 28.500 MHz| 6
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----------------------------------------------------------------------------
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1 preference(marked by "*" above) not met.
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----------------------------------------------------------------------------
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Critical Nets | Loads| Errors| % of total
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----------------------------------------------------------------------------
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apple_module/wc1_i | 5| 204| 100.00%
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apple_module/clear_char | 4| 204| 100.00%
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apple_module/un6_y1 | 1| 144| 70.59%
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apple_module/C8/y2_3 | 1| 138| 67.65%
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apple_module/load_v_i_0 | 5| 94| 46.08%
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apple_module/C8/y2_1 | 1| 72| 35.29%
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apple_module/y2_1 | 2| 66| 32.35%
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apple_module/D8/N_19 | 4| 40| 19.61%
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apple_module/count_5[0] | 4| 40| 19.61%
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rd[3] | 2| 36| 17.65%
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rd[0] | 2| 36| 17.65%
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apple_module/D8/count_cnv_0[0] | 2| 32| 15.69%
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apple_module/D9/count_cnv_1[0] | 2| 32| 15.69%
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apple_module/D9/N_19 | 3| 30| 14.71%
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rd[4] | 2| 22| 10.78%
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rd[2] | 2| 22| 10.78%
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rd[1] | 2| 22| 10.78%
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rd[5] | 2| 22| 10.78%
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apple_module/char_ready | 4| 22| 10.78%
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rd[6] | 3| 22| 10.78%
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----------------------------------------------------------------------------
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<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 8 clocks:
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Clock Domain: clock_module/CLKFB_t Source: clock_module/PLLInst_0.CLKINTFB Loads: 1
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No transfer within this clock domain is found
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Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
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No transfer within this clock domain is found
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Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1 Loads: 4
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
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Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
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Clock Domain: sys_clock_c Source: sys_clock.PAD
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0 Loads: 47
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 18
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Clock Domain: sys_clock_c Source: sys_clock.PAD
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 8
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Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
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No transfer within this clock domain is found
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Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS Loads: 24
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
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Data transfers from:
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Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 6
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 4
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Clock Domain: sys_clock_c Source: sys_clock.PAD
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 7
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Clock Domain: sys_clock_c Source: sys_clock.PAD Loads: 38
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Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
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Data transfers from:
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ; Transfers: 1
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<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
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---------------
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Timing errors: 204 Score: 1027544
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Cumulative negative slack: 1027544
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Constraints cover 3276 paths, 10 nets, and 1222 connections (98.39% coverage)
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--------------------------------------------------------------------------------
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<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.10.2.115</big></U></B>
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Thu Aug 08 18:39:21 2019
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o Apple1Display_impl1.tw1 -gui -msgset C:/Dev/Apple1Display/promote.xml Apple1Display_impl1_map.ncd Apple1Display_impl1.prf
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Design file: apple1display_impl1_map.ncd
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Preference file: apple1display_impl1.prf
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Device,speed: LCMXO2-7000HC,M
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
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<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY NET "sys_clock_c" 25.000000 MHz (0 errors)</A></LI> 1257 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY NET "circuit_clk" 14.285714 MHz (0 errors)</A></LI> 899 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "sys_clock" 25.000000 MHz (0 errors)</A></LI> 1120 items scored, 0 timing errors detected.
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
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1257 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.441ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q uart_module/r_SM_Main[1] (from sys_clock_c +)
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Destination: FF Data in uart_module/r_SM_Main[1] (to sys_clock_c +)
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Delay: 0.428ns (53.3% logic, 46.7% route), 2 logic levels.
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Constraint Details:
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0.428ns physical path delay uart_module/SLICE_115 to uart_module/SLICE_115 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.013ns) by 0.441ns
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Physical Path Details:
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Data path uart_module/SLICE_115 to uart_module/SLICE_115:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 *SLICE_115.CLK to */SLICE_115.Q0 uart_module/SLICE_115 (from sys_clock_c)
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ROUTE 9 e 0.199 */SLICE_115.Q0 to */SLICE_115.M0 uart_module/r_SM_Main[1]
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MTOOFX_DEL --- 0.095 */SLICE_115.M0 to *LICE_115.OFX0 uart_module/SLICE_115
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ROUTE 1 e 0.001 *LICE_115.OFX0 to *SLICE_115.DI0 uart_module/r_SM_Main_ns[1] (to sys_clock_c)
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--------
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0.428 (53.3% logic, 46.7% route), 2 logic levels.
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================================================================================
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<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
|
|
899 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.447ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q apple_module/D15/count[0] (from circuit_clk +)
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Destination: FF Data in apple_module/D15/count[2] (to circuit_clk +)
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Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
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Constraint Details:
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0.434ns physical path delay apple_module/D15/SLICE_71 to apple_module/D15/SLICE_71 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
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Physical Path Details:
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Data path apple_module/D15/SLICE_71 to apple_module/D15/SLICE_71:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 */SLICE_71.CLK to *5/SLICE_71.Q0 apple_module/D15/SLICE_71 (from circuit_clk)
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ROUTE 4 e 0.199 *5/SLICE_71.Q0 to *5/SLICE_71.B1 apple_module/D15/count[0]
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CTOF_DEL --- 0.101 *5/SLICE_71.B1 to *5/SLICE_71.F1 apple_module/D15/SLICE_71
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ROUTE 1 e 0.001 *5/SLICE_71.F1 to */SLICE_71.DI1 apple_module/D15/N_42_i (to circuit_clk)
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--------
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0.434 (53.9% logic, 46.1% route), 2 logic levels.
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================================================================================
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<A name="map_twr_pref_1_2"></A>Preference: FREQUENCY PORT "sys_clock" 25.000000 MHz ;
|
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1120 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.447ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q apple_module/D13/flash_counter[1] (from apple_module/D10/y3 +)
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Destination: FF Data in apple_module/D13/flash_counter[1] (to apple_module/D10/y3 +)
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Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
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Constraint Details:
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0.434ns physical path delay apple_module/D13/SLICE_68 to apple_module/D13/SLICE_68 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
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Physical Path Details:
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Data path apple_module/D13/SLICE_68 to apple_module/D13/SLICE_68:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 */SLICE_68.CLK to *3/SLICE_68.Q1 apple_module/D13/SLICE_68 (from apple_module/D10/y3)
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ROUTE 5 e 0.199 *3/SLICE_68.Q1 to *3/SLICE_68.B1 apple_module/D13/flash_counter[1]
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CTOF_DEL --- 0.101 *3/SLICE_68.B1 to *3/SLICE_68.F1 apple_module/D13/SLICE_68
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ROUTE 1 e 0.001 *3/SLICE_68.F1 to */SLICE_68.DI1 apple_module/D13/un3_flash_counter_1_axbxc1 (to apple_module/D10/y3)
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--------
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0.434 (53.9% logic, 46.1% route), 2 logic levels.
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<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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| | |
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FREQUENCY NET "sys_clock_c" 25.000000 | | |
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MHz ; | 0.000 ns| 0.441 ns| 2
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| | |
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FREQUENCY NET "circuit_clk" 14.285714 | | |
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MHz ; | 0.000 ns| 0.447 ns| 2
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| | |
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FREQUENCY PORT "sys_clock" 25.000000 | | |
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MHz ; | -| -| 2
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| | |
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----------------------------------------------------------------------------
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All preferences were met.
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<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 8 clocks:
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Clock Domain: clock_module/CLKFB_t Source: clock_module/PLLInst_0.CLKINTFB Loads: 1
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No transfer within this clock domain is found
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Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
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No transfer within this clock domain is found
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Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1 Loads: 4
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
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Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
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Clock Domain: sys_clock_c Source: sys_clock.PAD
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 7
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0 Loads: 47
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 18
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Clock Domain: sys_clock_c Source: sys_clock.PAD
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Covered under: FREQUENCY PORT "sys_clock" 25.000000 MHz ; Transfers: 8
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Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
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No transfer within this clock domain is found
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Data transfers from:
|
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Clock Domain: apple_module/D10/y3 Source: apple_module/SLICE_152.F0 Loads: 4
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No transfer within this clock domain is found
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Clock Domain: circuit_clk Source: clock_module/PLLInst_0.CLKOS Loads: 24
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ;
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Data transfers from:
|
|
Clock Domain: apple_module/D10/y1 Source: apple_module/SLICE_82.F1
|
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 6
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 1
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Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 4
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Clock Domain: sys_clock_c Source: sys_clock.PAD
|
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Covered under: FREQUENCY NET "circuit_clk" 14.285714 MHz ; Transfers: 7
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|
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Clock Domain: sys_clock_c Source: sys_clock.PAD Loads: 38
|
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Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ;
|
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|
|
Data transfers from:
|
|
Clock Domain: apple_module/C5/y1 Source: apple_module/SLICE_127.F0
|
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Covered under: FREQUENCY NET "sys_clock_c" 25.000000 MHz ; Transfers: 1
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<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
|
---------------
|
|
|
|
Timing errors: 0 Score: 0
|
|
Cumulative negative slack: 0
|
|
|
|
Constraints cover 3276 paths, 10 nets, and 1222 connections (98.39% coverage)
|
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|
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<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
|
---------------
|
|
|
|
Timing errors: 204 (setup), 0 (hold)
|
|
Score: 1027544 (setup), 0 (hold)
|
|
Cumulative negative slack: 1027544 (1027544+0)
|
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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