922 lines
62 KiB
Plaintext
922 lines
62 KiB
Plaintext
# Mon Aug 5 13:38:43 2019
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Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 11:10:16
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Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version M-2017.03L-SP1-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 101MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 101MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Adding property syn_ta_report_clock_domain_crossing, value 0 to view:work.FleaFPGA_Uno_E1(arch)
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Adding property syn_ta_max_display_worst_paths, value 5 to view:work.FleaFPGA_Uno_E1(arch)
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Start Timing Analyst (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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@W: MT246 :"c:\dev\apple1display\impl1\master_clk.vhd":109:4:109:12|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
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@W: MT420 |Found inferred clock apple1display|line_clock_inferred_clock with period 6.07ns. Please declare a user-defined clock on object "n:apple_module.line_clock"
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@W: MT420 |Found inferred clock apple1display|mem0_inferred_clock with period 3.71ns. Please declare a user-defined clock on object "n:apple_module.mem0"
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@W: MT420 |Found inferred clock dm7400|y2_1_inferred_clock with period 3.76ns. Please declare a user-defined clock on object "n:apple_module.D10.y2_1"
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##### START OF TIMING REPORT #####[
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# Timing Report written on Mon Aug 5 13:38:43 2019
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#
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Top view: FleaFPGA_Uno_E1
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Requested Frequency: 164.6 MHz
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Wire load mode: top
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Paths requested: 5
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Constraint File(s):
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@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
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@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
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Performance Summary
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*******************
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Worst slack in design: -1.072
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Requested Estimated Requested Estimated Clock Clock
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Starting Clock Frequency Frequency Period Period Slack Type Group
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--------------------------------------------------------------------------------------------------------------------------------------------------
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apple1display|line_clock_inferred_clock 164.6 MHz 139.9 MHz 6.074 7.146 -1.072 inferred Autoconstr_clkgroup_4
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apple1display|mem0_inferred_clock 269.3 MHz 228.9 MHz 3.713 4.368 -0.655 inferred Autoconstr_clkgroup_3
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dm7400|y2_1_inferred_clock 265.9 MHz 226.0 MHz 3.761 4.424 -0.664 inferred Autoconstr_clkgroup_1
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System 1.0 MHz 194.8 MHz 1000.000 5.134 994.866 system system_clkgroup
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==================================================================================================================================================
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Clock Relationships
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*******************
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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System System | 1000.000 994.866 | No paths - | No paths - | No paths -
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System apple1display|mem0_inferred_clock | No paths - | No paths - | 3.713 1.929 | No paths -
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System apple1display|line_clock_inferred_clock | No paths - | No paths - | 6.074 1.032 | No paths -
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dm7400|y2_1_inferred_clock dm7400|y2_1_inferred_clock | 3.761 -0.053 | 3.761 -0.664 | No paths - | No paths -
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dm7400|y2_1_inferred_clock apple1display|mem0_inferred_clock | No paths - | Diff grp - | No paths - | No paths -
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dm7400|y2_1_inferred_clock apple1display|line_clock_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths -
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apple1display|mem0_inferred_clock System | No paths - | No paths - | No paths - | 3.713 1.798
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apple1display|mem0_inferred_clock dm7400|y2_1_inferred_clock | No paths - | Diff grp - | No paths - | No paths -
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apple1display|mem0_inferred_clock apple1display|mem0_inferred_clock | No paths - | 3.713 -0.655 | No paths - | No paths -
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apple1display|mem0_inferred_clock apple1display|line_clock_inferred_clock | No paths - | Diff grp - | No paths - | No paths -
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apple1display|line_clock_inferred_clock System | No paths - | No paths - | No paths - | 6.074 0.015
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apple1display|line_clock_inferred_clock apple1display|line_clock_inferred_clock | No paths - | 6.074 -1.072 | No paths - | No paths -
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===========================================================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Interface Information
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*********************
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No IO constraint found
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====================================
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Detailed Report for Clock: apple1display|line_clock_inferred_clock
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====================================
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Starting Points with Worst Slack
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********************************
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
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Clock
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------------------------------------------------------------------------------------------------------------------------------------------------
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DOA0 screen_char[0] 4.377 -1.072
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DOA1 screen_char[1] 4.377 -1.072
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DOA2 screen_char[2] 4.377 -1.072
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DOA3 screen_char[3] 4.377 -1.072
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DOA4 screen_char[4] 4.377 -1.072
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================================================================================================================================================
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Ending Points with Worst Slack
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******************************
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Starting Required
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Instance Reference Type Pin Net Time Slack
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Clock
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-------------------------------------------------------------------------------------------------------------------------------------------
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DIA0 input[0] 4.321 -1.072
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DIA1 input[1] 4.321 -1.072
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DIA2 input[2] 4.321 -1.072
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DIA3 input[3] 4.321 -1.072
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apple_module.C3.LineBuffer.sram_1_0_0_0 apple1display|line_clock_inferred_clock DP8KC DIA4 input[4] 4.321 -1.072
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===========================================================================================================================================
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Worst Path Information
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***********************
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Path information for path number 1:
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Requested Period: 6.074
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- Setup time: 1.753
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 4.321
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- Propagation time: 5.393
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : -1.072
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Number of logic level(s): 1
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Starting point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DOA0
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Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA0
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The start point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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--------------------------------------------------------------------------------------------------------------
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DOA0 Out 4.377 4.377 -
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screen_char[0] Net - - - - 2
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apple_module.C3.LineBuffer.sram_1_0_0_0_RNO ORCALUT4 C In 0.000 4.377 -
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apple_module.C3.LineBuffer.sram_1_0_0_0_RNO ORCALUT4 Z Out 1.017 5.393 -
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input[0] Net - - - - 1
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA0 In 0.000 5.393 -
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==============================================================================================================
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Path information for path number 2:
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Requested Period: 6.074
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- Setup time: 1.753
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 4.321
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- Propagation time: 5.393
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : -1.072
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Number of logic level(s): 1
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Starting point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DOA1
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Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA1
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The start point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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--------------------------------------------------------------------------------------------------------------
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DOA1 Out 4.377 4.377 -
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screen_char[1] Net - - - - 2
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apple_module.C3.LineBuffer.sram_1_0_0_RNO_0 ORCALUT4 C In 0.000 4.377 -
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apple_module.C3.LineBuffer.sram_1_0_0_RNO_0 ORCALUT4 Z Out 1.017 5.393 -
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input[1] Net - - - - 1
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA1 In 0.000 5.393 -
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==============================================================================================================
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Path information for path number 3:
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Requested Period: 6.074
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- Setup time: 1.753
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 4.321
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- Propagation time: 5.393
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : -1.072
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Number of logic level(s): 1
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Starting point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DOA2
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Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA2
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The start point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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--------------------------------------------------------------------------------------------------------------
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DOA2 Out 4.377 4.377 -
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screen_char[2] Net - - - - 2
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apple_module.C3.LineBuffer.sram_1_0_0_RNO_1 ORCALUT4 C In 0.000 4.377 -
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apple_module.C3.LineBuffer.sram_1_0_0_RNO_1 ORCALUT4 Z Out 1.017 5.393 -
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input[2] Net - - - - 1
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA2 In 0.000 5.393 -
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==============================================================================================================
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Path information for path number 4:
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Requested Period: 6.074
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- Setup time: 1.753
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 4.321
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- Propagation time: 5.393
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : -1.072
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Number of logic level(s): 1
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Starting point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DOA3
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Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA3
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The start point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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--------------------------------------------------------------------------------------------------------------
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DOA3 Out 4.377 4.377 -
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screen_char[3] Net - - - - 2
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apple_module.C3.LineBuffer.sram_1_0_0_RNO_2 ORCALUT4 C In 0.000 4.377 -
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apple_module.C3.LineBuffer.sram_1_0_0_RNO_2 ORCALUT4 Z Out 1.017 5.393 -
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input[3] Net - - - - 1
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA3 In 0.000 5.393 -
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==============================================================================================================
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Path information for path number 5:
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Requested Period: 6.074
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- Setup time: 1.753
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 4.321
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- Propagation time: 5.393
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : -1.072
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Number of logic level(s): 1
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Starting point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DOA4
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Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA4
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The start point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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--------------------------------------------------------------------------------------------------------------
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DOA4 Out 4.377 4.377 -
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screen_char[4] Net - - - - 2
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apple_module.C3.LineBuffer.sram_1_0_0_RNO_3 ORCALUT4 C In 0.000 4.377 -
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apple_module.C3.LineBuffer.sram_1_0_0_RNO_3 ORCALUT4 Z Out 1.017 5.393 -
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input[4] Net - - - - 1
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apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA4 In 0.000 5.393 -
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==============================================================================================================
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====================================
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Detailed Report for Clock: apple1display|mem0_inferred_clock
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====================================
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Starting Points with Worst Slack
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********************************
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
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Clock
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---------------------------------------------------------------------------------------------------------------------------------
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apple_module.ScreenBuffer.FF_1 apple1display|mem0_inferred_clock FD1P3DX Q shreg_addr_w8 1.347 -0.655
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apple_module.ScreenBuffer.FF_2 apple1display|mem0_inferred_clock FD1P3DX Q shreg_addr_w7 1.347 -0.655
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apple_module.ScreenBuffer.FF_3 apple1display|mem0_inferred_clock FD1P3DX Q shreg_addr_w6 1.347 -0.655
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apple_module.ScreenBuffer.FF_4 apple1display|mem0_inferred_clock FD1P3DX Q shreg_addr_w5 1.347 -0.655
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apple_module.ScreenBuffer.FF_5 apple1display|mem0_inferred_clock FD1P3DX Q shreg_addr_w4 1.347 -0.655
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=================================================================================================================================
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Ending Points with Worst Slack
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******************************
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Starting Required
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Instance Reference Type Pin Net Time Slack
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Clock
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--------------------------------------------------------------------------------------------------------------------------------------
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apple_module.ScreenBuffer.sram_1_0_0 apple1display|mem0_inferred_clock SPR16X4C WRE dec0_wre3 3.713 -0.655
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apple_module.ScreenBuffer.sram_1_0_1 apple1display|mem0_inferred_clock SPR16X4C WRE dec0_wre3 3.713 -0.655
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apple_module.ScreenBuffer.sram_1_1_0 apple1display|mem0_inferred_clock SPR16X4C WRE dec1_wre7 3.713 -0.655
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apple_module.ScreenBuffer.sram_1_1_1 apple1display|mem0_inferred_clock SPR16X4C WRE dec1_wre7 3.713 -0.655
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apple_module.ScreenBuffer.sram_1_2_0 apple1display|mem0_inferred_clock SPR16X4C WRE dec2_wre11 3.713 -0.655
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======================================================================================================================================
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Worst Path Information
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***********************
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Path information for path number 1:
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Requested Period: 3.713
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- Setup time: 0.000
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 3.713
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- Propagation time: 4.368
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (non-critical) : -0.655
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Number of logic level(s): 3
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Starting point: apple_module.ScreenBuffer.FF_1 / Q
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Ending point: apple_module.ScreenBuffer.sram_1_47_0 / WRE
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The start point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
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The end point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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--------------------------------------------------------------------------------------------------------
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apple_module.ScreenBuffer.FF_1 FD1P3DX Q Out 1.347 1.347 -
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shreg_addr_w8 Net - - - - 46
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apple_module.ScreenBuffer.INV_1 INV A In 0.000 1.347 -
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apple_module.ScreenBuffer.INV_1 INV Z Out 0.915 2.262 -
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shreg_addr_w8_inv Net - - - - 32
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apple_module.ScreenBuffer.LUT4_49 ROM16X1A AD1 In 0.000 2.262 -
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apple_module.ScreenBuffer.LUT4_49 ROM16X1A DO0 Out 1.017 3.279 -
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func_and_inet_95 Net - - - - 1
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apple_module.ScreenBuffer.LUT4_48 ROM16X1A AD2 In 0.000 3.279 -
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apple_module.ScreenBuffer.LUT4_48 ROM16X1A DO0 Out 1.089 4.368 -
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dec47_wre191 Net - - - - 2
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apple_module.ScreenBuffer.sram_1_47_0 SPR16X4C WRE In 0.000 4.368 -
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========================================================================================================
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Path information for path number 2:
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Requested Period: 3.713
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- Setup time: 0.000
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 3.713
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- Propagation time: 4.368
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (non-critical) : -0.655
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Number of logic level(s): 3
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Starting point: apple_module.ScreenBuffer.FF_2 / Q
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Ending point: apple_module.ScreenBuffer.sram_1_55_0 / WRE
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The start point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
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The end point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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--------------------------------------------------------------------------------------------------------
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apple_module.ScreenBuffer.FF_2 FD1P3DX Q Out 1.347 1.347 -
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shreg_addr_w7 Net - - - - 46
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apple_module.ScreenBuffer.INV_2 INV A In 0.000 1.347 -
|
|
apple_module.ScreenBuffer.INV_2 INV Z Out 0.915 2.262 -
|
|
shreg_addr_w7_inv Net - - - - 32
|
|
apple_module.ScreenBuffer.LUT4_25 ROM16X1A AD2 In 0.000 2.262 -
|
|
apple_module.ScreenBuffer.LUT4_25 ROM16X1A DO0 Out 1.017 3.279 -
|
|
func_and_inet_111 Net - - - - 1
|
|
apple_module.ScreenBuffer.LUT4_24 ROM16X1A AD2 In 0.000 3.279 -
|
|
apple_module.ScreenBuffer.LUT4_24 ROM16X1A DO0 Out 1.089 4.368 -
|
|
dec55_wre223 Net - - - - 2
|
|
apple_module.ScreenBuffer.sram_1_55_0 SPR16X4C WRE In 0.000 4.368 -
|
|
========================================================================================================
|
|
|
|
|
|
Path information for path number 3:
|
|
Requested Period: 3.713
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 3.713
|
|
|
|
- Propagation time: 4.368
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.655
|
|
|
|
Number of logic level(s): 3
|
|
Starting point: apple_module.ScreenBuffer.FF_3 / Q
|
|
Ending point: apple_module.ScreenBuffer.sram_1_59_0 / WRE
|
|
The start point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
|
|
The end point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------
|
|
apple_module.ScreenBuffer.FF_3 FD1P3DX Q Out 1.347 1.347 -
|
|
shreg_addr_w6 Net - - - - 46
|
|
apple_module.ScreenBuffer.INV_3 INV A In 0.000 1.347 -
|
|
apple_module.ScreenBuffer.INV_3 INV Z Out 0.915 2.262 -
|
|
shreg_addr_w6_inv Net - - - - 32
|
|
apple_module.ScreenBuffer.LUT4_13 ROM16X1A AD3 In 0.000 2.262 -
|
|
apple_module.ScreenBuffer.LUT4_13 ROM16X1A DO0 Out 1.017 3.279 -
|
|
func_and_inet_119 Net - - - - 1
|
|
apple_module.ScreenBuffer.LUT4_12 ROM16X1A AD2 In 0.000 3.279 -
|
|
apple_module.ScreenBuffer.LUT4_12 ROM16X1A DO0 Out 1.089 4.368 -
|
|
dec59_wre239 Net - - - - 2
|
|
apple_module.ScreenBuffer.sram_1_59_0 SPR16X4C WRE In 0.000 4.368 -
|
|
========================================================================================================
|
|
|
|
|
|
Path information for path number 4:
|
|
Requested Period: 3.713
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 3.713
|
|
|
|
- Propagation time: 4.368
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.655
|
|
|
|
Number of logic level(s): 3
|
|
Starting point: apple_module.ScreenBuffer.FF_4 / Q
|
|
Ending point: apple_module.ScreenBuffer.sram_1_61_0 / WRE
|
|
The start point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
|
|
The end point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------
|
|
apple_module.ScreenBuffer.FF_4 FD1P3DX Q Out 1.347 1.347 -
|
|
shreg_addr_w5 Net - - - - 46
|
|
apple_module.ScreenBuffer.INV_4 INV A In 0.000 1.347 -
|
|
apple_module.ScreenBuffer.INV_4 INV Z Out 0.915 2.262 -
|
|
shreg_addr_w5_inv Net - - - - 32
|
|
apple_module.ScreenBuffer.LUT4_8 ROM16X1A AD0 In 0.000 2.262 -
|
|
apple_module.ScreenBuffer.LUT4_8 ROM16X1A DO0 Out 1.017 3.279 -
|
|
func_and_inet_122 Net - - - - 1
|
|
apple_module.ScreenBuffer.LUT4_6 ROM16X1A AD3 In 0.000 3.279 -
|
|
apple_module.ScreenBuffer.LUT4_6 ROM16X1A DO0 Out 1.089 4.368 -
|
|
dec61_wre247 Net - - - - 2
|
|
apple_module.ScreenBuffer.sram_1_61_0 SPR16X4C WRE In 0.000 4.368 -
|
|
========================================================================================================
|
|
|
|
|
|
Path information for path number 5:
|
|
Requested Period: 3.713
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 3.713
|
|
|
|
- Propagation time: 4.368
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.655
|
|
|
|
Number of logic level(s): 3
|
|
Starting point: apple_module.ScreenBuffer.FF_5 / Q
|
|
Ending point: apple_module.ScreenBuffer.sram_1_62_0 / WRE
|
|
The start point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
|
|
The end point is clocked by apple1display|mem0_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------
|
|
apple_module.ScreenBuffer.FF_5 FD1P3DX Q Out 1.347 1.347 -
|
|
shreg_addr_w4 Net - - - - 46
|
|
apple_module.ScreenBuffer.INV_5 INV A In 0.000 1.347 -
|
|
apple_module.ScreenBuffer.INV_5 INV Z Out 0.915 2.262 -
|
|
shreg_addr_w4_inv Net - - - - 32
|
|
apple_module.ScreenBuffer.LUT4_5 ROM16X1A AD1 In 0.000 2.262 -
|
|
apple_module.ScreenBuffer.LUT4_5 ROM16X1A DO0 Out 1.017 3.279 -
|
|
func_and_inet_124 Net - - - - 1
|
|
apple_module.ScreenBuffer.LUT4_3 ROM16X1A AD3 In 0.000 3.279 -
|
|
apple_module.ScreenBuffer.LUT4_3 ROM16X1A DO0 Out 1.089 4.368 -
|
|
dec62_wre251 Net - - - - 2
|
|
apple_module.ScreenBuffer.sram_1_62_0 SPR16X4C WRE In 0.000 4.368 -
|
|
========================================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: dm7400|y2_1_inferred_clock
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
--------------------------------------------------------------------------------------------------------------------
|
|
apple_module.char_num[30] dm7400|y2_1_inferred_clock FD1P3AX Q char_num[30] 1.236 -0.664
|
|
apple_module.char_num[28] dm7400|y2_1_inferred_clock FD1P3AX Q char_num[28] 1.232 -0.660
|
|
apple_module.char_num[27] dm7400|y2_1_inferred_clock FD1P3AX Q char_num[27] 1.228 -0.656
|
|
apple_module.char_num[29] dm7400|y2_1_inferred_clock FD1P3AX Q un13lto2 1.228 -0.656
|
|
apple_module.char_num[31] dm7400|y2_1_inferred_clock FD1S3AY Q char_num[31] 1.204 -0.632
|
|
====================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
---------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.char_out[0] dm7400|y2_1_inferred_clock FD1P3IX CD un13lto5_c_RNITO581 2.958 -0.664
|
|
apple_module.char_out[1] dm7400|y2_1_inferred_clock FD1P3IX CD un13lto5_c_RNITO581 2.958 -0.664
|
|
apple_module.char_out[2] dm7400|y2_1_inferred_clock FD1P3IX CD un13lto5_c_RNITO581 2.958 -0.664
|
|
apple_module.char_out[3] dm7400|y2_1_inferred_clock FD1P3IX CD un13lto5_c_RNITO581 2.958 -0.664
|
|
apple_module.char_out[4] dm7400|y2_1_inferred_clock FD1P3IX CD un13lto5_c_RNITO581 2.958 -0.664
|
|
===========================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 3.761
|
|
- Setup time: 0.803
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 2.958
|
|
|
|
- Propagation time: 3.621
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.664
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.char_num[30] / Q
|
|
Ending point: apple_module.char_out[0] / CD
|
|
The start point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
The end point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
---------------------------------------------------------------------------------------------------
|
|
apple_module.char_num[30] FD1P3AX Q Out 1.236 1.236 -
|
|
char_num[30] Net - - - - 11
|
|
apple_module.un13lto5_d ORCALUT4 A In 0.000 1.236 -
|
|
apple_module.un13lto5_d ORCALUT4 Z Out 1.153 2.389 -
|
|
un13lto5_d Net - - - - 3
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 D In 0.000 2.389 -
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 Z Out 1.233 3.621 -
|
|
un13lto5_c_RNITO581 Net - - - - 6
|
|
apple_module.char_out[0] FD1P3IX CD In 0.000 3.621 -
|
|
===================================================================================================
|
|
|
|
|
|
Path information for path number 2:
|
|
Requested Period: 3.761
|
|
- Setup time: 0.803
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 2.958
|
|
|
|
- Propagation time: 3.621
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.664
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.char_num[30] / Q
|
|
Ending point: apple_module.char_out[6] / CD
|
|
The start point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
The end point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
---------------------------------------------------------------------------------------------------
|
|
apple_module.char_num[30] FD1P3AX Q Out 1.236 1.236 -
|
|
char_num[30] Net - - - - 11
|
|
apple_module.un13lto5_d ORCALUT4 A In 0.000 1.236 -
|
|
apple_module.un13lto5_d ORCALUT4 Z Out 1.153 2.389 -
|
|
un13lto5_d Net - - - - 3
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 D In 0.000 2.389 -
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 Z Out 1.233 3.621 -
|
|
un13lto5_c_RNITO581 Net - - - - 6
|
|
apple_module.char_out[6] FD1P3IX CD In 0.000 3.621 -
|
|
===================================================================================================
|
|
|
|
|
|
Path information for path number 3:
|
|
Requested Period: 3.761
|
|
- Setup time: 0.803
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 2.958
|
|
|
|
- Propagation time: 3.621
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.664
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.char_num[30] / Q
|
|
Ending point: apple_module.char_out[4] / CD
|
|
The start point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
The end point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
---------------------------------------------------------------------------------------------------
|
|
apple_module.char_num[30] FD1P3AX Q Out 1.236 1.236 -
|
|
char_num[30] Net - - - - 11
|
|
apple_module.un13lto5_d ORCALUT4 A In 0.000 1.236 -
|
|
apple_module.un13lto5_d ORCALUT4 Z Out 1.153 2.389 -
|
|
un13lto5_d Net - - - - 3
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 D In 0.000 2.389 -
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 Z Out 1.233 3.621 -
|
|
un13lto5_c_RNITO581 Net - - - - 6
|
|
apple_module.char_out[4] FD1P3IX CD In 0.000 3.621 -
|
|
===================================================================================================
|
|
|
|
|
|
Path information for path number 4:
|
|
Requested Period: 3.761
|
|
- Setup time: 0.803
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 2.958
|
|
|
|
- Propagation time: 3.621
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.664
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.char_num[30] / Q
|
|
Ending point: apple_module.char_out[3] / CD
|
|
The start point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
The end point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
---------------------------------------------------------------------------------------------------
|
|
apple_module.char_num[30] FD1P3AX Q Out 1.236 1.236 -
|
|
char_num[30] Net - - - - 11
|
|
apple_module.un13lto5_d ORCALUT4 A In 0.000 1.236 -
|
|
apple_module.un13lto5_d ORCALUT4 Z Out 1.153 2.389 -
|
|
un13lto5_d Net - - - - 3
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 D In 0.000 2.389 -
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 Z Out 1.233 3.621 -
|
|
un13lto5_c_RNITO581 Net - - - - 6
|
|
apple_module.char_out[3] FD1P3IX CD In 0.000 3.621 -
|
|
===================================================================================================
|
|
|
|
|
|
Path information for path number 5:
|
|
Requested Period: 3.761
|
|
- Setup time: 0.803
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 2.958
|
|
|
|
- Propagation time: 3.621
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.664
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.char_num[30] / Q
|
|
Ending point: apple_module.char_out[2] / CD
|
|
The start point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
The end point is clocked by dm7400|y2_1_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
---------------------------------------------------------------------------------------------------
|
|
apple_module.char_num[30] FD1P3AX Q Out 1.236 1.236 -
|
|
char_num[30] Net - - - - 11
|
|
apple_module.un13lto5_d ORCALUT4 A In 0.000 1.236 -
|
|
apple_module.un13lto5_d ORCALUT4 Z Out 1.153 2.389 -
|
|
un13lto5_d Net - - - - 3
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 D In 0.000 2.389 -
|
|
apple_module.un13lto5_c_RNITO581 ORCALUT4 Z Out 1.233 3.621 -
|
|
un13lto5_c_RNITO581 Net - - - - 6
|
|
apple_module.char_out[2] FD1P3IX CD In 0.000 3.621 -
|
|
===================================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: System
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
----------------------------------------------------------------------------------------------------------
|
|
apple_module.C13.states[3] System FD1S3AX Q states[3] 1.256 1.032
|
|
apple_module.D7.count[3] System FD1S3AX Q horz_count_upper[3] 1.244 1.612
|
|
apple_module.D8.count[0] System FD1S3DX Q count[0] 1.204 1.652
|
|
apple_module.D8.count[1] System FD1S3DX Q count[1] 1.188 1.668
|
|
apple_module.D8.count[2] System FD1S3DX Q count[2] 1.180 1.676
|
|
==========================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
------------------------------------------------------------------------------------------------------------
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 System DP8KC DIA0 input[0] 4.321 1.032
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 System DP8KC DIA1 input[1] 4.321 1.032
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 System DP8KC DIA2 input[2] 4.321 1.032
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 System DP8KC DIA3 input[3] 4.321 1.032
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 System DP8KC DIA4 input[4] 4.321 1.032
|
|
============================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 6.074
|
|
- Setup time: 1.753
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 4.321
|
|
|
|
- Propagation time: 3.289
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : 1.032
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.C13.states[3] / Q
|
|
Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA2
|
|
The start point is clocked by System [rising] on pin CK
|
|
The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------
|
|
apple_module.C13.states[3] FD1S3AX Q Out 1.256 1.256 -
|
|
states[3] Net - - - - 14
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_5 ORCALUT4 A In 0.000 1.256 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_5 ORCALUT4 Z Out 1.017 2.273 -
|
|
sram_1_0_0_RNO_5 Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_1 ORCALUT4 A In 0.000 2.273 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_1 ORCALUT4 Z Out 1.017 3.289 -
|
|
input[2] Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA2 In 0.000 3.289 -
|
|
==============================================================================================================
|
|
|
|
|
|
Path information for path number 2:
|
|
Requested Period: 6.074
|
|
- Setup time: 1.753
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 4.321
|
|
|
|
- Propagation time: 3.289
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : 1.032
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.C13.states[3] / Q
|
|
Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA4
|
|
The start point is clocked by System [rising] on pin CK
|
|
The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------
|
|
apple_module.C13.states[3] FD1S3AX Q Out 1.256 1.256 -
|
|
states[3] Net - - - - 14
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_7 ORCALUT4 A In 0.000 1.256 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_7 ORCALUT4 Z Out 1.017 2.273 -
|
|
sram_1_0_0_RNO_7 Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_3 ORCALUT4 A In 0.000 2.273 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_3 ORCALUT4 Z Out 1.017 3.289 -
|
|
input[4] Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA4 In 0.000 3.289 -
|
|
==============================================================================================================
|
|
|
|
|
|
Path information for path number 3:
|
|
Requested Period: 6.074
|
|
- Setup time: 1.753
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 4.321
|
|
|
|
- Propagation time: 3.289
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : 1.032
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.C13.states[3] / Q
|
|
Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA1
|
|
The start point is clocked by System [rising] on pin CK
|
|
The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
---------------------------------------------------------------------------------------------------------------
|
|
apple_module.C13.states[3] FD1S3AX Q Out 1.256 1.256 -
|
|
states[3] Net - - - - 14
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_10 ORCALUT4 A In 0.000 1.256 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_10 ORCALUT4 Z Out 1.017 2.273 -
|
|
sram_1_0_0_RNO_10 Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_0 ORCALUT4 B In 0.000 2.273 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_0 ORCALUT4 Z Out 1.017 3.289 -
|
|
input[1] Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA1 In 0.000 3.289 -
|
|
===============================================================================================================
|
|
|
|
|
|
Path information for path number 4:
|
|
Requested Period: 6.074
|
|
- Setup time: 1.753
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 4.321
|
|
|
|
- Propagation time: 3.289
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : 1.032
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.C13.states[3] / Q
|
|
Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA3
|
|
The start point is clocked by System [rising] on pin CK
|
|
The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------
|
|
apple_module.C13.states[3] FD1S3AX Q Out 1.256 1.256 -
|
|
states[3] Net - - - - 14
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_6 ORCALUT4 A In 0.000 1.256 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_6 ORCALUT4 Z Out 1.017 2.273 -
|
|
sram_1_0_0_RNO_6 Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_2 ORCALUT4 A In 0.000 2.273 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_2 ORCALUT4 Z Out 1.017 3.289 -
|
|
input[3] Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA3 In 0.000 3.289 -
|
|
==============================================================================================================
|
|
|
|
|
|
Path information for path number 5:
|
|
Requested Period: 6.074
|
|
- Setup time: 1.753
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 4.321
|
|
|
|
- Propagation time: 3.289
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : 1.032
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: apple_module.C13.states[3] / Q
|
|
Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA0
|
|
The start point is clocked by System [rising] on pin CK
|
|
The end point is clocked by apple1display|line_clock_inferred_clock [falling] on pin CLKA
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------
|
|
apple_module.C13.states[3] FD1S3AX Q Out 1.256 1.256 -
|
|
states[3] Net - - - - 14
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_9 ORCALUT4 A In 0.000 1.256 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_RNO_9 ORCALUT4 Z Out 1.017 2.273 -
|
|
sram_1_0_0_RNO_9 Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0_RNO ORCALUT4 B In 0.000 2.273 -
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0_RNO ORCALUT4 Z Out 1.017 3.289 -
|
|
input[0] Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA0 In 0.000 3.289 -
|
|
==============================================================================================================
|
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
|
|
|
Timing exceptions that could not be applied
|
|
None
|
|
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
|
|
|
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
|
|
|
Writing Analyst data base C:\Dev\Apple1Display\impl1\impl1_ta.srm
|
|
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
|
|
|
Mapper successful!
|
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 143MB)
|
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
|
# Mon Aug 5 13:38:44 2019
|
|
|
|
###########################################################]
|