mirror of
https://github.com/Myndale/Apple1Display.git
synced 2024-06-06 06:29:27 +00:00
730 lines
51 KiB
Plaintext
730 lines
51 KiB
Plaintext
# Thu Aug 8 18:39:12 2019
|
|
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 11:10:16
|
|
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
|
Product Version M-2017.03L-SP1-1
|
|
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
|
|
|
@N: MF248 |Running in 64-bit mode.
|
|
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
|
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
|
|
|
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
|
|
|
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
|
|
|
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
|
|
|
|
|
|
|
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
|
|
|
|
|
Available hyper_sources - for debug and ip models
|
|
None Found
|
|
|
|
@N: FX493 |Applying initial value "00000000" on instance uart_module.r_RX_Byte[7:0].
|
|
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
|
|
|
@N: BN362 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Removing sequential instance flash_count[22] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74160.vhd":25:2:25:3|Found counter in view:work.apple1display(behavior) instance D6.count[3:0]
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_3(behavior) instance count[3:0]
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_2(behavior) instance count[3:0]
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_1(behavior) instance count[3:0]
|
|
@N: MO231 :"c:\dev\apple1display\ttl\dm74161.vhd":25:2:25:3|Found counter in view:work.dm74161_0(behavior) instance count[3:0]
|
|
Encoding state machine r_SM_Main[0:4] (in view: work.UART_RX(rtl))
|
|
original code -> new code
|
|
00001 -> 000
|
|
00010 -> 001
|
|
00100 -> 010
|
|
01000 -> 011
|
|
10000 -> 100
|
|
|
|
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
|
|
|
|
|
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
|
|
|
|
|
Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
|
|
|
|
@N: BN362 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Removing sequential instance apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) because it does not drive other instances.
|
|
@A: BN291 :"c:\dev\apple1display\ttl\dm74175.vhd":29:2:29:3|Boundary register apple_module.C13.states[0] (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
|
|
|
|
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
|
|
|
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
|
|
|
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
|
|
|
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
|
|
|
|
|
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
|
|
|
|
|
|
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 147MB)
|
|
|
|
Pass CPU time Worst Slack Luts / Registers
|
|
------------------------------------------------------------
|
|
1 0h:00m:01s 990.85ns 151 / 99
|
|
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 147MB)
|
|
|
|
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_6_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_5_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_4_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_3_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_2_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_1_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
@A: BN291 :"c:\dev\apple1display\impl1\source\fleafpga_uno_top.vhd":165:2:165:3|Boundary register rd_0_.fb (in view: work.FleaFPGA_Uno_E1(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
|
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 147MB)
|
|
|
|
@N: MT611 :|Automatically generated clock master_clk|CLKOS_inferred_clock is not used and is being removed
|
|
@N: MT611 :|Automatically generated clock dm74175|q0_i_inferred_clock is not used and is being removed
|
|
@N: MT617 :|Automatically generated clock dm74161_4|count_derived_clock[3] has lost its master clock dm74175|q0_i_inferred_clock and is being removed
|
|
|
|
|
|
@S |Clock Optimization Summary
|
|
|
|
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
|
|
|
1 non-gated/non-generated clock tree(s) driving 54 clock pin(s) of sequential element(s)
|
|
4 gated/generated clock tree(s) driving 131 clock pin(s) of sequential element(s)
|
|
0 instances converted, 131 sequential instances remain driven by gated/generated clocks
|
|
|
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
|
---------------------------------------------------------------------------------------
|
|
@K:CKID0005 sys_clock port 54 flash_count[0]
|
|
=======================================================================================
|
|
===================================================================================================================== Gated/Generated Clocks ======================================================================================================================
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
@K:CKID0001 clock_module.PLLInst_0 EHXPLLJ 35 apple_module.D1.Qd Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
|
|
@K:CKID0002 apple_module.C5.y1 ORCALUT4 83 apple_module.C7.states[5] Multiple clocks on instance from nets line_clock, vbl_i
|
|
@K:CKID0003 apple_module.D10.y1 ORCALUT4 7 apple_module.C3.LineBuffer.FF_0 No gated clock conversion method for cell cell:LUCENT.FD1P3IX
|
|
@K:CKID0004 apple_module.D10.y3_inferred_clock_RNO ORCALUT4 6 apple_module.D13.flash_counter[0] No clocks found on inputs
|
|
===================================================================================================================================================================================================================================================================
|
|
|
|
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
|
|
|
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 147MB)
|
|
|
|
Writing Analyst data base C:\Dev\Apple1Display\impl1\synwork\Apple1Display_impl1_m.srm
|
|
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 147MB)
|
|
|
|
Writing EDIF Netlist and constraint files
|
|
@N: FX1056 |Writing EDF file: C:\Dev\Apple1Display\impl1\Apple1Display_impl1.edi
|
|
M-2017.03L-SP1-1
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
|
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB)
|
|
|
|
|
|
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB)
|
|
|
|
@W: MT246 :"c:\dev\apple1display\impl1\master_clk.vhd":109:4:109:12|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
|
@W: MT420 |Found inferred clock FleaFPGA_Uno_E1|sys_clock with period 1000.00ns. Please declare a user-defined clock on object "p:sys_clock"
|
|
@W: MT420 |Found inferred clock dm7427|y1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.C5.y1"
|
|
@W: MT420 |Found inferred clock dm7400_1|y1_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.D10.y1"
|
|
@W: MT420 |Found inferred clock dm7400_1|y3_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:apple_module.D10.y3"
|
|
|
|
|
|
##### START OF TIMING REPORT #####[
|
|
# Timing Report written on Thu Aug 8 18:39:15 2019
|
|
#
|
|
|
|
|
|
Top view: FleaFPGA_Uno_E1
|
|
Requested Frequency: 1.0 MHz
|
|
Wire load mode: top
|
|
Paths requested: 5
|
|
Constraint File(s):
|
|
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
|
|
|
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
|
|
|
|
|
|
|
Performance Summary
|
|
*******************
|
|
|
|
|
|
Worst slack in design: 991.335
|
|
|
|
Requested Estimated Requested Estimated Clock Clock
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
|
-----------------------------------------------------------------------------------------------------------------------------------
|
|
FleaFPGA_Uno_E1|sys_clock 1.0 MHz 115.4 MHz 1000.000 8.665 991.335 inferred Inferred_clkgroup_0
|
|
dm7400_1|y1_inferred_clock 1.0 MHz 168.4 MHz 1000.000 5.938 994.062 inferred Inferred_clkgroup_4
|
|
dm7400_1|y3_inferred_clock 1.0 MHz 262.2 MHz 1000.000 3.813 996.187 inferred Inferred_clkgroup_2
|
|
dm7427|y1_inferred_clock 1.0 MHz 218.9 MHz 1000.000 4.569 995.431 inferred Inferred_clkgroup_3
|
|
System 1.0 MHz 151.3 MHz 1000.000 6.608 993.392 system system_clkgroup
|
|
===================================================================================================================================
|
|
|
|
|
|
|
|
|
|
|
|
Clock Relationships
|
|
*******************
|
|
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------
|
|
System System | 1000.000 993.392 | No paths - | No paths - | No paths -
|
|
System dm7427|y1_inferred_clock | 1000.000 995.399 | No paths - | No paths - | No paths -
|
|
System dm7400_1|y1_inferred_clock | 1000.000 994.080 | No paths - | No paths - | No paths -
|
|
FleaFPGA_Uno_E1|sys_clock System | 1000.000 991.943 | No paths - | No paths - | No paths -
|
|
FleaFPGA_Uno_E1|sys_clock FleaFPGA_Uno_E1|sys_clock | 1000.000 991.335 | No paths - | No paths - | No paths -
|
|
FleaFPGA_Uno_E1|sys_clock dm7427|y1_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
|
|
FleaFPGA_Uno_E1|sys_clock dm7400_1|y1_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
|
|
dm7400_1|y3_inferred_clock dm7400_1|y3_inferred_clock | No paths - | 1000.000 996.187 | No paths - | No paths -
|
|
dm7400_1|y3_inferred_clock dm7400_1|y1_inferred_clock | No paths - | No paths - | No paths - | Diff grp -
|
|
dm7427|y1_inferred_clock System | 1000.000 993.424 | No paths - | No paths - | No paths -
|
|
dm7427|y1_inferred_clock FleaFPGA_Uno_E1|sys_clock | Diff grp - | No paths - | No paths - | No paths -
|
|
dm7427|y1_inferred_clock dm7427|y1_inferred_clock | 1000.000 995.431 | No paths - | No paths - | No paths -
|
|
dm7427|y1_inferred_clock dm7400_1|y1_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
|
|
dm7400_1|y1_inferred_clock System | 1000.000 994.581 | No paths - | No paths - | No paths -
|
|
dm7400_1|y1_inferred_clock dm7400_1|y1_inferred_clock | 1000.000 994.062 | No paths - | No paths - | No paths -
|
|
==================================================================================================================================================
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
|
|
|
|
|
|
|
Interface Information
|
|
*********************
|
|
|
|
No IO constraint found
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: FleaFPGA_Uno_E1|sys_clock
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
-----------------------------------------------------------------------------------------------------------------------
|
|
uart_module.r_Clk_Count[3] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[3] 1.108 991.335
|
|
uart_module.r_Clk_Count[4] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[4] 1.108 991.335
|
|
uart_module.r_Clk_Count[5] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[5] 1.108 991.335
|
|
uart_module.r_Clk_Count[6] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[6] 1.108 991.335
|
|
uart_module.r_Clk_Count[0] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[0] 1.044 991.607
|
|
uart_module.r_Clk_Count[1] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[1] 1.044 991.607
|
|
uart_module.r_Clk_Count[2] FleaFPGA_Uno_E1|sys_clock FD1S3IX Q r_Clk_Count[2] 1.044 991.607
|
|
rd[0] FleaFPGA_Uno_E1|sys_clock FD1P3JX Q rd[0] 1.044 991.943
|
|
rd[3] FleaFPGA_Uno_E1|sys_clock FD1P3JX Q rd[3] 1.044 991.943
|
|
flash_count[2] FleaFPGA_Uno_E1|sys_clock FD1P3AX Q flash_count[2] 1.044 992.273
|
|
=======================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
----------------------------------------------------------------------------------------------------------------------------
|
|
uart_module.r_Clk_Count[5] FleaFPGA_Uno_E1|sys_clock FD1S3IX D r_Clk_Count_6[5] 1000.089 991.335
|
|
uart_module.r_Clk_Count[6] FleaFPGA_Uno_E1|sys_clock FD1S3IX D r_Clk_Count_6[6] 1000.089 991.335
|
|
uart_module.r_Clk_Count[3] FleaFPGA_Uno_E1|sys_clock FD1S3IX D r_Clk_Count_6[3] 1000.089 991.477
|
|
uart_module.r_Clk_Count[7] FleaFPGA_Uno_E1|sys_clock FD1S3IX D un1_r_Clk_Count[0] 999.894 991.614
|
|
uart_module.r_Clk_Count[2] FleaFPGA_Uno_E1|sys_clock FD1S3IX D r_Clk_Count_6[2] 1000.089 991.620
|
|
uart_module.r_Clk_Count[4] FleaFPGA_Uno_E1|sys_clock FD1S3IX D un1_r_Clk_Count[3] 999.894 991.900
|
|
uart_module.r_Clk_Count[1] FleaFPGA_Uno_E1|sys_clock FD1S3IX D un1_r_Clk_Count[6] 999.894 992.043
|
|
da FleaFPGA_Uno_E1|sys_clock FD1S3IX CD da_0_sqmuxa 999.197 992.273
|
|
rd[0] FleaFPGA_Uno_E1|sys_clock FD1P3JX SP un1_flash_count_1 999.528 992.605
|
|
rd[1] FleaFPGA_Uno_E1|sys_clock FD1P3JX SP un1_flash_count_1 999.528 992.605
|
|
============================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 1000.000
|
|
- Setup time: -0.089
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 1000.089
|
|
|
|
- Propagation time: 8.754
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (critical) : 991.335
|
|
|
|
Number of logic level(s): 8
|
|
Starting point: uart_module.r_Clk_Count[3] / Q
|
|
Ending point: uart_module.r_Clk_Count[6] / D
|
|
The start point is clocked by FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
|
|
The end point is clocked by FleaFPGA_Uno_E1|sys_clock [rising] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-------------------------------------------------------------------------------------------------------------
|
|
uart_module.r_Clk_Count[3] FD1S3IX Q Out 1.108 1.108 -
|
|
r_Clk_Count[3] Net - - - - 3
|
|
uart_module.r_SM_Main_ns_2_0_.m12 ORCALUT4 A In 0.000 1.108 -
|
|
uart_module.r_SM_Main_ns_2_0_.m12 ORCALUT4 Z Out 1.193 2.301 -
|
|
N_13 Net - - - - 4
|
|
uart_module.r_SM_Main_ns_2_0_.m13 ORCALUT4 B In 0.000 2.301 -
|
|
uart_module.r_SM_Main_ns_2_0_.m13 ORCALUT4 Z Out 1.225 3.525 -
|
|
N_14 Net - - - - 5
|
|
uart_module.un1_r_Clk_Count_2_sqmuxa ORCALUT4 C In 0.000 3.525 -
|
|
uart_module.un1_r_Clk_Count_2_sqmuxa ORCALUT4 Z Out 1.233 4.758 -
|
|
un1_r_Clk_Count_2_sqmuxa Net - - - - 6
|
|
uart_module.un1_r_Clk_Count_cry_0_0 CCU2D B0 In 0.000 4.758 -
|
|
uart_module.un1_r_Clk_Count_cry_0_0 CCU2D COUT Out 1.544 6.303 -
|
|
un1_r_Clk_Count_cry_0 Net - - - - 1
|
|
uart_module.un1_r_Clk_Count_cry_1_0 CCU2D CIN In 0.000 6.303 -
|
|
uart_module.un1_r_Clk_Count_cry_1_0 CCU2D COUT Out 0.143 6.446 -
|
|
un1_r_Clk_Count_cry_2 Net - - - - 1
|
|
uart_module.un1_r_Clk_Count_cry_3_0 CCU2D CIN In 0.000 6.446 -
|
|
uart_module.un1_r_Clk_Count_cry_3_0 CCU2D COUT Out 0.143 6.588 -
|
|
un1_r_Clk_Count_cry_4 Net - - - - 1
|
|
uart_module.un1_r_Clk_Count_cry_5_0 CCU2D CIN In 0.000 6.588 -
|
|
uart_module.un1_r_Clk_Count_cry_5_0 CCU2D S1 Out 1.549 8.137 -
|
|
un1_r_Clk_Count_cry_5_0_S1 Net - - - - 1
|
|
uart_module.p_UART_RX\.r_Clk_Count_6_iv[6] ORCALUT4 A In 0.000 8.137 -
|
|
uart_module.p_UART_RX\.r_Clk_Count_6_iv[6] ORCALUT4 Z Out 0.617 8.754 -
|
|
r_Clk_Count_6[6] Net - - - - 1
|
|
uart_module.r_Clk_Count[6] FD1S3IX D In 0.000 8.754 -
|
|
=============================================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: dm7400_1|y1_inferred_clock
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
--------------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA0 screen_char[0] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA1 screen_char[1] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA2 screen_char[2] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA3 screen_char[3] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA4 screen_char[4] 3.737 994.062
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC DOA5 screen_char[5] 3.737 994.062
|
|
apple_module.C3.LineBuffer.FF_2 dm7400_1|y1_inferred_clock FD1P3IX Q shreg_addr_w3 1.108 996.291
|
|
apple_module.C3.LineBuffer.FF_5 dm7400_1|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
apple_module.C3.LineBuffer.FF_3 dm7400_1|y1_inferred_clock FD1P3IX Q shreg_addr_w2 1.108 996.859
|
|
apple_module.C3.LineBuffer.FF_4 dm7400_1|y1_inferred_clock FD1P3IX Q shreg_addr_w1 1.108 996.859
|
|
======================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
--------------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA6 screen_char[0] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA7 screen_char[1] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA8 screen_char[2] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA9 screen_char[3] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA10 screen_char[4] 998.318 994.581
|
|
apple_module.D2.sig2513_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA11 screen_char[5] 998.318 994.581
|
|
apple_module.C3.LineBuffer.OR2_t0 dm7400_1|y1_inferred_clock OR2 B dec0_r102 1000.000 996.291
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA3 shreg_addr_w0 998.318 997.210
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA4 shreg_addr_w1 998.318 997.210
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 dm7400_1|y1_inferred_clock DP8KC ADA5 shreg_addr_w2 998.318 997.210
|
|
======================================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 1000.000
|
|
- Setup time: 1.753
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 998.247
|
|
|
|
- Propagation time: 4.185
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 994.062
|
|
|
|
Number of logic level(s): 1
|
|
Starting point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DOA0
|
|
Ending point: apple_module.C3.LineBuffer.sram_1_0_0_0 / DIA0
|
|
The start point is clocked by dm7400_1|y1_inferred_clock [rising] on pin CLKA
|
|
The end point is clocked by dm7400_1|y1_inferred_clock [rising] on pin CLKA
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
----------------------------------------------------------------------------------------------------------
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DOA0 Out 3.737 3.737 -
|
|
screen_char[0] Net - - - - 2
|
|
apple_module.C3.input[0] ORCALUT4 D In 0.000 3.737 -
|
|
apple_module.C3.input[0] ORCALUT4 Z Out 0.449 4.185 -
|
|
input[0] Net - - - - 1
|
|
apple_module.C3.LineBuffer.sram_1_0_0_0 DP8KC DIA0 In 0.000 4.185 -
|
|
==========================================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: dm7400_1|y3_inferred_clock
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
---------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.D13.flash_counter[1] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[1] 1.180 996.187
|
|
apple_module.D13.flash_counter[2] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[2] 1.148 996.219
|
|
apple_module.D13.flash_counter[3] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[3] 1.108 996.259
|
|
apple_module.D13.flash_counter[5] dm7400_1|y3_inferred_clock FD1S3AX Q cursor_flash 1.108 996.259
|
|
apple_module.D13.flash_counter[0] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[0] 1.188 997.195
|
|
apple_module.D13.flash_counter[4] dm7400_1|y3_inferred_clock FD1S3AX Q flash_counter[4] 1.148 997.307
|
|
=================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
--------------------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.D13.flash_counter[5] dm7400_1|y3_inferred_clock FD1S3AX D flash_counter_3[5] 1000.089 996.187
|
|
apple_module.D13.flash_counter[4] dm7400_1|y3_inferred_clock FD1S3AX D un3_flash_counter_1_axbxc4 1000.089 997.195
|
|
apple_module.D13.flash_counter[0] dm7400_1|y3_inferred_clock FD1S3AX D flash_counter_3[0] 1000.089 997.203
|
|
apple_module.D13.flash_counter[1] dm7400_1|y3_inferred_clock FD1S3AX D un3_flash_counter_1_axbxc1 1000.089 998.284
|
|
apple_module.D13.flash_counter[2] dm7400_1|y3_inferred_clock FD1S3AX D un3_flash_counter_1_axbxc2 1000.089 998.284
|
|
apple_module.D13.flash_counter[3] dm7400_1|y3_inferred_clock FD1S3AX D un3_flash_counter_1_axbxc3 1000.089 998.284
|
|
============================================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 1000.000
|
|
- Setup time: -0.089
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 1000.089
|
|
|
|
- Propagation time: 3.902
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 996.187
|
|
|
|
Number of logic level(s): 3
|
|
Starting point: apple_module.D13.flash_counter[1] / Q
|
|
Ending point: apple_module.D13.flash_counter[5] / D
|
|
The start point is clocked by dm7400_1|y3_inferred_clock [falling] on pin CK
|
|
The end point is clocked by dm7400_1|y3_inferred_clock [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
------------------------------------------------------------------------------------------------------
|
|
apple_module.D13.flash_counter[1] FD1S3AX Q Out 1.180 1.180 -
|
|
flash_counter[1] Net - - - - 5
|
|
apple_module.D13.flash_counter_1_3 ORCALUT4 A In 0.000 1.180 -
|
|
apple_module.D13.flash_counter_1_3 ORCALUT4 Z Out 1.089 2.269 -
|
|
flash_counter_1_3 Net - - - - 2
|
|
apple_module.D13.flash_counter_1 ORCALUT4 C In 0.000 2.269 -
|
|
apple_module.D13.flash_counter_1 ORCALUT4 Z Out 1.017 3.285 -
|
|
flash_counter_1 Net - - - - 1
|
|
apple_module.D13.flash_counter_3[5] ORCALUT4 B In 0.000 3.285 -
|
|
apple_module.D13.flash_counter_3[5] ORCALUT4 Z Out 0.617 3.902 -
|
|
flash_counter_3[5] Net - - - - 1
|
|
apple_module.D13.flash_counter[5] FD1S3AX D In 0.000 3.902 -
|
|
======================================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: dm7427|y1_inferred_clock
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
---------------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.C7.states[1] dm7427|y1_inferred_clock FD1S3AX Q char_ready 1.148 993.424
|
|
apple_module.C7.states[5] dm7427|y1_inferred_clock FD1S3AX Q wc2_i 1.044 993.977
|
|
apple_module.C7.states[3] dm7427|y1_inferred_clock FD1S3AX Q cleared_last 0.972 994.049
|
|
apple_module.C7.states[0] dm7427|y1_inferred_clock FD1S3AX Q screen_clear_inhibit 0.972 995.241
|
|
apple_module.C7.states[4] dm7427|y1_inferred_clock FD1S3AX Q line_clear_inhibit 0.972 995.690
|
|
apple_module.C11b.sram_1_0_0_0 dm7427|y1_inferred_clock DP8KC DOA0 mem_curs_out[0] 3.737 996.158
|
|
apple_module.C11b.FF_9 dm7427|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
apple_module.D4a.FF_9 dm7427|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
apple_module.D14b.FF_9 dm7427|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
apple_module.D14a.FF_9 dm7427|y1_inferred_clock FD1P3IX Q shreg_addr_w0 1.108 996.291
|
|
=================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
-----------------------------------------------------------------------------------------------------------------------------
|
|
apple_module.C7.states[5] dm7427|y1_inferred_clock FD1S3AX D wc1_i 999.894 995.431
|
|
apple_module.C13.states[3] dm7427|y1_inferred_clock FD1S3AX D mem_curs_out[0] 999.894 996.158
|
|
apple_module.C11b.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D14a.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D4a.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D14b.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D5a.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D4b.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.D5b.OR2_t0 dm7427|y1_inferred_clock OR2 B dec0_r2046 1000.000 996.291
|
|
apple_module.C11b.sram_1_0_0_0 dm7427|y1_inferred_clock DP8KC DIA1 mem_curs_in[0] 998.247 996.755
|
|
=============================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 1000.000
|
|
- Setup time: 0.472
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
+ Estimated clock delay at ending point: 0.000
|
|
= Required time: 999.528
|
|
|
|
- Propagation time: 6.105
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 993.424
|
|
|
|
Number of logic level(s): 6
|
|
Starting point: apple_module.C7.states[1] / Q
|
|
Ending point: apple_module.D8.count[0] / SP
|
|
The start point is clocked by dm7427|y1_inferred_clock [rising] on pin CK
|
|
The end point is clocked by System [rising] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-----------------------------------------------------------------------------------------------
|
|
apple_module.C7.states[1] FD1S3AX Q Out 1.148 1.148 -
|
|
char_ready Net - - - - 4
|
|
apple_module.C5.y2 ORCALUT4 B In 0.000 1.148 -
|
|
apple_module.C5.y2 ORCALUT4 Z Out 0.449 1.597 -
|
|
y2_0 Net - - - - 2
|
|
apple_module.C8.un1_y2 ORCALUT4 A In 0.000 1.597 -
|
|
apple_module.C8.un1_y2 ORCALUT4 Z Out 1.193 2.789 -
|
|
clear_char Net - - - - 4
|
|
apple_module.C8.un6_y1 ORCALUT4 B In 0.000 2.789 -
|
|
apple_module.C8.un6_y1 ORCALUT4 Z Out 0.449 3.238 -
|
|
un6_y1 Net - - - - 1
|
|
apple_module.C12.Y2 ORCALUT4 A In 0.000 3.238 -
|
|
apple_module.C12.Y2 ORCALUT4 Z Out 1.225 4.463 -
|
|
wc1_i Net - - - - 5
|
|
apple_module.C12.Y2_RNICBVQ ORCALUT4 B In 0.000 4.463 -
|
|
apple_module.C12.Y2_RNICBVQ ORCALUT4 Z Out 0.449 4.912 -
|
|
load_v_i_0 Net - - - - 5
|
|
apple_module.D8.count_cnv[0] ORCALUT4 C In 0.000 4.912 -
|
|
apple_module.D8.count_cnv[0] ORCALUT4 Z Out 1.193 6.105 -
|
|
count_cnv_0[0] Net - - - - 4
|
|
apple_module.D8.count[0] FD1P3DX SP In 0.000 6.105 -
|
|
===============================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: System
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
------------------------------------------------------------------------------------------------------------
|
|
apple_module.C13.states[3] System FD1S3AX Q states[3] 1.180 993.392
|
|
apple_module.D7.count[3] System FD1P3AX Q horz_count_upper[3] 1.232 994.084
|
|
apple_module.D9.count[3] System FD1P3DX Q count_0[3] 1.148 994.168
|
|
apple_module.D9.count[2] System FD1P3DX Q count_0[2] 1.108 994.208
|
|
apple_module.D9.count[1] System FD1P3DX Q count[1] 1.148 994.946
|
|
apple_module.D8.count[0] System FD1P3DX Q count[0] 1.204 995.026
|
|
apple_module.D8.count[1] System FD1P3DX Q count[1] 1.188 995.042
|
|
apple_module.D6.count[3] System FD1P3AX Q horz_count_lower[3] 1.220 995.474
|
|
apple_module.D7.count[2] System FD1P3AX Q horz_count_upper[2] 1.220 995.514
|
|
apple_module.D7.count[0] System FD1P3AX Q horz_count_upper[0] 1.188 995.546
|
|
============================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
-----------------------------------------------------------------------------------------------------
|
|
apple_module.C7.states[5] System FD1S3AX D wc1_i 999.894 995.399
|
|
apple_module.D1.Qd System FD1P3AX D Qd_3 1000.089 995.735
|
|
apple_module.D1.Qe System FD1P3AX D Qe_3 1000.089 995.735
|
|
apple_module.D1.Qf System FD1P3AX D Qf_3 1000.089 995.735
|
|
apple_module.D1.Qg System FD1P3AX D Qg_3 1000.089 995.735
|
|
apple_module.D1.Qh System FD1P3AX D Qh_3 1000.089 995.735
|
|
apple_module.D7.count[0] System FD1P3AX SP count_cnv[0] 999.528 995.923
|
|
apple_module.D7.count[1] System FD1P3AX SP count_cnv[0] 999.528 995.923
|
|
apple_module.D7.count[2] System FD1P3AX SP count_cnv[0] 999.528 995.923
|
|
apple_module.D7.count[3] System FD1P3AX SP count_cnv[0] 999.528 995.923
|
|
=====================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 1000.000
|
|
- Setup time: 0.472
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
+ Estimated clock delay at ending point: 0.000
|
|
= Required time: 999.528
|
|
|
|
- Propagation time: 6.137
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : 993.392
|
|
|
|
Number of logic level(s): 6
|
|
Starting point: apple_module.C13.states[3] / Q
|
|
Ending point: apple_module.D8.count[0] / SP
|
|
The start point is clocked by System [rising] on pin CK
|
|
The end point is clocked by System [rising] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-----------------------------------------------------------------------------------------------
|
|
apple_module.C13.states[3] FD1S3AX Q Out 1.180 1.180 -
|
|
states[3] Net - - - - 5
|
|
apple_module.C5.y2 ORCALUT4 A In 0.000 1.180 -
|
|
apple_module.C5.y2 ORCALUT4 Z Out 0.449 1.629 -
|
|
y2_0 Net - - - - 2
|
|
apple_module.C8.un1_y2 ORCALUT4 A In 0.000 1.629 -
|
|
apple_module.C8.un1_y2 ORCALUT4 Z Out 1.193 2.821 -
|
|
clear_char Net - - - - 4
|
|
apple_module.C8.un6_y1 ORCALUT4 B In 0.000 2.821 -
|
|
apple_module.C8.un6_y1 ORCALUT4 Z Out 0.449 3.270 -
|
|
un6_y1 Net - - - - 1
|
|
apple_module.C12.Y2 ORCALUT4 A In 0.000 3.270 -
|
|
apple_module.C12.Y2 ORCALUT4 Z Out 1.225 4.495 -
|
|
wc1_i Net - - - - 5
|
|
apple_module.C12.Y2_RNICBVQ ORCALUT4 B In 0.000 4.495 -
|
|
apple_module.C12.Y2_RNICBVQ ORCALUT4 Z Out 0.449 4.944 -
|
|
load_v_i_0 Net - - - - 5
|
|
apple_module.D8.count_cnv[0] ORCALUT4 C In 0.000 4.944 -
|
|
apple_module.D8.count_cnv[0] ORCALUT4 Z Out 1.193 6.137 -
|
|
count_cnv_0[0] Net - - - - 4
|
|
apple_module.D8.count[0] FD1P3DX SP In 0.000 6.137 -
|
|
===============================================================================================
|
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
|
|
|
Timing exceptions that could not be applied
|
|
None
|
|
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 150MB)
|
|
|
|
|
|
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 150MB)
|
|
|
|
---------------------------------------
|
|
Resource Usage Report
|
|
Part: lcmxo2_7000hc-4
|
|
|
|
Register bits: 175 of 6864 (3%)
|
|
PIC Latch: 0
|
|
I/O cells: 15
|
|
Block Rams : 9 of 26 (34%)
|
|
|
|
|
|
Details:
|
|
CCU2D: 17
|
|
CU2: 38
|
|
DP8KC: 9
|
|
FADD2B: 8
|
|
FD1P3AX: 49
|
|
FD1P3DX: 8
|
|
FD1P3IX: 76
|
|
FD1P3JX: 7
|
|
FD1S3AX: 22
|
|
FD1S3IX: 12
|
|
GSR: 1
|
|
IB: 3
|
|
IFS1P3DX: 1
|
|
INV: 25
|
|
OB: 12
|
|
OR2: 8
|
|
ORCALUT4: 143
|
|
PFUMX: 3
|
|
PUR: 1
|
|
ROM16X1A: 30
|
|
VHI: 34
|
|
VLO: 34
|
|
Mapper successful!
|
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 150MB)
|
|
|
|
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
|
|
# Thu Aug 8 18:39:15 2019
|
|
|
|
###########################################################]
|