9 lines
565 B
XML
9 lines
565 B
XML
<?xml version="1.0" encoding="UTF-8"?>
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<DiamondModule name="master_clk" module="master_clk" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2019 08 05 08:34:52.070" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
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<Package>
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<File name="master_clk.lpc" type="lpc" modified="2019 08 05 08:34:49.852"/>
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<File name="master_clk.vhd" type="top_level_vhdl" modified="2019 08 05 08:34:49.929"/>
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<File name="master_clk_tmpl.vhd" type="template_vhdl" modified="2019 08 05 08:34:49.934"/>
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</Package>
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</DiamondModule>
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