remove pwr_reset
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caa2268b82
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@ -175,7 +175,6 @@ set_global_assignment -name VERILOG_FILE rtl/arlet_6502/ALU.v
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set_global_assignment -name VERILOG_FILE rtl/arlet_6502/arlet_6502.v
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set_global_assignment -name VERILOG_FILE rtl/apple1.v
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set_global_assignment -name VERILOG_FILE rtl/clock.v
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set_global_assignment -name VERILOG_FILE rtl/pwr_reset.v
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set_global_assignment -name VERILOG_FILE rtl/ram.v
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set_global_assignment -name VERILOG_FILE rtl/rom_basic.v
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set_global_assignment -name VERILOG_FILE rtl/rom_wozmon.v
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23
rtl/apple1.v
23
rtl/apple1.v
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@ -24,7 +24,7 @@
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module apple1(
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input clk7, // 7 MHz master clock
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input rst_n, // active low synchronous reset (needed for simulation)
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input reset, // reset
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input cpu_clken, // cpu clock enable
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@ -61,28 +61,13 @@ assign ram_wr = we & ram_cs;
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wire [7:0] cpu_dout;
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wire we;
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//////////////////////////////////////////////////////////////////////////
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// Clocks
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//////////////////////////////////////////////////////////////////////////
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// Reset
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wire rst;
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pwr_reset pwr_reset(
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.clk7(clk7),
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.rst_n(rst_n),
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.enable(cpu_clken),
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.rst(rst)
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);
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//////////////////////////////////////////////////////////////////////////
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// 6502
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arlet_6502 arlet_6502(
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.clk (clk7),
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.enable (cpu_clken),
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.rst (rst),
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.rst (reset),
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.ab (addr),
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.dbi (cpu_din),
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.dbo (cpu_dout),
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@ -108,7 +93,7 @@ assign ram_wr = we & ram_cs;
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wire [7:0] ps2_dout;
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ps2keyboard keyboard(
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.clk7(clk7),
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.rst(rst),
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.rst(reset),
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.key_clk(ps2_clk),
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.key_din(ps2_din),
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.cs(keyboard_cs),
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@ -119,7 +104,7 @@ assign ram_wr = we & ram_cs;
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display display(
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.clk(clk7),
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.enable(display_cs & cpu_clken),
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.rst(rst),
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.rst(reset),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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@ -258,7 +258,7 @@ wire [7:0] bus_dout = basic_cs ? basic_dout :
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apple1 apple1
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(
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.clk7(clk7),
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.rst_n(~reset_button),
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.reset(reset_button),
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.cpu_clken(cpu_clken), // apple1 outputs the CPU clock enable
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@ -421,7 +421,7 @@ wire cpu_clken; // provides the cpu clock enable signal derived from main clock
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//wire cpu_clken;
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clock clock(
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.clk7 ( clk7 ), // input: main clock
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.rst_n ( ~reset_button ), // input: reset signal
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.reset ( reset_button ), // input: reset signal
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.cpu_clken( cpu_clken ) // output: cpu clock enable
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);
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@ -26,7 +26,7 @@
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module clock
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(
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input clk7, // 7MHz clock master clock
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input rst_n, // active low synchronous reset
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input reset, // reset
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// Clock enables
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output reg cpu_clken // 1MHz clock enable for the CPU and devices
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@ -44,7 +44,7 @@ module clock
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reg [4:0] clk_div;
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always @(posedge clk7)
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begin
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if ((clk_div == 7) || (rst_n == 1'b0))
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if (clk_div == 7 || reset )
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clk_div <= 0;
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else
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clk_div <= clk_div + 1'b1;
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