112 lines
3.4 KiB
Systemverilog
112 lines
3.4 KiB
Systemverilog
// This module allows easy download of three types of files into system ram:
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//
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// 1) ROM file that is injected by the firmware at startup/boot (loaded at address 0)
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// 2) PRG file, containing load address in the first two bytes as in C64's .prg
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// 3) ROM as 1) but with different .rom file name selected by the user from the menu
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module downloader (
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// SPI interface with the ARM controller
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input SPI_DO,
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input SPI_DI,
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input SPI_SCK,
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input SPI_SS2,
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input SPI_SS3,
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input SPI_SS4,
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input clk,
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input clk_ena,
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output reg wr,
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output reg [24:0] addr,
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output reg [7:0] data,
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output reg downloading, // 1 = active download is in process
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output reg ROM_done // 1 = boot ROM has already been loaded
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);
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parameter BOOT_INDEX = 0; // menu index for the boot rom (0 by default in MiST firmware)
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parameter PRG_INDEX; // menu index for .prg files
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parameter ROM_INDEX; // menu index for .rom files (not loaded at boot)
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parameter ROM_START_ADDR = 0; // start of ROM
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reg [15:0] prg_start_addr; // first two bytes of the .prg file containing ram loading address
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// simplify checks
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wire is_rom_download = dio_index == BOOT_INDEX || dio_index == ROM_INDEX;
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wire is_prg_download = dio_index == PRG_INDEX;
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reg dio_dowloading_old = 0; // used to detect changes in dio_dowloading
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always @(posedge clk) begin
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if(dio_dowloading == 1) begin
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downloading <= 1;
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if(is_rom_download) begin
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addr <= dio_addr + ROM_START_ADDR;
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wr <= dio_wr;
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data <= dio_data;
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end
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else if(is_prg_download) begin
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if(dio_addr == 0) begin
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prg_start_addr [7:0] = dio_data; // extracts address low byte
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wr <= 0; // do not write yet
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end
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else if(dio_addr == 1) begin
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prg_start_addr[15:8] = dio_data; // extracts address high byte
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wr <= 0; // do not write yet
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end
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else begin
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addr <= dio_addr + { 9'b0, prg_start_addr } - 2; // write prg at load address and skip first two bytes
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wr <= dio_wr;
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data <= dio_data;
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end
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end
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end
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// end of transfer
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if(dio_dowloading_old == 1 && dio_dowloading == 0) begin
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downloading <= 0;
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if(is_rom_download) ROM_done <= 1;
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end
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// detect change in dio_dowloading
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dio_dowloading_old <= dio_dowloading;
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end
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @data_io ***************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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wire dio_dowloading;
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wire [7:0] dio_index;
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wire dio_wr;
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wire [24:0] dio_addr;
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wire [7:0] dio_data;
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data_io data_io (
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.clk_sys ( clk ),
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.clkref_n( ~clk_ena ), // keep this to zero
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// io controller spi interface
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.SPI_SCK( SPI_SCK ),
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.SPI_SS2( SPI_SS2 ),
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.SPI_SS4( SPI_SS4 ),
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.SPI_DI ( SPI_DI ),
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.SPI_DO ( SPI_DO ),
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.ioctl_download ( dio_dowloading ), // signal indicating an active rom download
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.ioctl_index ( dio_index ), // 0=rom download, 1=prg dowload
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.ioctl_addr ( dio_addr ),
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.ioctl_dout ( dio_data ),
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.ioctl_wr ( dio_wr )
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);
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endmodule
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