162 lines
6.4 KiB
Verilog
162 lines
6.4 KiB
Verilog
//
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// sdram.v
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//
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// sdram controller implementation for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module sdram (
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// interface to the MT48LC16M16 chip
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inout [15:0] sd_data, // 16 bit bidirectional data bus
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output [12:0] sd_addr, // 13 bit multiplexed address bus for row/col select
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output [1:0] sd_dqm, // two byte masks
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output [1:0] sd_ba, // four banks
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output sd_cs, // chip select
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output sd_we, // write enable
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output sd_ras, // row address select
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output sd_cas, // columns address select
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// cpu/chipset interface
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input init, // init signal after FPGA config to initialize RAM
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input clk, // sdram is accessed at up to 128MHz
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input clkref, // reference clock to sync to
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// input [2:0] q,
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input [7:0] din, // data input from chipset/cpu
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output [7:0] dout, // data output to chipset/cpu
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input [24:0] addr, // 25 bit byte address
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input oe, // cpu/chipset requests read
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input we // cpu/chipset requests write
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);
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// ---------------------------------------------------------------------
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// ------------------------ sdram configuration ------------------------
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// ---------------------------------------------------------------------
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// MODE is sent as address on reset = 2
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// PRECHARGE_ADDR is sent as address on reset = 13
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localparam RASCAS_DELAY = 3'd3; // tRCD>=20ns -> 2 cycles@64MHz
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localparam BURST_LENGTH = 3'b000; // 000=none, 001=2, 010=4, 011=8
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localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
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localparam CAS_LATENCY = 3'd2; // 2/3 allowed
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localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
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localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
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localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
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localparam PRECHARGE_ADDR = 13'b0010000000000;
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// ---------------------------------------------------------------------
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// ------------------------ cycle state machine ------------------------
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// ---------------------------------------------------------------------
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// there are 8 states (0-7) tracked by "q"
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localparam STATE_IDLE = 3'd0; // first state in cycle
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localparam STATE_CMD_START = 3'd1; // state in which a new command can be started
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localparam STATE_CMD_CONT = STATE_CMD_START+RASCAS_DELAY-3'd1; // 4 command can be continued
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localparam STATE_LAST = 3'd7; // last state in cycle
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reg [2:0] q /* synthesis noprune */;
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always @(posedge clk) begin
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// 32Mhz counter synchronous to 4 Mhz clock
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// force counter to pass state 5->6 exactly after the rising edge of clkref
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// since clkref is two clocks early
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if(((q == 7) && ( clkref == 0)) ||
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((q == 0) && ( clkref == 1)) ||
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((q != 7) && (q != 0)))
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q <= q + 3'd1;
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end
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// ---------------------------------------------------------------------
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// --------------------------- startup/reset ---------------------------
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// ---------------------------------------------------------------------
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// wait 1ms (32 clkref cycles) after FPGA config is done before going
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// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
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reg [4:0] reset;
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always @(posedge clk) begin
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if(init) reset <= 5'h1f;
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else if((q == STATE_LAST) && (reset != 0))
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reset <= reset - 5'd1;
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end
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// ---------------------------------------------------------------------
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// ------------------ generate ram control signals ---------------------
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// ---------------------------------------------------------------------
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// all possible commands
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localparam CMD_INHIBIT = 4'b1111; // initial state
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localparam CMD_NOP = 4'b0111; // (not used here)
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localparam CMD_ACTIVE = 4'b0011; // command starts, done at STATE_IDLE
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localparam CMD_READ = 4'b0101; // read commanddone, done at STATE_CMD_CONT
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localparam CMD_WRITE = 4'b0100; // write command, done at STATE_CMD_CONT
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localparam CMD_BURST_TERMINATE = 4'b0110; // (not used here)
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localparam CMD_PRECHARGE = 4'b0010; // sends a precharge address, done when reset=13 and STATE_IDLE
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localparam CMD_AUTO_REFRESH = 4'b0001; // refresh command, done at STATE_IDLE
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localparam CMD_LOAD_MODE = 4'b0000; // sends MODE (sdram config), done when reset=2 and STATE_IDLE
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reg [3:0] sd_cmd; // current command sent to sd ram
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// drive control signals according to current command
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assign sd_cs = sd_cmd[3]; // in negated logic
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assign sd_ras = sd_cmd[2]; // in negated logic
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assign sd_cas = sd_cmd[1]; // in negated logic
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assign sd_we = sd_cmd[0]; // in negated logic
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assign sd_data = we ? {din, din} : 16'bZZZZZZZZZZZZZZZZ;
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assign dout = sd_data[7:0];
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always @(posedge clk) begin
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sd_cmd <= CMD_INHIBIT;
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if(reset != 0) begin
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// SDRAM is resetting, counting from 31 to 0
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if(q == STATE_IDLE) begin
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if(reset == 13) sd_cmd <= CMD_PRECHARGE;
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if(reset == 2) sd_cmd <= CMD_LOAD_MODE;
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end
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end else begin
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// normal run
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if(q == STATE_IDLE) begin
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if(we || oe) sd_cmd <= CMD_ACTIVE;
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else sd_cmd <= CMD_AUTO_REFRESH;
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end
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else if(q == STATE_CMD_CONT) begin
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if(we) sd_cmd <= CMD_WRITE;
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else if(oe) sd_cmd <= CMD_READ;
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end
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end
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end
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// address during reset
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wire [12:0] reset_addr = (reset == 13) ? PRECHARGE_ADDR : MODE;
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// address during normal run
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wire [12:0] row = addr[20:8];
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wire [12:0] col = { 4'b0010, addr[23], addr[7:0] };
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wire [12:0] run_addr = (q == STATE_CMD_START)? row : col;
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assign sd_addr = (reset != 0) ? reset_addr : run_addr;
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assign sd_ba = addr[22:21]; // bank is taken from cpu address high bits
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assign sd_dqm = 2'b00; // no mask
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endmodule
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