620 lines
21 KiB
Verilog
620 lines
21 KiB
Verilog
//
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// sd_card.v
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//
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// This file implelents a sd card for the MIST board since on the board
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// the SD card is connected to the ARM IO controller and the FPGA has no
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// direct connection to the SD card. This file provides a SD card like
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// interface to the IO controller easing porting of cores that expect
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// a direct interface to the SD card.
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the Lesser GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// http://elm-chan.org/docs/mmc/mmc_e.html
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module sd_card (
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input clk_sys,
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// link to user_io for io controller
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output reg[31:0] sd_lba,
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output reg sd_rd,
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output reg sd_wr,
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input sd_ack,
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input sd_ack_conf,
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output sd_conf,
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output sd_sdhc,
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input img_mounted,
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input [63:0] img_size,
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output reg sd_busy = 0,
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// data coming in from io controller
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input [7:0] sd_buff_dout,
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input sd_buff_wr,
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// data going out to io controller
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output [7:0] sd_buff_din,
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input [8:0] sd_buff_addr,
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// configuration input
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// in case of a VHD file, this will determine the SD Card type returned to the SPI master
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// in case of a pass-through, the firmware will display a warning if SDHC is not allowed,
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// but the card inserted is SDHC
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input allow_sdhc,
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input sd_cs,
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input sd_sck,
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input sd_sdi,
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output reg sd_sdo
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);
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wire [31:0] OCR = { 1'b1, sdhc, 6'h0, 9'h1f, 15'h0 }; // bit31 = finished powerup
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// bit30 = 1 -> high capaciry card (sdhc)
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// 15-23 supported voltage range
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wire [7:0] READ_DATA_TOKEN = 8'hfe;
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// number of bytes to wait after a command before sending the reply
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localparam NCR=4;
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localparam RD_STATE_IDLE = 3'd0;
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localparam RD_STATE_WAIT_BUSY = 3'd1;
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localparam RD_STATE_WAIT_IO = 3'd2;
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localparam RD_STATE_SEND_TOKEN = 3'd3;
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localparam RD_STATE_SEND_DATA = 3'd4;
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localparam RD_STATE_DELAY = 3'd5;
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reg [2:0] read_state = RD_STATE_IDLE;
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localparam WR_STATE_IDLE = 3'd0;
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localparam WR_STATE_EXP_DTOKEN = 3'd1;
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localparam WR_STATE_RECV_DATA = 3'd2;
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localparam WR_STATE_RECV_CRC0 = 3'd3;
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localparam WR_STATE_RECV_CRC1 = 3'd4;
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localparam WR_STATE_SEND_DRESP = 3'd5;
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localparam WR_STATE_WRITE = 3'd6;
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localparam WR_STATE_BUSY = 3'd7;
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reg [2:0] write_state = WR_STATE_IDLE;
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reg card_is_reset = 1'b0; // flag that card has received a reset command
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reg [6:0] sbuf;
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reg cmd55;
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reg terminate_cmd = 1'b0;
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reg [7:0] cmd = 8'h00;
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reg [2:0] bit_cnt = 3'd0; // counts bits 0-7 0-7 ...
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reg [3:0] byte_cnt= 4'd15; // counts bytes
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reg [4:0] delay_cnt;
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reg wr_first;
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reg [39:0] args;
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reg [7:0] reply;
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reg [7:0] reply0, reply1, reply2, reply3;
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reg [3:0] reply_len;
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// ------------------------- SECTOR BUFFER -----------------------
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// the buffer itself. Can hold two sectors
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reg [9:0] buffer_ptr;
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wire [7:0] buffer_dout;
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reg [7:0] buffer_din;
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reg buffer_write_strobe;
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reg sd_buff_sel;
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sd_card_dpram #(8, 10) buffer_dpram
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(
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.clock_a (clk_sys),
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.address_a ({sd_buff_sel, sd_buff_addr}),
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.data_a (sd_buff_dout),
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.wren_a (sd_buff_wr & sd_ack & read_state != RD_STATE_IDLE),
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.q_a (sd_buff_din),
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.clock_b (clk_sys),
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.address_b (buffer_ptr),
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.data_b (buffer_din),
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.wren_b (buffer_write_strobe),
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.q_b (buffer_dout)
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);
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wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
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// ------------------------- CSD/CID BUFFER ----------------------
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reg [7:0] conf;
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assign sd_conf = sd_configuring;
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reg sd_configuring = 1;
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reg [4:0] conf_buff_ptr;
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reg [7:0] conf_byte_orig;
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reg[255:0] csdcid;
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reg vhd = 0;
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reg [40:0] vhd_size;
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// conf[0]==1 -> io controller is using an sdhc card
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wire sd_has_sdhc = conf[0];
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assign sd_sdhc = (allow_sdhc & sd_has_sdhc) | vhd; // report to user_io
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wire sdhc = allow_sdhc & (sd_has_sdhc | vhd); // used internally
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always @(posedge clk_sys) begin
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reg old_mounted;
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if (sd_buff_wr & sd_ack_conf) begin
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if (sd_buff_addr == 32) begin
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conf <= sd_buff_dout;
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sd_configuring <= 0;
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end
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else csdcid[(31-sd_buff_addr) << 3 +:8] <= sd_buff_dout;
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end
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conf_byte_orig <= csdcid[(31-conf_buff_ptr) << 3 +:8];
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old_mounted <= img_mounted;
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if (~old_mounted & img_mounted) begin
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vhd <= |img_size;
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vhd_size <= img_size[40:0];
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end
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end
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// CSD V1.0 no. of blocks = c_size ** (c_size_mult + 2)
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wire [127:0] csd_sd = {
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8'h00, // CSD_STRUCTURE + reserved
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8'h2d, // TAAC
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8'd0, // NSAC
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8'h32, // TRAN_SPEED
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12'h5b5, // CCC
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4'h9, // READ_BL_LEN
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1'b1, 1'b0, 1'b0, 1'b0, // READ_BL_PARTIAL, WRITE_BLK_MISALIGN, READ_BLK_MISALIGN, DSR_IMP
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2'd0, vhd_size[29:18], // reserved + C_SIZE
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3'b111, // VDD_R_CURR_MIN
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3'b110, // VDD_R_CURR_MAX
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3'b111, // VDD_W_CURR_MIN
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3'b110, // VDD_W_CURR_MAX
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3'd7, // C_SIZE_MULT
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1'b1, // ERASE_BLK_EN
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7'd127, // SECTOR_SIZE
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7'd0, // WP_GRP_SIZE
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1'b0, // WP_GRP_ENABLE,
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2'b00, // reserved,
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3'd5, // R2W_FACTOR,
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4'h9, // WRITE_BL_LEN,
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1'b0, // WRITE_BL_PARTIAL,
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5'd0, // reserved,
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8'd0,
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7'h67, // CRC (wrong, but usually not checked)
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1'b1 };
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// CSD V2.0 size = (c_size + 1) * 512K
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wire [127:0] csd_sdhc = {
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8'h40, // CSD_STRUCTURE + reserved
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8'h0e, // TAAC
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8'd0, // NSAC
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8'h32, // TRAN_SPEED
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12'h5b5, // CCC
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4'h9, // READ_BL_LEN
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1'b0, 1'b0, 1'b0, 1'b0, // READ_BL_PARTIAL, WRITE_BLK_MISALIGN, READ_BLK_MISALIGN, DSR_IMP
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6'd0, // reserved
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vhd_size[40:19] - 1'd1, // C_SIZE
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1'b0, // reserved
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1'b1, // ERASE_BLK_EN
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7'd127, // SECTOR_SIZE
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7'd0, // WP_GRP_SIZE
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1'b0, // WP_GRP_ENABLE,
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2'b00, // reserved,
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3'd2, // R2W_FACTOR,
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4'h9, // WRITE_BL_LEN,
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1'b0, // WRITE_BL_PARTIAL,
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5'd0, // reserved,
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8'd0,
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7'h78, // CRC (wrong, but usually not checked)
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1'b1 };
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wire [7:0] conf_byte = (!conf_buff_ptr[4] | !vhd) ? conf_byte_orig : // CID or CSD if not VHD
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sdhc ? csd_sdhc[(15-conf_buff_ptr[3:0]) << 3 +:8] :
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csd_sd[(15-conf_buff_ptr[3:0]) << 3 +:8];
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always@(posedge clk_sys) begin
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reg old_sd_sck;
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reg [5:0] ack;
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ack <= {ack[4:0], sd_ack};
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if(ack[5:4] == 'b01) { sd_rd, sd_wr } <= 2'b00;
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if(ack[5:4] == 'b10) sd_busy <= 0;
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buffer_write_strobe <= 0;
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if (buffer_write_strobe) buffer_ptr <= buffer_ptr + 1'd1;
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old_sd_sck <= sd_sck;
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// advance transmitter state machine on falling sck edge, so data is valid on the
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// rising edge
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// ----------------- spi transmitter --------------------
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if(sd_cs == 0 && old_sd_sck && ~sd_sck) begin
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sd_sdo <= 1'b1; // default: send 1's (busy/wait)
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if(byte_cnt == 5+NCR) begin
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sd_sdo <= reply[~bit_cnt];
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if(bit_cnt == 7) begin
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// these three commands all have a reply_len of 0 and will thus
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// not send more than a single reply byte
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// CMD9: SEND_CSD
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// CMD10: SEND_CID
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if((cmd == 8'h49)||(cmd == 8'h4a))
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read_state <= RD_STATE_SEND_TOKEN; // jump directly to data transmission
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// CMD17: READ_SINGLE_BLOCK
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// CMD18: READ_MULTIPLE_BLOCK
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if((cmd == 8'h51 || cmd == 8'h52) && !terminate_cmd)
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read_state <= RD_STATE_WAIT_BUSY; // start waiting for data from io controller
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end
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end
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else if((reply_len > 0) && (byte_cnt == 5+NCR+1))
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sd_sdo <= reply0[~bit_cnt];
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else if((reply_len > 1) && (byte_cnt == 5+NCR+2))
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sd_sdo <= reply1[~bit_cnt];
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else if((reply_len > 2) && (byte_cnt == 5+NCR+3))
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sd_sdo <= reply2[~bit_cnt];
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else if((reply_len > 3) && (byte_cnt == 5+NCR+4))
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sd_sdo <= reply3[~bit_cnt];
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// ---------- read state machine processing -------------
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case(read_state)
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RD_STATE_IDLE: ;
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// don't do anything
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// wait until the IO controller is free and issue a read
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RD_STATE_WAIT_BUSY:
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if (~sd_busy) begin
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sd_buff_sel <= 0;
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sd_lba <= sdhc?args[39:8]:{9'd0, args[39:17]};
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sd_rd <= 1; // trigger request to io controller
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sd_busy <= 1;
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read_state <= RD_STATE_WAIT_IO;
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end
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// waiting for io controller to return data
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RD_STATE_WAIT_IO: begin
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buffer_ptr <= 0;
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if(~sd_busy) begin
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if (terminate_cmd) begin
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cmd <= 0;
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read_state <= RD_STATE_IDLE;
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end else if (bit_cnt == 7)
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read_state <= RD_STATE_SEND_TOKEN;
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end
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end
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// send data token
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RD_STATE_SEND_TOKEN: begin
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if(~sd_busy) begin
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sd_sdo <= READ_DATA_TOKEN[~bit_cnt];
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if(bit_cnt == 7) begin
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read_state <= RD_STATE_SEND_DATA; // next: send data
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conf_buff_ptr <= (cmd == 8'h4a) ? 5'h0 : 5'h10;
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end
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end
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end
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// send data
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RD_STATE_SEND_DATA: begin
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if(cmd == 8'h51 || (cmd == 8'h52 && !terminate_cmd)) // CMD17: READ_SINGLE_BLOCK, CMD18: READ_MULTIPLE_BLOCK
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sd_sdo <= buffer_dout[~bit_cnt];
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else if(cmd == 8'h49 || cmd == 8'h4a) // CMD9: SEND_CSD, CMD10: SEND CID
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sd_sdo <= conf_byte[~bit_cnt];
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if(bit_cnt == 7) begin
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// sent 512 sector data bytes?
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if((cmd == 8'h51) && &buffer_ptr[8:0])
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read_state <= RD_STATE_IDLE; // next: send crc. It's ignored so return to idle state
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if (cmd == 8'h52) begin
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if (terminate_cmd) begin
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read_state <= RD_STATE_IDLE;
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cmd <= 0;
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end else if (buffer_ptr[8:0] == 10) begin
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// prefetch the next sector into the other buffer
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sd_lba <= sd_lba + 1'd1;
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sd_rd <= 1;
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sd_busy <= 1;
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sd_buff_sel <= !sd_buff_sel;
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end else if (&buffer_ptr[8:0]) begin
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delay_cnt <= 20;
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read_state <= RD_STATE_DELAY;
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end
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end
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// sent 16 cid/csd data bytes?
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if(((cmd == 8'h49)||(cmd == 8'h4a)) && conf_buff_ptr[3:0] == 4'h0f) // && (buffer_rptr == 16))
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read_state <= RD_STATE_IDLE; // return to idle state
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buffer_ptr <= buffer_ptr + 1'd1;
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conf_buff_ptr<= conf_buff_ptr+ 1'd1;
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end
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end
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RD_STATE_DELAY:
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if(bit_cnt == 7) begin
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if (delay_cnt == 0) begin
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read_state <= RD_STATE_SEND_TOKEN;
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end else begin
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delay_cnt <= delay_cnt - 1'd1;
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end
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end
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endcase
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// ------------------ write support ----------------------
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// send write data response
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if(write_state == WR_STATE_SEND_DRESP)
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sd_sdo <= WRITE_DATA_RESPONSE[~bit_cnt];
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// busy after write until the io controller sends ack
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if(write_state == WR_STATE_WRITE || write_state == WR_STATE_BUSY)
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sd_sdo <= 1'b0;
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end
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// spi receiver
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// cs is active low
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if(sd_cs == 1) begin
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bit_cnt <= 3'd0;
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terminate_cmd <= 0;
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cmd <= 0;
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read_state <= RD_STATE_IDLE;
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reply_len <= 0;
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end else if (~old_sd_sck & sd_sck) begin
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bit_cnt <= bit_cnt + 3'd1;
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// assemble byte
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if(bit_cnt != 7)
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sbuf[6:0] <= { sbuf[5:0], sd_sdi };
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else begin
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// finished reading one byte
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// byte counter runs against 15 byte boundary
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if(byte_cnt != 15)
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byte_cnt <= byte_cnt + 4'd1;
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// byte_cnt > 6 -> complete command received
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// first byte of valid command is 01xxxxxx
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// don't accept new commands (except STOP TRANSMISSION) once a write or read command has been accepted
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if((byte_cnt > (reply_len == 0 ? 5 : (5+NCR+reply_len))) &&
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(write_state == WR_STATE_IDLE) &&
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(read_state == RD_STATE_IDLE || (read_state != RD_STATE_IDLE && { sbuf, sd_sdi} == 8'h4c)) &&
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sbuf[6:5] == 2'b01)
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begin
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byte_cnt <= 4'd0;
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terminate_cmd <= 0;
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if ({ sbuf, sd_sdi } == 8'h4c) begin
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terminate_cmd <= 1;
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end else
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cmd <= { sbuf, sd_sdi};
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end
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// parse additional command bytes
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if(byte_cnt == 0) args[39:32] <= { sbuf, sd_sdi};
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if(byte_cnt == 1) args[31:24] <= { sbuf, sd_sdi};
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if(byte_cnt == 2) args[23:16] <= { sbuf, sd_sdi};
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if(byte_cnt == 3) args[15:8] <= { sbuf, sd_sdi};
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if(byte_cnt == 4) args[7:0] <= { sbuf, sd_sdi};
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// last byte received, evaluate
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if(byte_cnt == 5) begin
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// default:
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reply <= 8'h04; // illegal command
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reply_len <= 4'd0; // no extra reply bytes
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cmd55 <= 0;
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// CMD0: GO_IDLE_STATE
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if(cmd == 8'h40) begin
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card_is_reset <= 1'b1;
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reply <= 8'h01; // ok, busy
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end
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// every other command is only accepted after a reset
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else if(card_is_reset) begin
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// CMD12: STOP_TRANSMISSION
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if (terminate_cmd)
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reply <= 8'h00; // ok
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else case(cmd)
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// CMD1: SEND_OP_COND
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8'h41: reply <= 8'h00; // ok, not busy
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// CMD8: SEND_IF_COND (V2 only)
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8'h48: begin
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reply <= 8'h01; // ok, busy
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reply0 <= 8'h00;
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reply1 <= 8'h00;
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reply2 <= { 4'b0, args[19:16] };
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reply3 <= args[15:8];
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reply_len <= 4'd4;
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end
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// CMD9: SEND_CSD
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8'h49: reply <= 8'h00; // ok
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// CMD10: SEND_CID
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8'h4a: reply <= 8'h00; // ok
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// CMD13: SEND_STATUS
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8'h4d: begin
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reply <= 8'h00; // ok
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reply0 <=8'h00;
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reply_len <= 4'd1;
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end
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// CMD16: SET_BLOCKLEN
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8'h50:
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// we only support a block size of 512
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if(args[39:8] == 32'd512)
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reply <= 8'h00; // ok
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else
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reply <= 8'h40; // parmeter error
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// CMD17: READ_SINGLE_BLOCK
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|
8'h51: reply <= 8'h00; // ok
|
|
|
|
// CMD18: READ_MULTIPLE_BLOCK
|
|
8'h52: reply <= 8'h00; // ok
|
|
|
|
// CMD24: WRITE_BLOCK
|
|
// CMD25: WRITE_MULTIPLE_BLOCKS
|
|
8'h58, 8'h59: begin
|
|
reply <= 8'h00; // ok
|
|
buffer_ptr <= 0;
|
|
wr_first <= 1;
|
|
write_state <= WR_STATE_EXP_DTOKEN; // expect data token
|
|
end
|
|
|
|
// ACMD41: APP_SEND_OP_COND
|
|
8'h69: if(cmd55) begin
|
|
reply <= 8'h00; // ok, not busy
|
|
end
|
|
|
|
// CMD55: APP_COND
|
|
8'h77: begin
|
|
reply <= 8'h01; // ok, busy
|
|
cmd55 <= 1;
|
|
end
|
|
|
|
// CMD58: READ_OCR
|
|
8'h7a: begin
|
|
reply <= 8'h00; // ok
|
|
|
|
reply0 <= OCR[31:24]; // bit 30 = 1 -> high capacity card
|
|
reply1 <= OCR[23:16];
|
|
reply2 <= OCR[15:8];
|
|
reply3 <= OCR[7:0];
|
|
reply_len <= 4'd4;
|
|
end
|
|
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
// ---------- handle write -----------
|
|
case(write_state)
|
|
// don't do anything in idle state
|
|
WR_STATE_IDLE: ;
|
|
|
|
// waiting for data token
|
|
WR_STATE_EXP_DTOKEN:
|
|
if (sd_cs) write_state <= WR_STATE_IDLE;
|
|
else if (~old_sd_sck && sd_sck && bit_cnt == 7) begin
|
|
if({ sbuf, sd_sdi} == 8'hfd && cmd == 8'h59)
|
|
// stop multiple write (and wait until the last write finishes)
|
|
write_state <= WR_STATE_BUSY;
|
|
else
|
|
if({ sbuf, sd_sdi} == ((cmd == 8'h59) ? 8'hfc : 8'hfe))
|
|
write_state <= WR_STATE_RECV_DATA;
|
|
end
|
|
|
|
// transfer 512 bytes
|
|
WR_STATE_RECV_DATA:
|
|
if (sd_cs) write_state <= WR_STATE_IDLE;
|
|
else if (~old_sd_sck && sd_sck && bit_cnt == 7) begin
|
|
// push one byte into local buffer
|
|
buffer_write_strobe <= 1'b1;
|
|
buffer_din <= { sbuf, sd_sdi };
|
|
|
|
// all bytes written?
|
|
if(&buffer_ptr[8:0])
|
|
write_state <= WR_STATE_RECV_CRC0;
|
|
end
|
|
|
|
// transfer 1st crc byte
|
|
WR_STATE_RECV_CRC0:
|
|
if (sd_cs) write_state <= WR_STATE_IDLE;
|
|
else if (~old_sd_sck && sd_sck && bit_cnt == 7) write_state <= WR_STATE_RECV_CRC1;
|
|
|
|
// transfer 2nd crc byte
|
|
WR_STATE_RECV_CRC1:
|
|
if (sd_cs) write_state <= WR_STATE_IDLE;
|
|
else if (~old_sd_sck && sd_sck && bit_cnt == 7) write_state <= WR_STATE_SEND_DRESP;
|
|
|
|
// send data response
|
|
WR_STATE_SEND_DRESP:
|
|
if (sd_cs) write_state <= WR_STATE_IDLE;
|
|
else if (~old_sd_sck && sd_sck && bit_cnt == 7) write_state <= WR_STATE_WRITE;
|
|
|
|
WR_STATE_WRITE:
|
|
if (~sd_busy) begin
|
|
if (wr_first) begin
|
|
sd_buff_sel <= 0;
|
|
sd_lba <= sdhc?args[39:8]:{9'd0, args[39:17]};
|
|
wr_first <= 0;
|
|
end else begin
|
|
sd_buff_sel <= !sd_buff_sel;
|
|
sd_lba <= sd_lba + 1'd1;
|
|
end
|
|
sd_wr <= 1; // trigger write request to io controller
|
|
sd_busy <= 1;
|
|
|
|
if (sd_cs || cmd == 8'h58)
|
|
write_state <= WR_STATE_BUSY;
|
|
else
|
|
write_state <= WR_STATE_EXP_DTOKEN; // multi-sector writes
|
|
|
|
end
|
|
|
|
WR_STATE_BUSY:
|
|
if (~sd_busy) write_state <= WR_STATE_IDLE;
|
|
|
|
default: ;
|
|
endcase
|
|
end
|
|
|
|
endmodule
|
|
|
|
module sd_card_dpram #(parameter DATAWIDTH=8, ADDRWIDTH=9)
|
|
(
|
|
input clock_a,
|
|
input [ADDRWIDTH-1:0] address_a,
|
|
input [DATAWIDTH-1:0] data_a,
|
|
input wren_a,
|
|
output reg [DATAWIDTH-1:0] q_a,
|
|
|
|
input clock_b,
|
|
input [ADDRWIDTH-1:0] address_b,
|
|
input [DATAWIDTH-1:0] data_b,
|
|
input wren_b,
|
|
output reg [DATAWIDTH-1:0] q_b
|
|
);
|
|
|
|
reg [DATAWIDTH-1:0] ram[0:(1<<ADDRWIDTH)-1];
|
|
|
|
always @(posedge clock_a) begin
|
|
q_a <= ram[address_a];
|
|
if(wren_a) begin
|
|
q_a <= data_a;
|
|
ram[address_a] <= data_a;
|
|
end
|
|
end
|
|
|
|
always @(posedge clock_b) begin
|
|
q_b <= ram[address_b];
|
|
if(wren_b) begin
|
|
q_b <= data_b;
|
|
ram[address_b] <= data_b;
|
|
end
|
|
end
|
|
|
|
endmodule
|