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Silkscreen tweaks

This commit is contained in:
Tor-Eirik Bakke Lunde 2020-01-10 22:15:18 +01:00
parent 4d0855cde5
commit 813b28022c
15 changed files with 232 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
platforms/PP 6502/PP 6502.kicad_pcb
View File

@ -3,9 +3,9 @@
(general
(links 121)
(no_connects 0)
(area 93.345 43.815 204.470001 161.290001)
(area 100.254999 48.184999 199.465001 147.395001)
(thickness 1.6)
(drawings 463)
(drawings 471)
(tracks 663)
(zones 0)
(modules 21)
@ -1825,12 +1825,12 @@
)
)
(module Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm (layer F.Cu) (tedit 59650532) (tstamp 5DFD4C57)
(module Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm (layer F.Cu) (tedit 5E18E8C0) (tstamp 5DFD4C57)
(at 134.62 57.15 90)
(descr "Through hole straight pin header, 1x03, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x03 2.54mm single row")
(path /5E02AB75)
(fp_text reference JP3 (at 0 -2.33 90) (layer F.SilkS)
(fp_text reference JP3 (at 0 -2.54 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VIA_CLK (at 0 7.41 90) (layer F.Fab)
@ -1867,6 +1867,20 @@
)
)
(gr_line (start 161.29 88.265) (end 161.925 88.9) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 161.29 62.23) (end 161.29 88.265) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 160.655 61.595) (end 161.29 62.23) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 159.385 61.595) (end 160.655 61.595) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 170.815 88.9) (end 161.925 88.9) (angle 90) (layer B.SilkS) (width 0.2))
(gr_text IO3 (at 182.88 88.9) (layer B.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror))
)
(gr_text "- $170F" (at 173.99 88.9) (layer B.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror))
)
(gr_text $1700 (at 179.07 88.9) (layer B.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.1)) (justify mirror))
)
(gr_line (start 132.715 59.055) (end 141.605 59.055) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 132.715 55.245) (end 132.715 59.055) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 133.985 55.245) (end 132.715 55.245) (angle 90) (layer B.SilkS) (width 0.2))
@ -2742,7 +2756,7 @@
(gr_text R/~W (at 139.7 52.705 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify left))
)
(gr_text READY (at 137.16 52.705 270) (layer F.SilkS)
(gr_text RDY (at 137.16 52.705 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify left))
)
(gr_text SYNC (at 134.62 52.705 270) (layer F.SilkS)

6
platforms/PP 6502/PP 6502.pro
View File

@ -1,4 +1,4 @@
update=31/12/2019 01:19:24
update=10/01/2020 22:14:41
version=1
last_client=kicad
[pcbnew]
@ -23,8 +23,6 @@ ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[eeschema]
version=1
LibDir=library;../../common/library
@ -72,3 +70,5 @@ NetFmtName=Pcbnew
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[general]
version=1

4
platforms/PP 6502/PP 6502.sch
View File

@ -1245,7 +1245,7 @@ F 3 "" H 6500 2225 50 0001 C CNN
1 6500 2225
0 -1 -1 0
$EndComp
Text Label 7200 2550 2 60 ~ 0
Text Label 7175 2550 2 60 ~ 0
~IO3
Wire Wire Line
6500 2475 6500 2550
@ -1386,4 +1386,6 @@ Wire Bus Line
750 4650 1050 4650
Text Notes 850 4100 0 60 ~ 0
6522 clock selection jumper, solder\na link from 1-2 for most 6502-based\ncomputers. 2-3 for 6800-based CPUs.
Text Notes 6950 2650 0 60 ~ 0
$1700
$EndSCHEMATC

2
platforms/PP 6502/export/PP 6502-B.Cu.gbl
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@ -1,7 +1,7 @@
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2
platforms/PP 6502/export/PP 6502-B.Mask.gbs
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2
platforms/PP 6502/export/PP 6502-B.Paste.gbp
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181
platforms/PP 6502/export/PP 6502-B.SilkS.gbo
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2
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platforms/PP 6502/export/PP 6502.pdf
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