Apple-1-HW/RC-Project-Board
1
0
Fork 0
mirror of https://github.com/tebl/RC-Project-Board.git synced 2025-01-01 23:30:35 +00:00
Code Issues Projects Releases Wiki Activity

Added pictures

Browse Source
This commit is contained in:
Tor-Eirik Bakke Lunde 2021-01-25 16:26:57 +01:00
parent e3c6ef61d8
commit 98832d0c3a
11 changed files with 296 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
platforms/PP 6502/library/breadboard.dcm Normal file
View File

@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

20
platforms/PP 6502/library/breadboard.lib Normal file
View File

@ -0,0 +1,20 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# Breadboard
#
DEF Breadboard BB 0 40 Y Y 1 F N
F0 "BB" 0 475 60 H V C CNN
F1 "Breadboard" 0 -425 60 H V C CNN
F2 "" -50 0 60 H I C CNN
F3 "" -50 0 60 H I C CNN
DRAW
S -400 -275 375 -350 0 1 0 f
S -400 -25 375 -275 0 1 0 N
S -400 -25 375 25 0 1 0 f
S -400 25 375 275 0 1 0 N
S -400 275 375 350 0 1 0 f
ENDDRAW
ENDDEF
#
#End Library

82
platforms/PP 6502/modules/breadboard.pretty/RND 255-00005.kicad_mod Normal file
View File

@ -0,0 +1,82 @@
(module "RND 255-00005" (layer F.Cu) (tedit 5DE6EC19)
(fp_text reference REF** (at 0 4.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "RND 255-00005" (at 0 -4) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 38 26) (end 38.5 26) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 26) (end 38.5 25.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 25.5) (end 39 25.5) (layer F.SilkS) (width 0.15))
(fp_line (start 39 25.5) (end 39 25) (layer F.SilkS) (width 0.15))
(fp_line (start 39 25) (end 38.5 25) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 25) (end 38.5 24.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 24.5) (end 38 24.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38 24.5) (end 38 25) (layer F.SilkS) (width 0.15))
(fp_line (start 38 25) (end 37.5 25) (layer F.SilkS) (width 0.15))
(fp_line (start 37.5 25) (end 37.5 25.5) (layer F.SilkS) (width 0.15))
(fp_line (start 37.5 25.5) (end 38 25.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38 25.5) (end 38 26) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 20) (end 38 20) (layer F.SilkS) (width 0.15))
(fp_line (start 38 20) (end 38 21.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38 21.5) (end 38.5 21.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 21.5) (end 38.5 20) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 -20) (end 39 -20) (layer F.SilkS) (width 0.15))
(fp_line (start 39 -20) (end 39 -20.5) (layer F.SilkS) (width 0.15))
(fp_line (start 39 -20.5) (end 39.5 -20.5) (layer F.SilkS) (width 0.15))
(fp_line (start 39.5 -20.5) (end 39.5 -21) (layer F.SilkS) (width 0.15))
(fp_line (start 39.5 -21) (end 39 -21) (layer F.SilkS) (width 0.15))
(fp_line (start 39 -21) (end 39 -21.5) (layer F.SilkS) (width 0.15))
(fp_line (start 39 -21.5) (end 38.5 -21.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 -21.5) (end 38.5 -21) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 -21) (end 38 -21) (layer F.SilkS) (width 0.15))
(fp_line (start 38 -21) (end 38 -20.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38 -20.5) (end 38.5 -20.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 -20.5) (end 38.5 -20) (layer F.SilkS) (width 0.15))
(fp_line (start 39 -26) (end 38.5 -26) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 -26) (end 38.5 -24.5) (layer F.SilkS) (width 0.15))
(fp_line (start 38.5 -24.5) (end 39 -24.5) (layer F.SilkS) (width 0.15))
(fp_line (start 39 -24.5) (end 39 -26) (layer F.SilkS) (width 0.15))
(fp_line (start -39 -20) (end -38.5 -20) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 -20) (end -38.5 -20.5) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 -20.5) (end -38 -20.5) (layer F.SilkS) (width 0.15))
(fp_line (start -38 -20.5) (end -38 -21) (layer F.SilkS) (width 0.15))
(fp_line (start -38 -21) (end -38.5 -21) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 -21) (end -38.5 -21.5) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 -21.5) (end -39 -21.5) (layer F.SilkS) (width 0.15))
(fp_line (start -39 -21.5) (end -39 -21) (layer F.SilkS) (width 0.15))
(fp_line (start -39 -21) (end -39.5 -21) (layer F.SilkS) (width 0.15))
(fp_line (start -39.5 -21) (end -39.5 -20.5) (layer F.SilkS) (width 0.15))
(fp_line (start -39.5 -20.5) (end -39 -20.5) (layer F.SilkS) (width 0.15))
(fp_line (start -39 -20.5) (end -39 -20) (layer F.SilkS) (width 0.15))
(fp_line (start -39 -26) (end -39 -24.5) (layer F.SilkS) (width 0.15))
(fp_line (start -39 -24.5) (end -38.5 -24.5) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 -24.5) (end -38.5 -26) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 -26) (end -39 -26) (layer F.SilkS) (width 0.15))
(fp_line (start -39 24.5) (end -38.5 24.5) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 24.5) (end -38.5 25) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 25) (end -38 25) (layer F.SilkS) (width 0.15))
(fp_line (start -38 25) (end -38 25.5) (layer F.SilkS) (width 0.15))
(fp_line (start -38 25.5) (end -38.5 25.5) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 25.5) (end -38.5 26) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 26) (end -39 26) (layer F.SilkS) (width 0.15))
(fp_line (start -39 26) (end -39 25.5) (layer F.SilkS) (width 0.15))
(fp_line (start -39 25.5) (end -39.5 25.5) (layer F.SilkS) (width 0.15))
(fp_line (start -39.5 25.5) (end -39.5 25) (layer F.SilkS) (width 0.15))
(fp_line (start -39.5 25) (end -39 25) (layer F.SilkS) (width 0.15))
(fp_line (start -39 25) (end -39 24.5) (layer F.SilkS) (width 0.15))
(fp_line (start -39 20) (end -38.5 20) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 20) (end -38.5 21.5) (layer F.SilkS) (width 0.15))
(fp_line (start -38.5 21.5) (end -39 21.5) (layer F.SilkS) (width 0.15))
(fp_line (start -39 20) (end -39 21.5) (layer F.SilkS) (width 0.15))
(fp_line (start 42 -1) (end -42 -1) (layer F.SilkS) (width 0.15))
(fp_line (start -42 1) (end 42 1) (layer F.SilkS) (width 0.15))
(fp_line (start 42 18.5) (end -42 18.5) (layer F.SilkS) (width 0.15))
(fp_line (start 42 -18.5) (end -42 -18.5) (layer F.SilkS) (width 0.15))
(fp_line (start -42 27.5) (end 42 27.5) (layer F.SilkS) (width 0.15))
(fp_line (start -42 -27.5) (end 42 -27.5) (layer F.SilkS) (width 0.15))
(fp_line (start -42 0) (end -42 27.5) (layer F.SilkS) (width 0.15))
(fp_line (start -42 0) (end -42 -27.5) (layer F.SilkS) (width 0.15))
(fp_line (start 42 0) (end 42 27.5) (layer F.SilkS) (width 0.15))
(fp_line (start 42 0) (end 42 -27.5) (layer F.SilkS) (width 0.15))
)

BIN
platforms/PP Arduino/gallery/2020-03-25 20.33.52.jpg Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 452 KiB

BIN
platforms/PP Arduino/gallery/2020-03-25 20.46.18.jpg Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 491 KiB

BIN
projects/PB-003 LED Cube/gallery/2020-03-25 20.46.32.jpg Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 457 KiB

14
projects/PB-003 LED Cube/software/Arduino Cube/cube.code-workspace
View File

@ -1,9 +1,13 @@
{
"folders": [
{
"name": "Arduino Cube",
"path": "."
}
],
{
"name": "Arduino Cube",
"path": "."
},
{
"name": "ExRAM",
"path": "..\\..\\..\\..\\..\\RC1\\software\\arduino\\ExRAM"
}
],
"settings": {}
}

3
projects/PB-003 LED Cube/software/BE6502/001-Alternate/assemble.bat Normal file
View File

@ -0,0 +1,3 @@
sbasm.py cubed.asm
type cubed.list
pause

86
projects/PB-003 LED Cube/software/BE6502/001-Alternate/cubed.asm Normal file
View File

@ -0,0 +1,86 @@
.CR 6502
.TF cubed.hex,INT
.LF cubed.list
* ----------------------------------------------------------------------
* SIMPLE ALTERNATING PATTERN SHOWN ACROSS THE VARIOUS LED CUBE LAYERS,
* CONTROL SIGNALS WILL BE MIRRORED OUT TO SBC LEDS TO HELP WITH
* DEBUGGING AND ENSURE BATTERIES DRAIN EXTREMELY FAST.
CURRENT .EQ $04
VIA .EQ $6000 SBC VIA
ORB .EQ VIA PORT B DATA
ORA .EQ VIA+1 PORT A DATA
DDRB .EQ VIA+2 PORT B DATA-DIRECTION
DDRA .EQ VIA+3 PORT A DATA-DIRECTION
PP_VIA .EQ $4000 PP VIA
PP_ORB .EQ PP_VIA
PP_ORA .EQ PP_VIA+1
PP_DDRB .EQ PP_VIA+2
PP_DDRA .EQ PP_VIA+3
.OR $8000
.TA $0000
START LDA #$FF SET SBC VIA PORT B AS OUTPUTS
STA DDRB
LDA #%1111111 PORT A, USED TO LOAD VALUES FOR LED-S
STA PP_DDRA INTO LATCHES.
LDA #%0011111 PORT B, USED FOR CONTROL LINES AS WELL AS
STA PP_DDRB SWITCHES.
LDA #$55 INITIAL VALUE TO START WITH
STA CURRENT
OUTPUT LDA #%00111111 DISABLE ALL LAYERS
STA PP_ORB
LDA #$FF ALTERNATE LEDS ON
EOR CURRENT THE LAYERS BY DOING
STA CURRENT AN EXCLUSIVE OR ON
STA PP_ORA THE CURRENT VALUE,
JSR LATCH THEN LATCH THEM.
JSR DELAY
LDA #%00111011
STA PP_ORB
STA ORB
JSR DELAY
LDA #%00110111
STA PP_ORB
STA ORB
JSR DELAY
LDA #%00101111
STA PP_ORB
STA ORB
JSR DELAY
LDA #%00011111
STA PP_ORB
STA ORB
JMP OUTPUT
LATCH LDA #%00111100 LATCH VALUES BY
STA PP_ORB TAKING THE CONTROLS
LDA #%00111111 LOW AND THEN
STA PP_ORB HIGH AGAIN.
RTS
DELAY LDX #$FF LOAD DELAY VALUE INTO X
LPDLY DEX DECREMENT X
BNE LPDLY
RTS
* ---------------------------------------------------------
* STORE VECTORS AT END OF EPROM.
.OR $FFFA
.TA $7FFA
.DA START NMI VECTOR
.DA START RESET VECTOR
.DA START IRQ VECTOR

9
projects/PB-003 LED Cube/software/BE6502/001-Alternate/cubed.hex Normal file
View File

@ -0,0 +1,9 @@
:10000000A9FF8D0260A97F8D0340A91F8D0240A921
:10001000558504A93F8D0040A9FF450485048D0145
:1000200040205380205E80A93B8D00408D006020E1
:100030005E80A9378D00408D0060205E80A92F8DE5
:1000400000408D0060205E80A91F8D00408D006003
:100050004C1380A93C8D0040A93F8D004060A2FF59
:04006000CAD0FD60A5
:067FFA0000800080008001
:00000001FF

84
projects/PB-003 LED Cube/software/BE6502/001-Alternate/cubed.list Normal file
View File

@ -0,0 +1,84 @@
0000- 4
0000- 5 * ----------------------------------------------------------------------
0000- 6 * SAMPLE PROGRAM AS FOUND IN THE BOOK "6502 APPLICATIONS BOOK" BY RODNEY
0000- 7 * ZAKS, IT IS A SOFTWARE METHOD OF CONTROLLING SOUND DURATION.ADAPTED FOR
0000- 8 * THE KIM-1 WITH THE 6502 PROJECT PLATFORM BOARD / COVOX PROJECT BOARD.
0000- 9 *
0004- 10 CURRENT .EQ $04
0000- 11
6000- 12 VIA .EQ $6000 SBC VIA
6000- 13 ORB .EQ VIA PORT B DATA
6001- 14 ORA .EQ VIA+1 PORT A DATA
6002- 15 DDRB .EQ VIA+2 PORT B DATA-DIRECTION
6003- 16 DDRA .EQ VIA+3 PORT A DATA-DIRECTION
0000- 17
4000- 18 PP_VIA .EQ $4000 PP VIA
4000- 19 PP_ORB .EQ PP_VIA
4001- 20 PP_ORA .EQ PP_VIA+1
4002- 21 PP_DDRB .EQ PP_VIA+2
4003- 22 PP_DDRA .EQ PP_VIA+3
0000- 23
8000- 24 .OR $8000
8000- 25 .TA $0000
8000-A9 FF 26 ( 2) START LDA #$FF SET SBC VIA PORT B AS OUTPUTS
8002-8D 02 60 27 ( 4) STA DDRB
8005- 28
8005-A9 7F 29 ( 2) LDA #%1111111 PORT A, USED TO LOAD VALUES FOR LED-S
8007-8D 03 40 30 ( 4) STA PP_DDRA INTO LATCHES.
800A-A9 1F 31 ( 2) LDA #%0011111 PORT B, USED FOR CONTROL LINES AS WELL AS
800C-8D 02 40 32 ( 4) STA PP_DDRB SWITCHES.
800F- 33
800F-A9 55 34 ( 2) LDA #$55
8011-85 04 35 ( 2) STA CURRENT
8013- 36
8013-A9 3F 37 ( 2) OUTPUT LDA #%00111111 DISABLE ALL LAYERS
8015-8D 00 40 38 ( 4) STA PP_ORB
8018- 39
8018-A9 FF 40 ( 2) LDA #$FF ALTERNATE LEDS ON
801A-45 04 41 ( 3) EOR CURRENT THE LAYERS BY DOING
801C-85 04 42 ( 2) STA CURRENT AN EXCLUSIVE OR ON
801E-8D 01 40 43 ( 4) STA PP_ORA THE CURRENT VALUE,
8021-20 53 80 44 ( 6) JSR LATCH THEN LATCH THEM.
8024- 45
8024-20 5E 80 46 ( 6) JSR DELAY
8027-A9 3B 47 ( 2) LDA #%00111011
8029-8D 00 40 48 ( 4) STA PP_ORB
802C-8D 00 60 49 ( 4) STA ORB
802F- 50
802F-20 5E 80 51 ( 6) JSR DELAY
8032-A9 37 52 ( 2) LDA #%00110111
8034-8D 00 40 53 ( 4) STA PP_ORB
8037-8D 00 60 54 ( 4) STA ORB
803A- 55
803A-20 5E 80 56 ( 6) JSR DELAY
803D-A9 2F 57 ( 2) LDA #%00101111
803F-8D 00 40 58 ( 4) STA PP_ORB
8042-8D 00 60 59 ( 4) STA ORB
8045- 60
8045-20 5E 80 61 ( 6) JSR DELAY
8048-A9 1F 62 ( 2) LDA #%00011111
804A-8D 00 40 63 ( 4) STA PP_ORB
804D-8D 00 60 64 ( 4) STA ORB
8050- 65
8050-4C 13 80 66 ( 3) JMP OUTPUT
8053- 67
8053-A9 3C 68 ( 2) LATCH LDA #%00111100 LATCH VALUES BY
8055-8D 00 40 69 ( 4) STA PP_ORB TAKING THE CONTROLS
8058-A9 3F 70 ( 2) LDA #%00111111 LOW AND THEN
805A-8D 00 40 71 ( 4) STA PP_ORB HIGH AGAIN.
805D-60 72 ( 6) RTS
805E- 73
805E- 74
805E-A2 FF 75 ( 2) DELAY LDX #$FF LOAD DELAY VALUE INTO X
8060-CA 76 ( 2) LPDLY DEX DECREMENT X
8061-D0 FD 77 (2**) BNE LPDLY
8063-60 78 ( 6) RTS
8064- 79
8064- 80
8064- 81 * ---------------------------------------------------------
8064- 82 * STORE VECTORS AT END OF EPROM.
FFFA- 83 .OR $FFFA
FFFA- 84 .TA $7FFA
FFFA-00 80 85 .DA START NMI VECTOR
FFFC-00 80 86 .DA START RESET VECTOR
FFFE-00 80 87 .DA START IRQ VECTOR