diff --git a/RC6502 VDU/RC6502 VDU.kicad_pcb b/RC6502 VDU/RC6502 VDU.kicad_pcb index d8079aa..acffe72 100644 --- a/RC6502 VDU/RC6502 VDU.kicad_pcb +++ b/RC6502 VDU/RC6502 VDU.kicad_pcb @@ -1,15 +1,15 @@ (kicad_pcb (version 4) (host pcbnew 4.0.7) (general - (links 216) + (links 214) (no_connects 0) (area 52.629999 44.374999 151.840001 144.220001) (thickness 1.6) - (drawings 68) - (tracks 1863) + (drawings 66) + (tracks 1840) (zones 0) - (modules 35) - (nets 86) + (modules 34) + (nets 85) ) (page A4) @@ -109,73 +109,72 @@ (net 16 A1) (net 17 A0) (net 18 PHI2) - (net 19 PHI0) - (net 20 "Net-(J1-Pad22)") - (net 21 R/~W) - (net 22 D0) - (net 23 D1) - (net 24 D2) - (net 25 D3) - (net 26 D4) - (net 27 D5) - (net 28 D6) - (net 29 D7) - (net 30 "Net-(J2-Pad1)") - (net 31 VDU_BASE) - (net 32 "Net-(J2-Pad3)") - (net 33 "Net-(J2-Pad5)") - (net 34 "Net-(J2-Pad7)") - (net 35 "Net-(J2-Pad9)") - (net 36 "Net-(J3-Pad1)") - (net 37 "Net-(J3-Pad2)") - (net 38 "Net-(J3-Pad3)") - (net 39 Y) - (net 40 VDU_CLK) - (net 41 "Net-(J8-Pad2)") - (net 42 ~VDU_DISABLE) - (net 43 ~FS) - (net 44 VA12) - (net 45 VD6) - (net 46 VA0) - (net 47 VD0) - (net 48 VA1) - (net 49 VD1) - (net 50 VA2) - (net 51 VD2) - (net 52 VA3) - (net 53 VD3) - (net 54 VA4) - (net 55 VD4) - (net 56 GM2) - (net 57 VD5) - (net 58 GM1) - (net 59 GM0) - (net 60 VD7) - (net 61 VA5) - (net 62 VA6) - (net 63 S/~A) - (net 64 VA7) - (net 65 G/~A) - (net 66 VA8) - (net 67 VA9) - (net 68 VA10) - (net 69 CSS) - (net 70 VA11) - (net 71 VA14) - (net 72 VA13) - (net 73 RAM_RW) - (net 74 ~CS_RAM_EXT) - (net 75 "Net-(U10-Pad2)") - (net 76 "Net-(U10-Pad1)") - (net 77 GND) - (net 78 ~REG0) - (net 79 "Net-(U10-Pad6)") - (net 80 "Net-(U10-Pad5)") - (net 81 ~REG1) - (net 82 "Net-(U10-Pad3)") - (net 83 "Net-(U10-Pad4)") - (net 84 "Net-(J2-Pad11)") - (net 85 "Net-(J2-Pad13)") + (net 19 "Net-(J1-Pad22)") + (net 20 R/~W) + (net 21 D0) + (net 22 D1) + (net 23 D2) + (net 24 D3) + (net 25 D4) + (net 26 D5) + (net 27 D6) + (net 28 D7) + (net 29 "Net-(J2-Pad1)") + (net 30 VDU_BASE) + (net 31 "Net-(J2-Pad3)") + (net 32 "Net-(J2-Pad5)") + (net 33 "Net-(J2-Pad7)") + (net 34 "Net-(J2-Pad9)") + (net 35 "Net-(J3-Pad1)") + (net 36 "Net-(J3-Pad2)") + (net 37 "Net-(J3-Pad3)") + (net 38 Y) + (net 39 VDU_CLK) + (net 40 "Net-(J8-Pad2)") + (net 41 ~VDU_DISABLE) + (net 42 ~FS) + (net 43 VA12) + (net 44 VD6) + (net 45 VA0) + (net 46 VD0) + (net 47 VA1) + (net 48 VD1) + (net 49 VA2) + (net 50 VD2) + (net 51 VA3) + (net 52 VD3) + (net 53 VA4) + (net 54 VD4) + (net 55 GM2) + (net 56 VD5) + (net 57 GM1) + (net 58 GM0) + (net 59 VD7) + (net 60 VA5) + (net 61 VA6) + (net 62 S/~A) + (net 63 VA7) + (net 64 G/~A) + (net 65 VA8) + (net 66 VA9) + (net 67 VA10) + (net 68 CSS) + (net 69 VA11) + (net 70 VA14) + (net 71 VA13) + (net 72 RAM_RW) + (net 73 ~CS_RAM_EXT) + (net 74 "Net-(U10-Pad2)") + (net 75 "Net-(U10-Pad1)") + (net 76 GND) + (net 77 ~REG0) + (net 78 "Net-(U10-Pad6)") + (net 79 "Net-(U10-Pad5)") + (net 80 ~REG1) + (net 81 "Net-(U10-Pad3)") + (net 82 "Net-(U10-Pad4)") + (net 83 "Net-(J2-Pad11)") + (net 84 "Net-(J2-Pad13)") (net_class Default "This is the default net class." (clearance 0.2) @@ -232,7 +231,6 @@ (add_net "Net-(U10-Pad4)") (add_net "Net-(U10-Pad5)") (add_net "Net-(U10-Pad6)") - (add_net PHI0) (add_net PHI2) (add_net R/~W) (add_net RAM_RW) @@ -302,7 +300,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -341,7 +339,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -380,7 +378,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -419,7 +417,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -458,7 +456,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -497,7 +495,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -536,7 +534,7 @@ (pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -575,7 +573,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -614,7 +612,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -653,7 +651,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1196,37 +1194,36 @@ (pad 16 thru_hole oval (at 0 38.1 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (net 17 A0)) (pad 17 thru_hole oval (at 0 40.64 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 18 thru_hole oval (at 0 43.18 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (net 1 VCC)) (pad 19 thru_hole oval (at 0 45.72 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (net 18 PHI2)) (pad 20 thru_hole oval (at 0 48.26 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) - (pad 21 thru_hole oval (at 0 50.8 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 19 PHI0)) + (pad 21 thru_hole oval (at 0 50.8 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (pad 22 thru_hole oval (at 0 53.34 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 20 "Net-(J1-Pad22)")) + (net 19 "Net-(J1-Pad22)")) (pad 23 thru_hole oval (at 0 55.88 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (pad 24 thru_hole oval (at 0 58.42 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 21 R/~W)) + (net 20 R/~W)) (pad 25 thru_hole oval (at 0 60.96 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (pad 26 thru_hole oval (at 0 63.5 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (pad 27 thru_hole oval (at 0 66.04 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 22 D0)) + (net 21 D0)) (pad 28 thru_hole oval (at 0 68.58 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 23 D1)) + (net 22 D1)) (pad 29 thru_hole oval (at 0 71.12 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 24 D2)) + (net 23 D2)) (pad 30 thru_hole oval (at 0 73.66 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 25 D3)) + (net 24 D3)) (pad 31 thru_hole oval (at 0 76.2 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 26 D4)) + (net 25 D4)) (pad 32 thru_hole oval (at 0 78.74 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 27 D5)) + (net 26 D5)) (pad 33 thru_hole oval (at 0 81.28 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 28 D6)) + (net 27 D6)) (pad 34 thru_hole oval (at 0 83.82 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 29 D7)) + (net 28 D7)) (pad 35 thru_hole oval (at 0 86.36 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (pad 36 thru_hole oval (at 0 88.9 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (pad 37 thru_hole oval (at 0 91.44 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) @@ -1342,11 +1339,11 @@ (fp_line (start -4.8006 4.99872) (end -4.8006 -6.80212) (layer F.SilkS) (width 0.381)) (fp_line (start 4.8006 -6.79958) (end 4.8006 5.00126) (layer F.SilkS) (width 0.381)) (pad 2 thru_hole oval (at 3.81 -3.81 90) (size 1.99898 3.19786) (drill oval 0.99568 2.1971) (layers *.Cu *.Mask F.SilkS) - (net 41 "Net-(J8-Pad2)")) + (net 40 "Net-(J8-Pad2)")) (pad 1 thru_hole oval (at 0 -1.27 90) (size 3.19786 1.99898) (drill oval 2.1971 0.99568) (layers *.Cu *.Mask F.SilkS) - (net 77 GND)) + (net 76 GND)) (pad 2 thru_hole oval (at -3.81 -3.81 90) (size 1.99898 3.19786) (drill oval 0.99568 2.1971) (layers *.Cu *.Mask F.SilkS) - (net 41 "Net-(J8-Pad2)")) + (net 40 "Net-(J8-Pad2)")) (model walter/conn_av/rca_yellow.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1384,9 +1381,9 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 31 VDU_BASE)) + (net 30 VDU_BASE)) (pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 42 ~VDU_DISABLE)) + (net 41 ~VDU_DISABLE)) (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1394,55 +1391,15 @@ ) ) - (module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 5C06EFCC) (tstamp 5C06E6C3) - (at 95.885 135.255) - (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row") - (tags "Through hole pin header THT 1x02 2.54mm single row") - (path /5C05E5BB) - (fp_text reference JP2 (at 0 -2.54 180) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value PHI0_OUT (at 2.54 1.27 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_text user %R (at 0 -2.54 180) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 40 VDU_CLK)) - (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 19 PHI0)) - (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 5C06EFDA) (tstamp 5C06E6C9) - (at 89.535 135.255) + (module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 5C28B028) (tstamp 5C06E6C9) + (at 94.615 133.985 90) (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row") (tags "Through hole pin header THT 1x02 2.54mm single row") (path /5C0D03FF) - (fp_text reference JP3 (at 0 -2.54 180) (layer F.SilkS) + (fp_text reference JP3 (at 0 -2.54 270) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value INT_ON_FS (at 2.54 1.27 90) (layer F.SilkS) + (fp_text value INT_ON_FS (at -2.54 1.27 180) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) @@ -1460,13 +1417,13 @@ (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_text user %R (at 0 -2.54 180) (layer F.Fab) + (fp_text user %R (at 0 -2.54 270) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) - (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 43 ~FS)) - (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 20 "Net-(J1-Pad22)")) + (pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 42 ~FS)) + (pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 19 "Net-(J1-Pad22)")) (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1512,83 +1469,83 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 21 thru_hole oval (at 15.24 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 44 VA12)) + (net 43 VA12)) (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 45 VD6)) + (net 44 VD6)) (pad 22 thru_hole oval (at 15.24 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 46 VA0)) + (net 45 VA0)) (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 47 VD0)) + (net 46 VD0)) (pad 23 thru_hole oval (at 15.24 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 48 VA1)) + (net 47 VA1)) (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 49 VD1)) + (net 48 VD1)) (pad 24 thru_hole oval (at 15.24 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 50 VA2)) + (net 49 VA2)) (pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 51 VD2)) + (net 50 VD2)) (pad 25 thru_hole oval (at 15.24 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 52 VA3)) + (net 51 VA3)) (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 53 VD3)) + (net 52 VD3)) (pad 26 thru_hole oval (at 15.24 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 54 VA4)) + (net 53 VA4)) (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 55 VD4)) + (net 54 VD4)) (pad 27 thru_hole oval (at 15.24 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 56 GM2)) + (net 55 GM2)) (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 57 VD5)) + (net 56 VD5)) (pad 28 thru_hole oval (at 15.24 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 39 Y)) + (net 38 Y)) (pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 36 "Net-(J3-Pad1)")) + (net 35 "Net-(J3-Pad1)")) (pad 29 thru_hole oval (at 15.24 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 58 GM1)) + (net 57 GM1)) (pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 37 "Net-(J3-Pad2)")) + (net 36 "Net-(J3-Pad2)")) (pad 30 thru_hole oval (at 15.24 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 59 GM0)) + (net 58 GM0)) (pad 11 thru_hole oval (at 0 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 38 "Net-(J3-Pad3)")) + (net 37 "Net-(J3-Pad3)")) (pad 31 thru_hole oval (at 15.24 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 12 thru_hole oval (at 0 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu 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${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-40_W15.24mm_Socket.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1634,59 +1591,59 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 71 VA14)) + (net 70 VA14)) (pad 15 thru_hole oval (at 15.24 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 53 VD3)) + (net 52 VD3)) (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 44 VA12)) + (net 43 VA12)) (pad 16 thru_hole oval (at 15.24 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 55 VD4)) + (net 54 VD4)) (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 64 VA7)) + (net 63 VA7)) (pad 17 thru_hole oval (at 15.24 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 57 VD5)) + (net 56 VD5)) (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 62 VA6)) + (net 61 VA6)) (pad 18 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13 thru_hole oval (at 0 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 51 VD2)) + (net 50 VD2)) (pad 27 thru_hole oval (at 15.24 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 73 RAM_RW)) + (net 72 RAM_RW)) (pad 14 thru_hole oval (at 0 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 28 thru_hole oval (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-28_W15.24mm_Socket.wrl @@ -1736,32 +1693,32 @@ (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 5 A12)) (pad 9 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 85 "Net-(J2-Pad13)")) + (net 84 "Net-(J2-Pad13)")) (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 4 A13)) (pad 10 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 84 "Net-(J2-Pad11)")) + (net 83 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"Net-(J2-Pad3)")) (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 15 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 30 "Net-(J2-Pad1)")) + (net 29 "Net-(J2-Pad1)")) (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 16 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-16_W7.62mm_Socket.wrl @@ -1801,17 +1758,17 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 36 "Net-(J3-Pad1)")) + (net 35 "Net-(J3-Pad1)")) (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 37 "Net-(J3-Pad2)")) + (net 36 "Net-(J3-Pad2)")) (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 38 "Net-(J3-Pad3)")) + (net 37 "Net-(J3-Pad3)")) (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 39 Y)) + (net 38 Y)) (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 40 VDU_CLK)) + (net 39 VDU_CLK)) (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (net 1 VCC)) (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x07_Pitch2.54mm.wrl @@ -1852,7 +1809,7 @@ (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1898,28 +1855,28 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 8 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 9 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 10 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 11 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 73 RAM_RW)) + (net 72 RAM_RW)) (pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 12 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 74 ~CS_RAM_EXT)) + (net 73 ~CS_RAM_EXT)) (pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 13 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 21 R/~W)) + (net 20 R/~W)) (pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 14 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-14_W7.62mm_Socket.wrl @@ -1972,28 +1929,28 @@ (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 6 A11)) (pad 10 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 79 "Net-(U10-Pad6)")) + (net 78 "Net-(U10-Pad6)")) (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 21 R/~W)) + (net 20 R/~W)) (pad 11 thru_hole oval (at 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*.Cu *.Mask) - (net 75 "Net-(U10-Pad2)")) + (net 74 "Net-(U10-Pad2)")) (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 16 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-16_W7.62mm_Socket.wrl @@ -2041,30 +1998,30 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 76 "Net-(U10-Pad1)")) + (net 75 "Net-(U10-Pad1)")) (pad 8 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 76 "Net-(U10-Pad1)")) + (net 75 "Net-(U10-Pad1)")) (pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 75 "Net-(U10-Pad2)")) + (net 74 "Net-(U10-Pad2)")) (pad 9 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 83 "Net-(U10-Pad4)")) + (net 82 "Net-(U10-Pad4)")) (pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 82 "Net-(U10-Pad3)")) + (net 81 "Net-(U10-Pad3)")) (pad 10 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 74 ~CS_RAM_EXT)) + (net 73 ~CS_RAM_EXT)) (pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 83 "Net-(U10-Pad4)")) + (net 82 "Net-(U10-Pad4)")) (pad 11 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 80 "Net-(U10-Pad5)")) + (net 79 "Net-(U10-Pad5)")) (pad 12 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 79 "Net-(U10-Pad6)")) + (net 78 "Net-(U10-Pad6)")) (pad 13 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 14 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-14_W7.62mm_Socket.wrl @@ -2104,37 +2061,37 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 74 ~CS_RAM_EXT)) + (net 73 ~CS_RAM_EXT)) (pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 81 ~REG1)) + (net 80 ~REG1)) (pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 70 VA11)) + (net 69 VA11)) (pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 6 A11)) (pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 5 A12)) (pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 44 VA12)) + (net 43 VA12)) (pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-20_W7.62mm.wrl @@ -2184,16 +2141,16 @@ (fp_arc (start 17.32 -9.51) (end 17.32 -10.16) (angle 90) (layer F.Fab) (width 0.1)) (fp_arc (start -2.08 -9.51) (end -2.73 -9.51) (angle 90) (layer F.Fab) (width 0.1)) (pad 7 thru_hole circle (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 8 thru_hole circle (at 7.62 -7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 40 VDU_CLK)) + (net 39 VDU_CLK)) (pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 14 thru_hole circle (at 0 -7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (pad 8 thru_hole circle (at 15.24 -7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 40 VDU_CLK)) + (net 39 VDU_CLK)) (pad 7 thru_hole circle (at 15.24 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (model ${KISYS3DMOD}/Oscillators.3dshapes/Oscillator_DIP-14.wrl (at (xyz 0 0 0)) (scale (xyz 0.3937 0.3937 0.3937)) @@ -2260,16 +2217,16 @@ (pad 1 thru_hole circle (at -19.05 -3.81) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) (net 1 VCC)) (pad 2 thru_hole circle (at -19.05 -1.27) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) - (net 39 Y)) + (net 38 Y)) (pad 4 thru_hole circle (at -19.05 1.27) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)) (pad 6 thru_hole circle (at -19.05 3.81) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 3 thru_hole circle (at 15.24 -3.81) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) - (net 41 "Net-(J8-Pad2)")) + (net 40 "Net-(J8-Pad2)")) (pad 6 thru_hole circle (at 15.24 -1.27) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 6 thru_hole circle (at 15.24 1.27) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 5 thru_hole circle (at 15.24 3.81) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)) ) @@ -2305,33 +2262,33 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 30 "Net-(J2-Pad1)")) + (net 29 "Net-(J2-Pad1)")) (pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 31 VDU_BASE)) + (net 30 VDU_BASE)) (pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 32 "Net-(J2-Pad3)")) + (net 31 "Net-(J2-Pad3)")) (pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 31 VDU_BASE)) + (net 30 VDU_BASE)) (pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 33 "Net-(J2-Pad5)")) + (net 32 "Net-(J2-Pad5)")) (pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 31 VDU_BASE)) + (net 30 VDU_BASE)) (pad 7 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 34 "Net-(J2-Pad7)")) + (net 33 "Net-(J2-Pad7)")) (pad 8 thru_hole oval (at 2.54 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 31 VDU_BASE)) + (net 30 VDU_BASE)) (pad 9 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 35 "Net-(J2-Pad9)")) + (net 34 "Net-(J2-Pad9)")) (pad 10 thru_hole oval (at 2.54 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 31 VDU_BASE)) + (net 30 VDU_BASE)) (pad 11 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 84 "Net-(J2-Pad11)")) + (net 83 "Net-(J2-Pad11)")) (pad 12 thru_hole oval (at 2.54 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 31 VDU_BASE)) + (net 30 VDU_BASE)) (pad 13 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 85 "Net-(J2-Pad13)")) + (net 84 "Net-(J2-Pad13)")) (pad 14 thru_hole oval (at 2.54 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 31 VDU_BASE)) + (net 30 VDU_BASE)) (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_2x07_Pitch2.54mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -2377,38 +2334,38 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 74 ~CS_RAM_EXT)) + (net 73 ~CS_RAM_EXT)) (pad 11 thru_hole oval (at 7.62 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 9 A8)) (pad 12 thru_hole oval (at 7.62 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 13 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 8 A9)) (pad 14 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 68 VA10)) + (net 67 VA10)) (pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 15 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 7 A10)) (pad 16 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 67 VA9)) + (net 66 VA9)) (pad 7 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thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 11 A6)) (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 15 A2)) (pad 16 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 48 VA1)) + (net 47 VA1)) (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 61 VA5)) + (net 60 VA5)) (pad 17 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 10 A7)) (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 14 A3)) (pad 18 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 46 VA0)) + (net 45 VA0)) (pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 54 VA4)) + (net 53 VA4)) (pad 19 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 74 ~CS_RAM_EXT)) + (net 73 ~CS_RAM_EXT)) (pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 77 GND)) + (net 76 GND)) (pad 20 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (net 1 VCC)) (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-20_W7.62mm_Socket.wrl @@ -2540,43 +2497,43 @@ (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 21 R/~W)) + (net 20 R/~W)) (pad 11 thru_hole oval (at 7.62 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 22 D0)) + (net 21 D0)) (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 60 VD7)) + (net 59 VD7)) (pad 12 thru_hole oval (at 7.62 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 23 D1)) + (net 22 D1)) (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - (net 45 VD6)) + (net 44 VD6)) (pad 13 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) - 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(xy 60.795 49.23869) (xy 60.2847 49.23869) + (xy 60.285543 48.274146) (xy 59.809273 47.121485) (xy 58.928153 46.238826) (xy 57.979714 45.845) (xy 103.58429 45.845) ) ) ) diff --git a/RC6502 VDU/RC6502 VDU.net b/RC6502 VDU/RC6502 VDU.net index d720f7c..5dfdb5d 100644 --- a/RC6502 VDU/RC6502 VDU.net +++ b/RC6502 VDU/RC6502 VDU.net @@ -1,7 +1,7 @@ (export (version D) (design (source "D:/ownCloud/Documents/Projects/RC6502/RC6502 VDU/RC6502 VDU.sch") - (date "30/12/2018 11:32:29") + (date "30/12/2018 12:41:03") (tool "Eeschema 4.0.7") (sheet (number 1) (name /) (tstamps /) (title_block @@ -147,12 +147,6 @@ (libsource (lib mc6847) (part MC6847)) (sheetpath (names /) (tstamps /)) (tstamp 5C053F7E)) - (comp (ref JP2) - (value PHI0_OUT) - (footprint Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm) - (libsource (lib device) (part Jumper_NO_Small)) - (sheetpath (names /) (tstamps /)) - (tstamp 5C05E5BB)) (comp (ref JP1) (value VDU_EN) (footprint Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm) @@ -635,20 +629,20 @@ (pin (num 5) (name AUD_OUT) (type power_out)) (pin (num 6) (name GND) (type power_in))))) (libraries - (library (logical conn) - (uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\conn.lib")) - (library (logical rc6502_backplane) - (uri D:\ownCloud\Documents\Projects\RC6502\Templates\rc6502_backplane.lib)) - (library (logical oscillator) - (uri D:\ownCloud\Documents\Projects\RC6502\Templates\oscillator.lib)) - (library (logical mounting) - (uri D:\ownCloud\Documents\Projects\RC6502\Templates\mounting.lib)) - (library (logical mc6847) - (uri D:\ownCloud\Documents\Projects\RC6502\Templates\mc6847.lib)) - (library (logical rca_plug) - (uri D:\ownCloud\Documents\Projects\RC6502\Templates\rca_plug.lib)) (library (logical vdu_port) (uri "D:\\ownCloud\\Documents\\Projects\\RC6502\\RC6502 VDU\\vdu_port.lib")) + (library (logical rca_plug) + (uri D:\ownCloud\Documents\Projects\RC6502\Templates\rca_plug.lib)) + (library (logical mounting) + (uri D:\ownCloud\Documents\Projects\RC6502\Templates\mounting.lib)) + (library (logical oscillator) + (uri D:\ownCloud\Documents\Projects\RC6502\Templates\oscillator.lib)) + (library (logical mc6847) + (uri D:\ownCloud\Documents\Projects\RC6502\Templates\mc6847.lib)) + (library (logical rc6502_backplane) + (uri D:\ownCloud\Documents\Projects\RC6502\Templates\rc6502_backplane.lib)) + (library (logical conn) + (uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\conn.lib")) (library (logical device) (uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\device.lib")) (library (logical 74xx) @@ -656,456 +650,454 @@ (library (logical memory) (uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\memory.lib"))) (nets - (net (code 1) (name "Net-(J1-Pad20)") - (node (ref J1) (pin 20))) - (net (code 2) (name ~CS_RAM_EXT) - (node (ref U10) (pin 10)) - (node (ref U5) (pin 19)) - (node (ref U8) (pin 12)) - (node (ref U4) (pin 1)) - (node (ref U3) (pin 19)) - (node (ref U4) (pin 19)) - (node (ref U3) (pin 1)) - (node (ref U12) (pin 1))) - (net (code 3) (name RAM_RW) + (net (code 1) (name RAM_RW) (node (ref U8) (pin 11)) (node (ref U2) (pin 27))) - (net (code 4) (name GND) - (node (ref U12) (pin 13)) - (node (ref U12) (pin 17)) - (node (ref U12) (pin 8)) - (node (ref U12) (pin 18)) - (node (ref U8) (pin 5)) - (node (ref U8) (pin 4)) - (node (ref U3) (pin 13)) - (node (ref U9) (pin 8)) - (node (ref U3) (pin 15)) - (node (ref U12) (pin 10)) - (node (ref U12) (pin 7)) + (net (code 2) (name "Net-(J1-Pad20)") + (node (ref J1) (pin 20))) + (net (code 3) (name "Net-(U3-Pad3)") + (node (ref U3) (pin 3))) + (net (code 4) (name GM2) + (node (ref U6) (pin 12)) + (node (ref U1) (pin 27))) + (net (code 5) (name GND) + (node (ref U3) (pin 17)) + (node (ref U7) (pin 8)) + (node (ref U3) (pin 11)) + (node (ref U2) (pin 14)) + (node (ref C12) (pin 2)) + (node (ref U2) (pin 22)) + (node (ref U7) (pin 5)) (node (ref U8) (pin 10)) (node (ref U8) (pin 9)) - (node (ref U8) (pin 7)) - (node (ref U10) (pin 12)) - (node (ref U8) (pin 2)) - (node (ref U8) (pin 1)) - (node (ref U10) (pin 11)) - (node (ref U3) (pin 17)) - (node (ref U12) (pin 14)) - (node (ref C12) (pin 2)) - (node (ref U2) (pin 14)) - (node (ref U7) (pin 8)) - (node (ref U7) (pin 5)) (node (ref U7) (pin 4)) - (node (ref U6) (pin 10)) (node (ref C6) (pin 2)) - (node (ref C1) (pin 2)) - (node (ref C2) (pin 2)) - (node (ref C3) (pin 2)) - (node (ref C5) (pin 2)) - (node (ref C7) (pin 2)) - (node (ref X1) (pin 7)) (node (ref C4) (pin 2)) - (node (ref U10) (pin 7)) - (node (ref U1) (pin 31)) - (node (ref U2) (pin 22)) - (node (ref U2) (pin 20)) + (node (ref X1) (pin 7)) + (node (ref C7) (pin 2)) + (node (ref U3) (pin 15)) + (node (ref U10) (pin 12)) + (node (ref C5) (pin 2)) + (node (ref C3) (pin 2)) + (node (ref C2) (pin 2)) + (node (ref C1) (pin 2)) (node (ref U6) (pin 1)) - (node (ref U4) (pin 10)) - (node (ref U1) (pin 1)) - (node (ref U5) (pin 10)) - (node (ref C8) (pin 2)) + (node (ref U10) (pin 11)) + (node (ref U8) (pin 7)) + (node (ref U3) (pin 13)) (node (ref J1) (pin 17)) - (node (ref U3) (pin 10)) - (node (ref U3) (pin 8)) (node (ref U9) (pin 4)) - (node (ref U3) (pin 11)) + (node (ref U9) (pin 8)) + (node (ref U3) (pin 10)) + (node (ref U10) (pin 7)) + (node (ref U12) (pin 8)) + (node (ref U12) (pin 7)) + (node (ref C8) (pin 2)) + (node (ref U12) (pin 10)) + (node (ref U12) (pin 17)) + (node (ref U12) (pin 14)) + (node (ref U12) (pin 13)) + (node (ref U8) (pin 5)) + (node (ref U8) (pin 4)) + (node (ref U12) (pin 18)) + (node (ref U8) (pin 1)) + (node (ref U5) (pin 10)) + (node (ref U3) (pin 8)) + (node (ref U8) (pin 2)) + (node (ref U2) (pin 20)) + (node (ref U4) (pin 10)) (node (ref J3) (pin 6)) + (node (ref J8) (pin 1)) (node (ref C10) (pin 2)) (node (ref U11) (pin 6)) (node (ref C9) (pin 2)) - (node (ref J8) (pin 1))) - (net (code 5) (name GM0) - (node (ref U6) (pin 16)) - (node (ref U1) (pin 30))) - (net (code 6) (name GM1) - (node (ref U6) (pin 15)) - (node (ref U1) (pin 29))) - (net (code 7) (name GM2) - (node (ref U6) (pin 12)) - (node (ref U1) (pin 27))) - (net (code 8) (name "Net-(U3-Pad3)") - (node (ref U3) (pin 3))) - (net (code 9) (name VCC) - (node (ref J1) (pin 18)) + (node (ref U6) (pin 10)) + (node (ref U1) (pin 1)) + (node (ref U1) (pin 31))) + (net (code 6) (name VCC) + (node (ref U6) (pin 20)) + (node (ref U7) (pin 16)) (node (ref U1) (pin 17)) - (node (ref C8) (pin 1)) - (node (ref U4) (pin 20)) - (node (ref U12) (pin 20)) - (node (ref U9) (pin 16)) - (node (ref J3) (pin 7)) - (node (ref U8) (pin 14)) + (node (ref U2) (pin 28)) (node (ref C12) (pin 1)) - (node (ref U3) (pin 20)) + (node (ref J1) (pin 18)) + (node (ref U8) (pin 14)) (node (ref U11) (pin 1)) + (node (ref J3) (pin 7)) (node (ref U5) (pin 20)) - (node (ref U10) (pin 14)) - (node (ref X1) (pin 14)) + (node (ref U4) (pin 20)) (node (ref C7) (pin 1)) (node (ref C6) (pin 1)) (node (ref C5) (pin 1)) (node (ref C4) (pin 1)) (node (ref C3) (pin 1)) (node (ref C2) (pin 1)) - (node (ref C10) (pin 1)) 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"Net-(J2-Pad9)") + (node (ref J2) (pin 9)) + (node (ref U7) (pin 11))) + (net (code 121) (name ~CS_RAM_EXT) + (node (ref U5) (pin 19)) + (node (ref U10) (pin 10)) + (node (ref U3) (pin 19)) + (node (ref U4) (pin 1)) + (node (ref U4) (pin 19)) + (node (ref U12) (pin 1)) + (node (ref U3) (pin 1)) + (node (ref U8) (pin 12))))) \ No newline at end of file diff --git a/RC6502 VDU/RC6502 VDU.pro b/RC6502 VDU/RC6502 VDU.pro index 3e2a3e5..c8a6dcf 100644 --- a/RC6502 VDU/RC6502 VDU.pro +++ b/RC6502 VDU/RC6502 VDU.pro @@ -1,4 +1,4 @@ -update=13/12/2018 15:24:21 +update=30/12/2018 21:08:07 version=1 last_client=kicad [pcbnew] @@ -23,8 +23,6 @@ ModuleOutlineThickness=0.150000000000 [cvpcb] version=1 NetIExt=net -[general] -version=1 [eeschema] version=1 LibDir= @@ -67,3 +65,5 @@ LibName35=D:/ownCloud/Documents/Projects/RC6502/Templates/oscillator LibName36=D:/ownCloud/Documents/Projects/RC6502/Templates/mc6847 LibName37=D:/ownCloud/Documents/Projects/RC6502/Templates/rca_plug LibName38=vdu_port +[general] +version=1 diff --git a/RC6502 VDU/RC6502 VDU.sch b/RC6502 VDU/RC6502 VDU.sch index 0a8b8a1..fdc7151 100644 --- a/RC6502 VDU/RC6502 VDU.sch +++ b/RC6502 VDU/RC6502 VDU.sch @@ -554,8 +554,6 @@ Text GLabel 3300 725 2 60 Output ~ 0 VDU_BASE Text GLabel 3150 2475 2 60 Output ~ 0 VDU_CLK -Wire Wire Line - 3000 2475 3150 2475 $Comp L GND #PWR02 U 1 1 5C0463DB @@ -890,28 +888,6 @@ Wire Wire Line 7500 6350 7650 6350 Wire Wire Line 7500 6450 7650 6450 -Text GLabel 10400 4450 0 60 Input ~ 0 -PHI0 -$Comp -L Jumper_NO_Small JP2 -U 1 1 5C05E5BB -P 3275 2250 -F 0 "JP2" H 3275 2330 50 0000 C CNN -F 1 "PHI0_OUT" H 3285 2190 50 0000 C CNN -F 2 "Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm" H 3275 2250 50 0001 C CNN -F 3 "" H 3275 2250 50 0001 C CNN - 1 3275 2250 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3075 2475 3075 2250 -Connection ~ 3075 2475 -Wire Wire Line - 3075 2250 3175 2250 -Text GLabel 3475 2250 2 60 Output ~ 0 -PHI0 -Wire Wire Line - 3375 2250 3475 2250 $Comp L GND #PWR08 U 1 1 5C0636E6 @@ -1610,4 +1586,7 @@ Connection ~ 2975 1125 Wire Wire Line 2975 1325 2900 1325 Connection ~ 2975 1225 +Wire Wire Line + 3000 2475 3150 2475 +NoConn ~ 10400 4450 $EndSCHEMATC