Apple-1-HW/RC6502-Apple-1-Replica
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VDU silkscreen tweaks

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This commit is contained in:
Unknown 2019-02-27 22:28:04 +01:00
parent cb1c2e9956
commit 575d37122d
2 changed files with 14 additions and 6 deletions
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18
RC6502 VDU/RC6502 VDU.kicad_pcb
View File

@ -5,7 +5,7 @@
(no_connects 0)
(area 52.629999 44.374999 151.840001 144.220001)
(thickness 1.6)
(drawings 97)
(drawings 103)
(tracks 1993)
(zones 0)
(modules 37)
@ -1310,7 +1310,7 @@
(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.2) (layers *.Cu *.Mask))
)
(module rca:rca_yellow (layer F.Cu) (tedit 5C6D4287) (tstamp 5C06E6B7)
(module rca:rca_yellow (layer F.Cu) (tedit 5C7700C6) (tstamp 5C06E6B7)
(at 149.86 57.785 90)
(descr "RCA Audio connector, yellow, Pro Signal p/n PSG01547")
(tags "rca, audio")
@ -1318,7 +1318,7 @@
(fp_text reference J8 (at 0 15.7988 90) (layer F.SilkS)
(effects (font (thickness 0.3048)))
)
(fp_text value RCA_PLUG (at 0 -8.89 90) (layer F.Fab)
(fp_text value RCA_PLUG (at 6.35 8.255 180) (layer F.Fab)
(effects (font (thickness 0.3048)))
)
(fp_circle (center -3.2512 -5.79882) (end -3.79984 -5.79882) (layer F.SilkS) (width 0.381))
@ -1357,12 +1357,12 @@
)
)
(module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 5C06EFCE) (tstamp 5C06E6BD)
(module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 5C77000D) (tstamp 5C06E6BD)
(at 146.05 67.31 90)
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x02 2.54mm single row")
(path /5C086A5B)
(fp_text reference JP1 (at 0 -2.54 270) (layer F.SilkS)
(fp_text reference JP1 (at 0 -2.54 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VDU_EN (at 2.54 1.27 180) (layer F.SilkS)
@ -2765,6 +2765,14 @@
)
)
(gr_text VDU_EN (at 147.32 64.77) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_line (start 146.05 67.31) (end 148.59 67.31) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 144.145 69.215) (end 144.145 65.405) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 150.495 69.215) (end 144.145 69.215) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 150.495 65.405) (end 150.495 69.215) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 144.145 65.405) (end 150.495 65.405) (angle 90) (layer B.SilkS) (width 0.2))
(gr_line (start 52.705 48.895) (end 52.705 144.145) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 151.765 48.895) (end 151.765 144.145) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 147.32 44.45) (end 57.15 44.45) (angle 90) (layer Edge.Cuts) (width 0.15))

2
RC6502 VDU/RC6502 VDU.pro
View File

@ -1,4 +1,4 @@
update=30/12/2018 21:16:23
update=27/02/2019 22:27:46
version=1
last_client=kicad
[pcbnew]