additional mapping starting at C600
This commit is contained in:
flowenol
Piotr Jaczewski
parent
21cddcb618
commit
146e94aa6a
11
Makefile
11
Makefile
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@ -14,8 +14,11 @@ apple1serial-C000.bin:
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apple1serial-C300.bin:
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xa -DOFFSET="768" -W -C -v -O ASCII -c src/apple1serial.a65 -l apple1serial-C300.label -o apple1serial-C300.bin
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apple1serial-C600.bin:
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xa -DOFFSET="1536" -W -C -v -O ASCII -c src/apple1serial.a65 -l apple1serial-C600.label -o apple1serial-C600.bin
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all: apple1serial-C000.bin apple1serial-C300.bin
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all: apple1serial-C000.bin apple1serial-C300.bin apple1serial-C600.bin
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clean:
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rm -f apple1serial*.bin apple1serial*.label
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@ -31,3 +34,9 @@ burn-C300-gal:
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burn-C300-rom: apple1serial-C300.bin
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minipro -s -p 28C64B -w apple1serial-C300.bin
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burn-C600-gal:
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minipro -p GAL20V8B -w mapping/address_decoder-C600.jed
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burn-C600-rom: apple1serial-C600.bin
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minipro -s -p 28C64B -w apple1serial-C600.bin
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26
README.md
26
README.md
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@ -62,21 +62,37 @@ The contents of this repository are as following:
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There are two .jed files for the GAL20V8 based address decoder:
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1. **address_decoder-C000.jed** - defines the standard mapping where the device mimics the original ACI loader program at `$C100`.
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2. **address_decoder-C300.jed** - defines an alternative mapping allowing tu run Apple-1 Serial Interface together with the original ACI within the same system.
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2. **address_decoder-C300.jed** - defines an alternative mapping to run Apple-1 Serial Interface together with the original ACI within the same system.
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All program and hardware entries are shifted by offset `$300`, so the loader program can be accessed at `$C400`.
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2. **address_decoder-C600.jed** - defines an alternative mapping to run Apple-1 Serial Interface together with both the original and Improved ACI 2.0 (by Uncle Bernie) within the same system.
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All program and hardware entries are shifted by offset `$600`, so the loader program can be accessed at `$C700`.
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Please be sure to program the ROM with the bin image corresponding to the selected mapping.
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You can use the convenient `make` targets to burn ROM and GAL, if you have the `minipro` utility installed:
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```bash
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make burn-C000-gal
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make burn-C000-rom
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make burn-C300-gal
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make burn-C300-rom
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make burn-C600-gal
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make burn-C600-rom
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```
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## Requirements
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You need the following to successfully build the firmware:
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* [xa](https://www.floodgap.com/retrotech/xa/) cross assembler
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* [avr-gcc](https://gcc.gnu.org/wiki/avr-gcc) toolchain
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* [avr-libc](https://www.nongnu.org/avr-libc/) set of libraries
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* [AVRDUDE](https://www.nongnu.org/avrdude/) AVR programmer software or equivalent to program the ATMega328P MCU
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* [xa](https://www.floodgap.com/retrotech/xa/) cross assembler.
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* [avr-gcc](https://gcc.gnu.org/wiki/avr-gcc) toolchain.
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* [avr-libc](https://www.nongnu.org/avr-libc/) set of libraries.
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* [AVRDUDE](https://www.nongnu.org/avrdude/) AVR programmer software or equivalent to program the ATMega328P MCU.
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* Software capable of translating the .eqn files into .jed's. I used for this purpose the DOS based EQN2JED from OPALjr PLD Development Package. This is only required if you wish to make some changes to the GAL based address decoder. The default .jed file should be fine for most users.
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* EEPROM programmer to write ROM and GAL. I used [TL866](http://autoelectric.cn/EN/TL866_main.html) programmer for this purpose. It can also program the ATMega328P MCU.
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* You can use the [minipro](https://gitlab.com/DavidGriffith/minipro/) utility to write ROM, GAL and MCU.
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## How to build?
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@ -0,0 +1,15 @@
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chip GAL20V8
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NC3=1 RW=2 A0=11 A1=10 A2=9 A3=8 A4=7 A5=6 A6=5 A7=4 A8=3 GND=12
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A9=16 A10=15 A11=14 SR=17 RD=18 WD=19 ROM=20 RES=21 PHI=22
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T=23 VCC=24
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equations
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SR = /A0 * /A1 * /A2 * /A3 * /A4 * /A5 * /A6 * /A7 * /A8 * A9 * A10 * /A11 * /T * RW
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RD = /A0 * /A1 * /A2 * /A3 * /A4 * /A5 * /A6 * A7 * /A8 * A9 * A10 * /A11 * /T * RW
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WD = A0 * /A1 * /A2 * /A3 * /A4 * /A5 * /A6 * A7 * /A8 * A9 * A10 * /A11 * /T * /RW * PHI
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/ROM = A11 * /T * RW
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+ /A11 * A10 * A9 * A8 * /T * RW
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+ A2 * A3 * A4 * A5 * A6 * A7 * /A8 * A9 * A10 * /A11 * /T * RW
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RES = A0 * /A1 * /A2 * /A3 * /A4 * /A5 * /A6 * /A7 * /A8 * A9 * A10 * /A11 * /T * RW
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@ -0,0 +1,33 @@
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GAL20V8
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V101)
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Copyright (c) National Semiconductor Corporation 1990-1993
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Assembled from "d:\ADDRES~2.EQN". Date: 3-29-123
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*
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NOTE PINS RW:2 A8:3 A7:4 A6:5 A5:6 A4:7 A3:8 A2:9 A1:10 A0:11*
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NOTE PINS GND:12 A11:14 A10:15 A9:16 SR:17 RD:18 WD:19 ROM:20*
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NOTE PINS RES:21 PHI:22 T:23 VCC:24*
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NOTE GALMODE SMALL*
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QF2706*QP24*F0*
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L0320
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0111101010111011101110111001100110100111*
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L0640
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0111111011111111111111111111111111011111
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0111011011111111111111111101110111101111
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0111101001110111011101110101010111101111*
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L0960
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1011101001011011101110111001100110100111*
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L1280
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0111101001111011101110111001100110101011*
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L1600
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0111101010111011101110111001100110101011*
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L2560
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01011100*
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L2632
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10000011*
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L2640
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0000000010000000111000001000000010000000100000000000000000000000*
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L2704
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10*
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C1BAB*
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0000
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@ -0,0 +1,73 @@
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V101)
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Copyright (c) National Semiconductor Corporation 1990-1993
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Log file for d:\ADDRES~2.EQN
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Device: 20V8
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Pin Label Type
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--- ----- ----
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2 RW pos,com input
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3 A8 pos,com input
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4 A7 pos,com input
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5 A6 pos,com input
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6 A5 pos,com input
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7 A4 pos,com input
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8 A3 pos,com input
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9 A2 pos,com input
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10 A1 pos,com input
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11 A0 pos,com input
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12 GND ground pin
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14 A11 pos,com input
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15 A10 pos,com input
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16 A9 pos,com input
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17 SR pos,com output
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18 RD pos,com output
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19 WD pos,com output
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20 ROM neg,com output
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21 RES pos,com output
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22 PHI pos,com input
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23 T pos,com input
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24 VCC power pin
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V101)
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Copyright (c) National Semiconductor Corporation 1990-1993
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Device Utilization:
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No of dedicated inputs used : 14/14 (100.0%)
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No of feedbacks used as dedicated inputs : 1/6 (16.7%)
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No of dedicated outputs used : 2/2 (100.0%)
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No of feedbacks used as dedicated outputs : 3/6 (50.0%)
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------------------------------------------
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Pin Label Terms Usage
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------------------------------------------
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21 RES 1/8 (12.5%)
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20 ROM 3/8 (37.5%)
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19 WD 1/8 (12.5%)
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18 RD 1/8 (12.5%)
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17 SR 1/8 (12.5%)
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------------------------------------------
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Total Terms 7/64 (10.9%)
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------------------------------------------
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V101)
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Copyright (c) National Semiconductor Corporation 1990-1993
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Chip diagram (DIP)
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._____ _____.
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| \__/ |
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| 1 24 | VCC
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RW | 2 23 | T
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A8 | 3 22 | PHI
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A7 | 4 21 | RES
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A6 | 5 20 | ROM
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A5 | 6 19 | WD
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A4 | 7 18 | RD
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A3 | 8 17 | SR
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A2 | 9 16 | A9
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A1 | 10 15 | A10
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A0 | 11 14 | A11
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GND | 12 13 |
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|______________|
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