[Project]
ProjectVersion=2.0
Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Build Date: Sep 11 2017 17:40:01
ProjectName=icecube2
Vendor=SiliconBlue
Synthesis=synplify
ProjectVFiles=../../../../rtl/apple1.v,../../../../rtl/clock.v,../../../../rtl/pwr_reset.v,../../../../rtl/ram.v,../../../../rtl/rom_basic.v,../../../../rtl/rom_wozmon.v,../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v,../../../../rtl/boards/tinyfpga_bx/clock_pll.v,../../../../rtl/cpu/arlet_6502.v,../../../../rtl/cpu/arlet/ALU.v,../../../../rtl/cpu/arlet/cpu.v,../../../../rtl/ps2keyboard/debounce.v,../../../../rtl/ps2keyboard/ps2keyboard.v,../../../../rtl/uart/async_tx_rx.v,../../../../rtl/uart/uart.v,../../../../rtl/vga/font_rom.v,../../../../rtl/vga/vga.v,../../../../rtl/vga/vram.v
ProjectCFiles=
CurImplementation=icecube2_Implmnt
Implementations=icecube2_Implmnt
StartFromSynthesis=yes
IPGeneration=false

[icecube2_Implmnt]
DeviceFamily=iCE40
Device=LP8K
DevicePackage=CM81
DevicePower=
NetlistFile=icecube2_Implmnt/icecube2.edf
AdditionalEDIFFile=
IPEDIFFile=
DesignLib=icecube2_Implmnt/sbt/netlist/oadb-apple1_top
DesignView=_rt
DesignCell=apple1_top
SynthesisSDCFile=icecube2_Implmnt/icecube2.scf
UserPinConstraintFile=
UserSDCFile=
PhysicalConstraintFile=../tinyfpga_bx.pcf
BackendImplPathName=
Devicevoltage=1.14
DevicevoltagePerformance=+/-5%(datasheet default)
DeviceTemperature=85
TimingAnalysisBasedOn=Worst
OperationRange=Commercial
TypicalCustomTemperature=25
WorstCustomTemperature=85
BestCustomTemperature=0
IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3
derValue=1.03369
TimingPathNumberStick=0

[lse options]
CarryChain=True
CarryChainLength=0
CommandLineOptions=
EBRUtilization=100.00
FSMEncodingStyle=Auto
FixGatedClocks=True
I/OInsertion=True
IntermediateFileDump=False
LoopLimit=1950
MaximalFanout=10000
MemoryInitialValueFileSearchPath=
NumberOfCriticalPaths=3
OptimizationGoal=Area
PropagateConstants=True
RAMStyle=Auto
ROMStyle=Auto
RWCheckOnRam=False
RemoveDuplicateRegisters=True
ResolvedMixedDrivers=False
ResourceSharing=True
TargetFrequency=
TopLevelUnit=
UseIORegister=Auto
VHDL2008=False
VerilogIncludeSearchPath=

[tool options]
PlacerEffortLevel=std
PlacerAutoLutCascade=yes
PlacerAutoRamCascade=yes
PlacerPowerDriven=no
PlacerAreaDriven=no
RouteWithTimingDriven=yes
RouteWithPinPermutation=yes
BitmapSPIFlashMode=yes
BitmapRAM4KInit=yes
BitmapInitRamBank=1111
BitmapOscillatorFR=low
BitmapEnableWarmBoot=yes
BitmapDisableHeader=no
BitmapSetSecurity=no
BitmapSetNoUsedIONoPullup=no
FloorPlannerShowFanInNets=yes
FloorPlannerShowFanOutNets=yes
HookTo3rdPartyTextEditor=

