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Updated DE0 top level and Quartus DE0 project to new directory layout
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@ -344,6 +344,10 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
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set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet/cpu.v
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set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet/ALU.v
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set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet_6502.v
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set_global_assignment -name VERILOG_FILE ../../rtl/apple1.v
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set_global_assignment -name SDC_FILE "apple-one.sdc"
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set_global_assignment -name SDC_FILE "apple-one.sdc"
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set_global_assignment -name VERILOG_FILE ../../rtl/boards/terasic_de0/apple1_de0_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/boards/terasic_de0/apple1_de0_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/cpu/cpu.v
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set_global_assignment -name VERILOG_FILE ../../rtl/cpu/cpu.v
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@ -352,5 +356,4 @@ set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart/async_tx_rx.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart/async_tx_rx.v
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set_global_assignment -name VERILOG_FILE ../../rtl/rom_wozmon.v
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set_global_assignment -name VERILOG_FILE ../../rtl/rom_wozmon.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ram.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ram.v
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set_global_assignment -name VERILOG_FILE ../../rtl/apple1_top.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -43,7 +43,7 @@ module apple1_de0_top(
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//////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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// Core of system
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top core_top(
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apple1 apple1_top(
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.clk25(clk25),
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.clk25(clk25),
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.rst_n(1'b1), // we don't have any reset pulse..
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.rst_n(1'b1), // we don't have any reset pulse..
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.uart_rx(UART_RXD),
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.uart_rx(UART_RXD),
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