Added support for ICE40UPDevBoard
My board features an ICE40UP5K in QFN and the usual flash, PS/2 port etc. Thought it would be fun to port this Apple One implementation, and it was super easy considering I'm quite new to Verilog.
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Lawrence Manning
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# TinyFPGA B2 support
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This adds support for building apple one design for [Aslak3's ICE40UP Development Board](http://github.com/aslak3/ICE40UPDevBoard). The board contains a [ADV7123](https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7123-EP.pdf) (PDF) RGB DAC and PS/2 port, and some I2C hardware that this Apple 1 implementation does not yet make use of. The single push button on the board is mapped to the reset line. The PS/2 port on the board is actually wired to two PS/2 connections, but this project makes only use of the first ("default") wiring for the keyboard.
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## Building
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Install a recent toolchain and:
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```
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$ cd yosys
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$ make
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```
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Unlike other boards in this project nextpnr-ice4 is used for routing, since it has been the current tool for some years now and arachne-pnr was deprecated in 2015.
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Program the board using any suitable method.
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Binary file not shown.
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After Width: | Height: | Size: 298 KiB |
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DEVICE = up5k
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PIN_DEF = ice40updevboard.pcf
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SOURCEDIR = ../../../rtl
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BUILDDIR = build
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all: apple1
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info:
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@echo " To build: make apple1"
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@echo "To build report: make report"
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@echo " To clean up: make clean"
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dir:
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mkdir -p $(BUILDDIR)
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# ------ TEMPLATES ------
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$(BUILDDIR)/%.json: $(SOURCEDIR)/%.v
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yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -json $@" $^
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$(BUILDDIR)/%.asc: $(BUILDDIR)/%.json
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nextpnr-ice40 --up5k --package sg48 --pcf $(PIN_DEF) --json $^ --asc $@
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$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
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icepack $^ $@
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%.rpt: $(BUILDDIR)/%.asc
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icetime -d $(DEVICE) -mtr $@ $<
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%_tb.vvp: %_tb.v %.v
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iverilog -o $@ $^
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%_tb.vcd: %_tb.vvp
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vvp -N $< +vcd=$@
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# ------ APPLE 1 ------
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apple1: dir $(BUILDDIR)/apple1.bin
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report: dir apple1.rpt
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$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
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$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.json
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$(BUILDDIR)/apple1.json: $(SOURCEDIR)/apple1.v \
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$(SOURCEDIR)/clock.v \
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$(SOURCEDIR)/pwr_reset.v \
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$(SOURCEDIR)/ram.v \
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$(SOURCEDIR)/rom_wozmon.v \
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$(SOURCEDIR)/rom_basic.v \
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$(SOURCEDIR)/cpu/arlet_6502.v \
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$(SOURCEDIR)/cpu/arlet/ALU.v \
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$(SOURCEDIR)/cpu/arlet/cpu.v \
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$(SOURCEDIR)/uart/uart.v \
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$(SOURCEDIR)/uart/async_tx_rx.v \
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$(SOURCEDIR)/vga/vga.v \
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$(SOURCEDIR)/vga/vram.v \
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$(SOURCEDIR)/vga/font_rom.v \
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$(SOURCEDIR)/ps2keyboard/debounce.v \
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$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
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$(SOURCEDIR)/boards/ice40updevboard/apple1_ice40updevboard.v
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apple1.rpt: $(BUILDDIR)/apple1.asc
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# ------ HELPERS ------
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clean:
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rm -rf build apple1.rpt
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.SECONDARY:
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.PHONY: all info clean
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### UART - This is the first 3 userheader pins, USER0 through 2 on the board
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set_io uart_rx 45
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set_io uart_tx 46
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set_io uart_cts 47
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### LEDs
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set_io led[0] 38
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set_io led[1] 39
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set_io led[2] 40
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set_io vga_h_sync 9
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set_io vga_v_sync 10
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set_io vga_clk 11 # DAC clock
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set_io vga_blank_n 20 # Blanking pin
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set_io vga_r[3] 27
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set_io vga_r[2] 28
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set_io vga_r[1] 31
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set_io vga_r[0] 32
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set_io vga_g[3] 21
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set_io vga_g[2] 23
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set_io vga_g[1] 25
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set_io vga_g[0] 26
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set_io vga_b[3] 12
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set_io vga_b[2] 13
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set_io vga_b[1] 18
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set_io vga_b[0] 19
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set_io clk 44
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set_io ps2_din 36
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set_io ps2_clk 37
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set_io button 41
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple 1 implementation for the Blackeice II ICE40HX8K +
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//
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// Author.....: Lawrence Manning
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// Date.......: 18-04-2024 (inspired by blackice2/apple1_hx8k.v)
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//
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module apple1_top #(
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parameter BASIC_FILENAME = "../../../roms/basic.hex",
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parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
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parameter RAM_FILENAME = "../../../roms/ram.hex",
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parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
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parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
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) (
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input clk, // 50 MHz board clock
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// I/O interface to computer
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input uart_rx, // asynchronous serial data input from computer
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output uart_tx, // asynchronous serial data output to computer
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output uart_cts, // clear to send flag to computer - not used
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// I/O interface to keyboard
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input ps2_clk, // PS/2 keyboard serial clock input
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input ps2_din, // PS/2 keyboard serial data input
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// Outputs to VGA display
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output vga_h_sync, // hozizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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// Outputs to the ADV7123 RGB DAC IC
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output vga_clk,
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output vga_blank_n,
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output [3:0] vga_r, // red VGA signal
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output [3:0] vga_g, // green VGA signal
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output [3:0] vga_b, // blue VGA signal
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// Debugging ports
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output [2:0] led,
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input button, // 1 button on board
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);
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assign vga_clk = clk25;
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assign vga_blank_n = 1;
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// Active low
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assign led[0] = reset_n;
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assign led[1] = 1;
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assign led[2] = 1;
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// ===============================================================
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// System Clock generation (25MHz)
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// ===============================================================
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reg clk25 = 1;
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// generate 25MHz clock from 50MHz master clock
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always @(posedge clk)
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begin
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clk25 <= ~clk25;
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end
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wire vga_bit;
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// set the monochrome base colour here..
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assign vga_r[3:0] = vga_bit ? 4'b1000 : 4'b0000;
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assign vga_g[3:0] = vga_bit ? 4'b1111 : 4'b0000;
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assign vga_b[3:0] = vga_bit ? 4'b1000 : 4'b0000;
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// debounce reset button
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wire reset_n;
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debounce reset_button (
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.clk25(clk25),
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.rst(1'b0),
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.sig_in(button),
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.sig_out(reset_n)
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);
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// apple one main system
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apple1 #(
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.BASIC_FILENAME (BASIC_FILENAME),
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.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
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.RAM_FILENAME (RAM_FILENAME),
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.VRAM_FILENAME (VRAM_FILENAME),
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.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
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) my_apple1(
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.clk25(clk25),
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.rst_n(reset_n),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts),
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.ps2_clk(ps2_clk),
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.ps2_din(ps2_din),
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.ps2_select(1'b1), // PS/2 enabled, UART TX disabled
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// .ps2_select(1'b0), // PS/2 disabled, UART TX enabled
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_bit),
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.vga_cls(~reset_n),
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);
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endmodule
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