moved some files around to clean things up a bit

apple1_sbt.project

@@ -4,7 +4,7 @@ Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Bui
 ProjectName=apple1
 Vendor=SiliconBlue
 Synthesis=synplify
-ProjectVFiles=rtl/MUX.v,rtl/basic.v,rtl/chip_6502.v,rtl/led_and_key.v,rtl/tm1638.v,rtl/uart.v
+ProjectVFiles=rtl/apple1_top.v,rtl/chip_6502.v,rtl/chip_6502_mux.v,rtl/led_and_key.v,rtl/tm1638.v,rtl/uart.v
 ProjectCFiles=
 CurImplementation=apple1_Implmnt
 Implementations=apple1_Implmnt

apple1_syn.prj

@@ -8,9 +8,9 @@
 
 
 
-add_file -verilog -lib work "rtl/MUX.v" 
-add_file -verilog -lib work "rtl/basic.v" 
+add_file -verilog -lib work "rtl/apple1_top.v" 
 add_file -verilog -lib work "rtl/chip_6502.v" 
+add_file -verilog -lib work "rtl/chip_6502_mux.v" 
 add_file -verilog -lib work "rtl/led_and_key.v" 
 add_file -verilog -lib work "rtl/tm1638.v" 
 add_file -verilog -lib work "rtl/uart.v" 

rtl/chip_6502.v

@@ -4,7 +4,7 @@ module LOGIC (
     input  [`NUM_NODES-1:0] i,
     output [`NUM_NODES-1:0] o);
 
-    `include "logic.inc"
+    `include "chip_6502_logic.inc"
 endmodule