From 51fc482c088c33a81ca8cebf6c353e0f29c61e2d Mon Sep 17 00:00:00 2001 From: Alan Garfield Date: Fri, 12 Jan 2018 14:36:55 +1100 Subject: [PATCH] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 4c77337..b4cf635 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ This is a basic implementation of the original Apple 1 in Verilog for an iCE40HX FPGA. It can run the Apple 1 WozMon and Integer Basic via the serial USB interface which is available on the iCE40HX8K-B-EVN breakout board. This makes this a very compact little set up. There is no reason this cannot be implemented for other FPGAs with very little work. -This project borrows heavily from the *awesome* work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project where he built a 6502 CPU core in Verilog using the netlist from the Visual 6502 project. Amazing stuff, and so far seems to work perfectly. Also many thanks to many thanks to ["sbprojects.com"](https://www.sbprojects.com/projects/apple1/index.php) for the wealth of information there. +This project borrows heavily from the *awesome* work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project where he built a 6502 CPU core in Verilog using the netlist from the Visual 6502 project. Amazing stuff, and so far seems to work perfectly. Also many special thanks to ["sbprojects.com"](https://www.sbprojects.com/projects/apple1/index.php) for the wealth of information I gleaned from there. ## Memory Map