mirror of
https://github.com/alangarf/apple-one.git
synced 2025-01-20 00:30:05 +00:00
fixed param paths for yosys, may need more work
This commit is contained in:
Alan Garfield
parent
78b3c6f5c6
commit
526538a685
@ -19,22 +19,6 @@ set_io led[2] C4
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set_io led[1] B3
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set_io led[0] C3
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### YL-4 Switch Matrix LEDs (inverted)
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set_io ledx[7] J1
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set_io ledx[6] J2
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set_io ledx[5] K1
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set_io ledx[4] K3
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set_io ledx[3] L1
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set_io ledx[2] L3
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set_io ledx[1] M1
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set_io ledx[0] M2
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### YL-4 Switch Marix Buttons
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set_io button[3] E2
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set_io button[2] F1
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set_io button[1] F2
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set_io button[0] G1
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### PS2 Keyboard
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set_io ps2_clk N3
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set_io ps2_din N2
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@ -46,6 +30,22 @@ set_io vga_red B1
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set_io vga_grn B2
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set_io vga_blu C1
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### YL-4 Switch Marix Buttons
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set_io button[3] E2
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set_io button[2] F1
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set_io button[1] F2
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set_io button[0] G1
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### YL-4 Switch Matrix LEDs (inverted)
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set_io ledx[7] J1
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set_io ledx[6] J2
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set_io ledx[5] K1
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set_io ledx[4] K3
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set_io ledx[3] L1
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set_io ledx[2] L3
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set_io ledx[1] M1
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set_io ledx[0] M2
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### TM1638 Display
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#set_io tm_clk P1
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#set_io tm_dio P2
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@ -1,9 +1,15 @@
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DEVICE = hx8k
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PIN_DEF=ice40hx8k.pcf
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DEVICE = 8k
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PACKAGE = ct256
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FREQ_OSC = 12
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FREQ_PLL = 25
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PIN_DEF = ice40hx8k.pcf
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SOURCEDIR = ../../../rtl
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BUILDDIR = build
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PLL = $(BUILDDIR)/pll.sv
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all: apple1 prog
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info:
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@ -17,10 +23,10 @@ dir:
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# ------ TEMPLATES ------
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$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
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yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^
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yosys -q -p "synth_ice40 -top apple1_top -blif $@" $^
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$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
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arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^
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arachne-pnr -d $(DEVICE) -P $(PACKAGE) -o $@ -p $^
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$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
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icepack $^ $@
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@ -34,8 +40,11 @@ $(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
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%_tb.vcd: %_tb.vvp
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vvp -N $< +vcd=$@
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$(PLL):
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icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
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# ------ APPLE 1 ------
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apple1: dir $(BUILDDIR)/apple1.bin
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apple1: dir $(PLL) $(BUILDDIR)/apple1.bin
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report: dir apple1.rpt
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$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
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@ -56,8 +65,8 @@ $(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
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$(SOURCEDIR)/vga/font_rom.v \
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$(SOURCEDIR)/ps2keyboard/debounce.v \
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$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
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$(SOURCEDIR)/boards/ice40hx8k/clock_pll.v \
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$(SOURCEDIR)/boards/ice40hx8k/apple1_hx8k.v
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$(SOURCEDIR)/boards/ice40hx8k-b-evn/apple1_hx8k.v \
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$(BUILDDIR)/pll.sv
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apple1.rpt: $(BUILDDIR)/apple1.asc
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16
rtl/apple1.v
16
rtl/apple1.v
@ -23,11 +23,11 @@
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//
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module apple1 #(
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parameter BASIC_FILENAME = "",
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parameter FONT_ROM_FILENAME = "",
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parameter RAM_FILENAME = "",
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parameter VRAM_FILENAME = "",
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parameter WOZMON_ROM_FILENAME = ""
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parameter BASIC_FILENAME = "../../../roms/basic.hex",
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parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
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parameter RAM_FILENAME = "../../../roms/ram.hex",
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parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
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parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
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) (
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input clk25, // 25 MHz master clock
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input rst_n, // active low synchronous reset (needed for simulation)
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@ -138,7 +138,7 @@ module apple1 #(
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// WozMon ROM
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wire [7:0] rom_dout;
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rom_wozmon #(
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.ROM_FILENAME (WOZMON_ROM_FILENAME)
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.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
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) my_rom_wozmon(
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.clk(clk25),
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.address(ab[7:0]),
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@ -198,8 +198,8 @@ module apple1 #(
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// VGA Display interface
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reg [1:0] vga_mode;
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vga #(
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.RAM_FILENAME (VRAM_FILENAME),
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.ROM_FILENAME (FONT_ROM_FILENAME)
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.VRAM_FILENAME (VRAM_FILENAME),
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.FONT_ROM_FILENAME (FONT_ROM_FILENAME)
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) my_vga(
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.clk25(clk25),
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.enable(vga_cs & cpu_clken),
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@ -56,11 +56,10 @@ module apple1_top #(
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wire clk25;
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// 12MHz up to 25MHz
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clock_pll clock_pll_inst(
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.REFERENCECLK(clk),
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.PLLOUTGLOBAL(clk25),
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.RESET(1'b1)
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);
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pll my_pll(
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.clock_in(clk),
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.clock_out(clk25)
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);
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wire [15:0] pc_monitor;
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assign led[7:0] = pc_monitor[7:0];
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@ -99,7 +98,7 @@ module apple1_top #(
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.uart_cts(uart_cts),
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.ps2_clk(ps2__clk),
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.ps2_din(ps2__din),
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.ps2_select(1'b0),
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.ps2_select(1'b1),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_red),
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@ -1,38 +0,0 @@
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module clock_pll(REFERENCECLK,
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PLLOUTCORE,
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PLLOUTGLOBAL,
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RESET);
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input REFERENCECLK;
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input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
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output PLLOUTCORE;
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output PLLOUTGLOBAL;
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SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
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.PLLOUTCORE(PLLOUTCORE),
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.PLLOUTGLOBAL(PLLOUTGLOBAL),
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.EXTFEEDBACK(),
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.DYNAMICDELAY(),
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.RESETB(RESET),
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.BYPASS(1'b0),
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.LATCHINPUTVALUE(),
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.LOCK(),
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.SDI(),
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.SDO(),
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.SCLK());
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//\\ Fin=12, Fout=25;
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defparam clock_pll_inst.DIVR = 4'b0000;
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defparam clock_pll_inst.DIVF = 7'b1000010;
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defparam clock_pll_inst.DIVQ = 3'b101;
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defparam clock_pll_inst.FILTER_RANGE = 3'b001;
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defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
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defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
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defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
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defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
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defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
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defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
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defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
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defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
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endmodule
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@ -1,4 +0,0 @@
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clock_pll clock_pll_inst(.REFERENCECLK(),
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.PLLOUTCORE(),
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.PLLOUTGLOBAL(),
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.RESET());
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@ -1,5 +0,0 @@
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[General]
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DeviceFamily=iCE40
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[AdditionalDelay]
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AdditionalDelayNo=true
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@ -22,15 +22,15 @@
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// Date.......: 26-1-2018
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//
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module ram(
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module ram #(
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parameter RAM_FILENAME = "../../../roms/ram.hex"
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) (
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input clk, // clock signal
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input [12:0] address, // address bus
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input w_en, // active high write enable strobe
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input [7:0] din, // 8-bit data bus (input)
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output reg [7:0] dout // 8-bit data bus (output)
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);
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parameter RAM_FILENAME = "";
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);
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reg [7:0] ram_data[0:8191];
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@ -22,13 +22,13 @@
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// Date.......: 26-1-2018
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//
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module rom_basic(
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module rom_basic #(
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parameter BASIC_FILENAME = "../../../roms/basic.hex"
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) (
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input clk, // clock signal
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input [11:0] address, // address bus
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output reg [7:0] dout // 8-bit data bus (output)
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);
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parameter BASIC_FILENAME = "";
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);
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reg [7:0] rom_data[0:4095];
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@ -22,18 +22,18 @@
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// Date.......: 26-1-2018
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//
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module rom_wozmon(
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module rom_wozmon #(
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parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
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) (
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input clk, // clock signal
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input [7:0] address, // address bus
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output reg [7:0] dout // 8-bit data bus (output)
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);
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parameter ROM_FILENAME = "";
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);
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reg [7:0] rom_data[0:255];
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initial
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$readmemh(ROM_FILENAME, rom_data, 0, 255);
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$readmemh(WOZMON_ROM_FILENAME, rom_data, 0, 255);
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always @(posedge clk)
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dout <= rom_data[address];
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@ -20,11 +20,10 @@
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// Author.....: Alan Garfield
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// Date.......: 3-2-2018
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//
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//`define DOTTY
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//`define SCANLINES
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`define NORMAL
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module font_rom(
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module font_rom #(
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parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex"
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) (
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input clk, // clock signal
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input [1:0] mode, // character mode
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input [5:0] character, // address bus
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@ -33,12 +32,10 @@ module font_rom(
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output reg out // single pixel from address and pixel pos
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);
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parameter ROM_FILENAME = "";
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reg [7:0] rom[0:1023];
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initial
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$readmemh(ROM_FILENAME, rom, 0, 1023);
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$readmemh(FONT_ROM_FILENAME, rom, 0, 1023);
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// double height of pixel by ignoring bit 0
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wire [3:0] line_ptr = line[4:1];
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@ -1,4 +1,7 @@
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module vga(
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module vga #(
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parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
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parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex"
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) (
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input clk25, // clock signal
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input enable, // clock enable strobe,
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input rst, // active high reset signal
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@ -11,7 +14,7 @@ module vga(
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input w_en, // active high write enable strobe
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input [7:0] din, // 8-bit data bus (input)
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input [1:0] mode // 2-bit mode setting for pixel doubling
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);
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);
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//////////////////////////////////////////////////////////////////////////
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// Registers and Parameters
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@ -26,9 +29,6 @@ module vga(
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parameter vbp = 31; // end of vertical back porch
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parameter vfp = 511; // beginning of vertical front porch
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// Video RAM contents
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parameter RAM_FILENAME = "";
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// registers for storing the horizontal & vertical counters
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reg [9:0] h_cnt;
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reg [9:0] v_cnt;
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@ -123,7 +123,7 @@ module vga(
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// Character ROM
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font_rom #(
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.ROM_FILENAME (ROM_FILENAME)
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.FONT_ROM_FILENAME (FONT_ROM_FILENAME)
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) my_font_rom(
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.clk(clk25),
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.mode(mode),
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@ -137,7 +137,7 @@ module vga(
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// Video RAM
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vram #(
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.RAM_FILENAME (RAM_FILENAME)
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.VRAM_FILENAME (VRAM_FILENAME)
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) my_vram(
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.clk(clk25),
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.read_addr(vram_r_addr),
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@ -22,7 +22,9 @@
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// Date.......: 26-1-2018
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//
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module vram(
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module vram #(
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parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
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) (
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input clk, // clock signal
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input [10:0] read_addr, // read address bus
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input [10:0] write_addr, // write address bus
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@ -30,14 +32,12 @@ module vram(
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input w_en, // active high write enable strobe
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input [5:0] din, // 6-bit data bus (input)
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output reg [5:0] dout // 6-bit data bus (output)
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);
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parameter RAM_FILENAME = "";
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);
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reg [5:0] ram_data[0:2047];
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initial
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$readmemb(RAM_FILENAME, ram_data, 0, 2047);
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$readmemb(VRAM_FILENAME, ram_data, 0, 2047);
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always @(posedge clk)
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begin
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