From 5e3f0652232975ef05583765ad26a55c7ce43c97 Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@gmail.com>
Date: Sat, 27 Jan 2018 01:21:47 +0100
Subject: [PATCH] Forced some internal CPU signals at start of simuation to get
 rid of undefined signals. Also made sure hard_reset signal is never undefined

---
 iverilog/apple1_top_tb.v | 10 ++++++++++
 rtl/apple1_top.v         |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/iverilog/apple1_top_tb.v b/iverilog/apple1_top_tb.v
index 4c003e0..55caaec 100644
--- a/iverilog/apple1_top_tb.v
+++ b/iverilog/apple1_top_tb.v
@@ -32,11 +32,21 @@ module apple1_top_tb;
     // Setup dumping of data for inspection
 
     initial begin
+        force core_top.my_cpu.DIHOLD = 0;
+        force core_top.my_cpu.ALU.OUT = 0;
+        force core_top.my_cpu.PC = 0;
+        force core_top.my_cpu.ALU.temp_logic = 0;
+
         clk25 = 1'b0;
         uart_rx = 1'b0;
         rst_n = 1'b0;         
         #40 rst_n = 1'b1;
 
+        release core_top.my_cpu.DIHOLD;
+        release core_top.my_cpu.PC;
+        release core_top.my_cpu.ALU.OUT;
+        release core_top.my_cpu.ALU.temp_logic;
+
         $display("Starting...");
         $dumpfile("apple1_top_tb.vcd");
         $dumpvars;                
diff --git a/rtl/apple1_top.v b/rtl/apple1_top.v
index dfad67b..658908f 100644
--- a/rtl/apple1_top.v
+++ b/rtl/apple1_top.v
@@ -80,7 +80,7 @@ module top(
         if (rst_n == 1'b0)
         begin
             reset_cnt  <= 6'b0;
-            //hard_reset <= 1'b0; we should init hard_reset here too..
+            hard_reset <= 1'b0;
         end
         else if (cpu_clken)
         begin