From 6823d0e3f94c6c1a375d173fc20644df6536590f Mon Sep 17 00:00:00 2001 From: Niels Moseley Date: Sat, 27 Jan 2018 18:11:33 +0100 Subject: [PATCH] Added 6502 PC monitoring --- boards/ice40hx8k/appleone_sbt.project | 6 +- boards/terasic_de0/apple-one.qsf | 20 +- iverilog/apple1_tb.v | 287 ++++++++++++------------ rtl/apple1.v | 50 +++-- rtl/boards/terasic_de0/apple1_de0_top.v | 48 +++- rtl/cpu/arlet/cpu.v | 5 +- rtl/cpu/arlet_6502.v | 24 +- 7 files changed, 261 insertions(+), 179 deletions(-) diff --git a/boards/ice40hx8k/appleone_sbt.project b/boards/ice40hx8k/appleone_sbt.project index abf69b5..bae845f 100644 --- a/boards/ice40hx8k/appleone_sbt.project +++ b/boards/ice40hx8k/appleone_sbt.project @@ -19,9 +19,9 @@ DevicePower= NetlistFile=appleone_Implmnt/appleone.edf AdditionalEDIFFile= IPEDIFFile= -DesignLib=appleone_Implmnt/sbt/netlist/oadb-apple1_top -DesignView=_rt -DesignCell=apple1_top +DesignLib= +DesignView= +DesignCell= SynthesisSDCFile=appleone_Implmnt/appleone.scf UserPinConstraintFile= UserSDCFile= diff --git a/boards/terasic_de0/apple-one.qsf b/boards/terasic_de0/apple-one.qsf index 46d1dba..d575ad8 100644 --- a/boards/terasic_de0/apple-one.qsf +++ b/boards/terasic_de0/apple-one.qsf @@ -71,6 +71,13 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2] @@ -85,6 +92,14 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD set_location_assignment PIN_B1 -to LEDG[9] set_location_assignment PIN_B2 -to LEDG[8] @@ -344,14 +359,15 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp +set_global_assignment -name VERILOG_FILE ../../rtl/boards/terasic_de0/segmentdisplay.v set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet/cpu.v set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet/ALU.v set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet_6502.v set_global_assignment -name VERILOG_FILE ../../rtl/apple1.v set_global_assignment -name SDC_FILE "apple-one.sdc" set_global_assignment -name VERILOG_FILE ../../rtl/boards/terasic_de0/apple1_de0_top.v -set_global_assignment -name VERILOG_FILE ../../rtl/cpu/cpu.v -set_global_assignment -name VERILOG_FILE ../../rtl/cpu/ALU.v set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart.v set_global_assignment -name VERILOG_FILE ../../rtl/uart/async_tx_rx.v set_global_assignment -name VERILOG_FILE ../../rtl/rom_wozmon.v diff --git a/iverilog/apple1_tb.v b/iverilog/apple1_tb.v index 753770d..f51f0ec 100644 --- a/iverilog/apple1_tb.v +++ b/iverilog/apple1_tb.v @@ -32,156 +32,157 @@ module apple1_tb; // Setup dumping of data for inspection initial begin - force core_top.clk_div = 0; - force core_top.cpu_clken = 0; - force core_top.hard_reset = 0; - force core_top.reset_cnt = 0; - force core_top.my_cpu.arlet_cpu.AB = 0; - force core_top.my_cpu.arlet_cpu.PC = 0; - force core_top.my_cpu.arlet_cpu.ABL = 0; - force core_top.my_cpu.arlet_cpu.ABH = 0; - force core_top.my_cpu.arlet_cpu.DIHOLD = 0; - force core_top.my_cpu.arlet_cpu.IRHOLD = 0; - force core_top.my_cpu.arlet_cpu.IRHOLD_valid = 0; - force core_top.my_cpu.arlet_cpu.C = 0; - force core_top.my_cpu.arlet_cpu.Z = 0; - force core_top.my_cpu.arlet_cpu.I = 0; - force core_top.my_cpu.arlet_cpu.D = 0; - force core_top.my_cpu.arlet_cpu.V = 0; - force core_top.my_cpu.arlet_cpu.N = 0; - force core_top.my_cpu.arlet_cpu.AI = 0; - force core_top.my_cpu.arlet_cpu.BI = 0; - force core_top.my_cpu.arlet_cpu.DO = 0; - force core_top.my_cpu.arlet_cpu.WE = 0; - force core_top.my_cpu.arlet_cpu.CI = 0; - force core_top.my_cpu.arlet_cpu.NMI_edge = 0; - force core_top.my_cpu.arlet_cpu.regsel = 0; - force core_top.my_cpu.arlet_cpu.PC_inc = 0; - force core_top.my_cpu.arlet_cpu.PC_temp = 0; - force core_top.my_cpu.arlet_cpu.src_reg = 0; - force core_top.my_cpu.arlet_cpu.dst_reg = 0; - force core_top.my_cpu.arlet_cpu.index_y = 0; - force core_top.my_cpu.arlet_cpu.load_reg = 0; - force core_top.my_cpu.arlet_cpu.inc = 0; - force core_top.my_cpu.arlet_cpu.write_back = 0; - force core_top.my_cpu.arlet_cpu.load_only = 0; - force core_top.my_cpu.arlet_cpu.store = 0; - force core_top.my_cpu.arlet_cpu.adc_sbc = 0; - force core_top.my_cpu.arlet_cpu.compare = 0; - force core_top.my_cpu.arlet_cpu.shift = 0; - force core_top.my_cpu.arlet_cpu.rotate = 0; - force core_top.my_cpu.arlet_cpu.backwards = 0; - force core_top.my_cpu.arlet_cpu.cond_true = 0; - force core_top.my_cpu.arlet_cpu.cond_code = 0; - force core_top.my_cpu.arlet_cpu.shift_right = 0; - force core_top.my_cpu.arlet_cpu.alu_shift_right = 0; - force core_top.my_cpu.arlet_cpu.op = 0; - force core_top.my_cpu.arlet_cpu.alu_op = 0; - force core_top.my_cpu.arlet_cpu.adc_bcd = 0; - force core_top.my_cpu.arlet_cpu.adj_bcd = 0; - force core_top.my_cpu.arlet_cpu.bit_ins = 0; - force core_top.my_cpu.arlet_cpu.plp = 0; - force core_top.my_cpu.arlet_cpu.php = 0; - force core_top.my_cpu.arlet_cpu.clc = 0; - force core_top.my_cpu.arlet_cpu.sed = 0; - force core_top.my_cpu.arlet_cpu.cli = 0; - force core_top.my_cpu.arlet_cpu.sei = 0; - force core_top.my_cpu.arlet_cpu.clv = 0; - force core_top.my_cpu.arlet_cpu.brk = 0; - force core_top.my_cpu.arlet_cpu.res = 0; - force core_top.my_cpu.arlet_cpu.write_register = 0; - force core_top.my_cpu.arlet_cpu.ADJL = 0; - force core_top.my_cpu.arlet_cpu.ADJH = 0; - force core_top.my_cpu.arlet_cpu.NMI_1 = 0; - force core_top.my_cpu.arlet_cpu.ALU.OUT = 0; - force core_top.my_cpu.arlet_cpu.ALU.CO = 0; - force core_top.my_cpu.arlet_cpu.ALU.N = 0; - force core_top.my_cpu.arlet_cpu.ALU.HC = 0; - force core_top.my_cpu.arlet_cpu.ALU.AI7 = 0; - force core_top.my_cpu.arlet_cpu.ALU.BI7 = 0; - force core_top.my_cpu.arlet_cpu.ALU.temp_logic = 0; - force core_top.my_cpu.arlet_cpu.ALU.temp_BI = 0; - force core_top.my_cpu.arlet_cpu.ALU.temp_l = 0; - force core_top.my_cpu.arlet_cpu.ALU.temp_h = 0; + // force core_top.clk_div = 0; + // force core_top.cpu_clken = 0; + // force core_top.hard_reset = 0; + // force core_top.reset_cnt = 0; + + // force core_top.my_cpu.arlet_cpu.AB = 0; + // force core_top.my_cpu.arlet_cpu.PC = 0; + // force core_top.my_cpu.arlet_cpu.ABL = 0; + // force core_top.my_cpu.arlet_cpu.ABH = 0; + // force core_top.my_cpu.arlet_cpu.DIHOLD = 0; + // force core_top.my_cpu.arlet_cpu.IRHOLD = 0; + // force core_top.my_cpu.arlet_cpu.IRHOLD_valid = 0; + // force core_top.my_cpu.arlet_cpu.C = 0; + // force core_top.my_cpu.arlet_cpu.Z = 0; + // force core_top.my_cpu.arlet_cpu.I = 0; + // force core_top.my_cpu.arlet_cpu.D = 0; + // force core_top.my_cpu.arlet_cpu.V = 0; + // force core_top.my_cpu.arlet_cpu.N = 0; + // force core_top.my_cpu.arlet_cpu.AI = 0; + // force core_top.my_cpu.arlet_cpu.BI = 0; + // force core_top.my_cpu.arlet_cpu.DO = 0; + // force core_top.my_cpu.arlet_cpu.WE = 0; + // force core_top.my_cpu.arlet_cpu.CI = 0; + // force core_top.my_cpu.arlet_cpu.NMI_edge = 0; + // force core_top.my_cpu.arlet_cpu.regsel = 0; + // force core_top.my_cpu.arlet_cpu.PC_inc = 0; + // force core_top.my_cpu.arlet_cpu.PC_temp = 0; + // force core_top.my_cpu.arlet_cpu.src_reg = 0; + // force core_top.my_cpu.arlet_cpu.dst_reg = 0; + // force core_top.my_cpu.arlet_cpu.index_y = 0; + // force core_top.my_cpu.arlet_cpu.load_reg = 0; + // force core_top.my_cpu.arlet_cpu.inc = 0; + // force core_top.my_cpu.arlet_cpu.write_back = 0; + // force core_top.my_cpu.arlet_cpu.load_only = 0; + // force core_top.my_cpu.arlet_cpu.store = 0; + // force core_top.my_cpu.arlet_cpu.adc_sbc = 0; + // force core_top.my_cpu.arlet_cpu.compare = 0; + // force core_top.my_cpu.arlet_cpu.shift = 0; + // force core_top.my_cpu.arlet_cpu.rotate = 0; + // force core_top.my_cpu.arlet_cpu.backwards = 0; + // force core_top.my_cpu.arlet_cpu.cond_true = 0; + // force core_top.my_cpu.arlet_cpu.cond_code = 0; + // force core_top.my_cpu.arlet_cpu.shift_right = 0; + // force core_top.my_cpu.arlet_cpu.alu_shift_right = 0; + // force core_top.my_cpu.arlet_cpu.op = 0; + // force core_top.my_cpu.arlet_cpu.alu_op = 0; + // force core_top.my_cpu.arlet_cpu.adc_bcd = 0; + // force core_top.my_cpu.arlet_cpu.adj_bcd = 0; + // force core_top.my_cpu.arlet_cpu.bit_ins = 0; + // force core_top.my_cpu.arlet_cpu.plp = 0; + // force core_top.my_cpu.arlet_cpu.php = 0; + // force core_top.my_cpu.arlet_cpu.clc = 0; + // force core_top.my_cpu.arlet_cpu.sed = 0; + // force core_top.my_cpu.arlet_cpu.cli = 0; + // force core_top.my_cpu.arlet_cpu.sei = 0; + // force core_top.my_cpu.arlet_cpu.clv = 0; + // force core_top.my_cpu.arlet_cpu.brk = 0; + // force core_top.my_cpu.arlet_cpu.res = 0; + // force core_top.my_cpu.arlet_cpu.write_register = 0; + // force core_top.my_cpu.arlet_cpu.ADJL = 0; + // force core_top.my_cpu.arlet_cpu.ADJH = 0; + // force core_top.my_cpu.arlet_cpu.NMI_1 = 0; + // force core_top.my_cpu.arlet_cpu.ALU.OUT = 0; + // force core_top.my_cpu.arlet_cpu.ALU.CO = 0; + // force core_top.my_cpu.arlet_cpu.ALU.N = 0; + // force core_top.my_cpu.arlet_cpu.ALU.HC = 0; + // force core_top.my_cpu.arlet_cpu.ALU.AI7 = 0; + // force core_top.my_cpu.arlet_cpu.ALU.BI7 = 0; + // force core_top.my_cpu.arlet_cpu.ALU.temp_logic = 0; + // force core_top.my_cpu.arlet_cpu.ALU.temp_BI = 0; + // force core_top.my_cpu.arlet_cpu.ALU.temp_l = 0; + // force core_top.my_cpu.arlet_cpu.ALU.temp_h = 0; clk25 = 1'b0; uart_rx = 1'b1; rst_n = 1'b0; #40 rst_n = 1'b1; - release core_top.clk_div; - release core_top.cpu_clken; - release core_top.hard_reset; - release core_top.reset_cnt; - release core_top.my_cpu.arlet_cpu.AB; - release core_top.my_cpu.arlet_cpu.PC; - release core_top.my_cpu.arlet_cpu.ABL; - release core_top.my_cpu.arlet_cpu.ABH; - release core_top.my_cpu.arlet_cpu.DIHOLD; - release core_top.my_cpu.arlet_cpu.IRHOLD; - release core_top.my_cpu.arlet_cpu.IRHOLD_valid; - release core_top.my_cpu.arlet_cpu.C; - release core_top.my_cpu.arlet_cpu.Z; - release core_top.my_cpu.arlet_cpu.I; - release core_top.my_cpu.arlet_cpu.D; - release core_top.my_cpu.arlet_cpu.V; - release core_top.my_cpu.arlet_cpu.N; - release core_top.my_cpu.arlet_cpu.AI; - release core_top.my_cpu.arlet_cpu.BI; - release core_top.my_cpu.arlet_cpu.DO; - release core_top.my_cpu.arlet_cpu.WE; - release core_top.my_cpu.arlet_cpu.CI; - release core_top.my_cpu.arlet_cpu.NMI_edge; - release core_top.my_cpu.arlet_cpu.regsel; - release core_top.my_cpu.arlet_cpu.PC_inc; - release core_top.my_cpu.arlet_cpu.PC_temp; - release core_top.my_cpu.arlet_cpu.src_reg; - release core_top.my_cpu.arlet_cpu.dst_reg; - release core_top.my_cpu.arlet_cpu.index_y; - release core_top.my_cpu.arlet_cpu.load_reg; - release core_top.my_cpu.arlet_cpu.inc; - release core_top.my_cpu.arlet_cpu.write_back; - release core_top.my_cpu.arlet_cpu.load_only; - release core_top.my_cpu.arlet_cpu.store; - release core_top.my_cpu.arlet_cpu.adc_sbc; - release core_top.my_cpu.arlet_cpu.compare; - release core_top.my_cpu.arlet_cpu.shift; - release core_top.my_cpu.arlet_cpu.rotate; - release core_top.my_cpu.arlet_cpu.backwards; - release core_top.my_cpu.arlet_cpu.cond_true; - release core_top.my_cpu.arlet_cpu.cond_code; - release core_top.my_cpu.arlet_cpu.shift_right; - release core_top.my_cpu.arlet_cpu.alu_shift_right; - release core_top.my_cpu.arlet_cpu.op; - release core_top.my_cpu.arlet_cpu.alu_op; - release core_top.my_cpu.arlet_cpu.adc_bcd; - release core_top.my_cpu.arlet_cpu.adj_bcd; - release core_top.my_cpu.arlet_cpu.bit_ins; - release core_top.my_cpu.arlet_cpu.plp; - release core_top.my_cpu.arlet_cpu.php; - release core_top.my_cpu.arlet_cpu.clc; - release core_top.my_cpu.arlet_cpu.sec; - release core_top.my_cpu.arlet_cpu.cld; - release core_top.my_cpu.arlet_cpu.sed; - release core_top.my_cpu.arlet_cpu.sei; - release core_top.my_cpu.arlet_cpu.clv; - release core_top.my_cpu.arlet_cpu.brk; - release core_top.my_cpu.arlet_cpu.res; - release core_top.my_cpu.arlet_cpu.write_register; - release core_top.my_cpu.arlet_cpu.ADJL; - release core_top.my_cpu.arlet_cpu.ADJH; - release core_top.my_cpu.arlet_cpu.NMI_1; - release core_top.my_cpu.arlet_cpu.ALU.OUT; - release core_top.my_cpu.arlet_cpu.ALU.CO; - release core_top.my_cpu.arlet_cpu.ALU.N; - release core_top.my_cpu.arlet_cpu.ALU.HC; - release core_top.my_cpu.arlet_cpu.ALU.AI7; - release core_top.my_cpu.arlet_cpu.ALU.BI7; - release core_top.my_cpu.arlet_cpu.ALU.temp_logic; - release core_top.my_cpu.arlet_cpu.ALU.temp_BI; - release core_top.my_cpu.arlet_cpu.ALU.temp_l; - release core_top.my_cpu.arlet_cpu.ALU.temp_h; + // release core_top.clk_div; + // release core_top.cpu_clken; + // release core_top.hard_reset; + // release core_top.reset_cnt; + // release core_top.my_cpu.arlet_cpu.AB; + // release core_top.my_cpu.arlet_cpu.PC; + // release core_top.my_cpu.arlet_cpu.ABL; + // release core_top.my_cpu.arlet_cpu.ABH; + // release core_top.my_cpu.arlet_cpu.DIHOLD; + // release core_top.my_cpu.arlet_cpu.IRHOLD; + // release core_top.my_cpu.arlet_cpu.IRHOLD_valid; + // release core_top.my_cpu.arlet_cpu.C; + // release core_top.my_cpu.arlet_cpu.Z; + // release core_top.my_cpu.arlet_cpu.I; + // release core_top.my_cpu.arlet_cpu.D; + // release core_top.my_cpu.arlet_cpu.V; + // release core_top.my_cpu.arlet_cpu.N; + // release core_top.my_cpu.arlet_cpu.AI; + // release core_top.my_cpu.arlet_cpu.BI; + // release core_top.my_cpu.arlet_cpu.DO; + // release core_top.my_cpu.arlet_cpu.WE; + // release core_top.my_cpu.arlet_cpu.CI; + // release core_top.my_cpu.arlet_cpu.NMI_edge; + // release core_top.my_cpu.arlet_cpu.regsel; + // release core_top.my_cpu.arlet_cpu.PC_inc; + // release core_top.my_cpu.arlet_cpu.PC_temp; + // release core_top.my_cpu.arlet_cpu.src_reg; + // release core_top.my_cpu.arlet_cpu.dst_reg; + // release core_top.my_cpu.arlet_cpu.index_y; + // release core_top.my_cpu.arlet_cpu.load_reg; + // release core_top.my_cpu.arlet_cpu.inc; + // release core_top.my_cpu.arlet_cpu.write_back; + // release core_top.my_cpu.arlet_cpu.load_only; + // release core_top.my_cpu.arlet_cpu.store; + // release core_top.my_cpu.arlet_cpu.adc_sbc; + // release core_top.my_cpu.arlet_cpu.compare; + // release core_top.my_cpu.arlet_cpu.shift; + // release core_top.my_cpu.arlet_cpu.rotate; + // release core_top.my_cpu.arlet_cpu.backwards; + // release core_top.my_cpu.arlet_cpu.cond_true; + // release core_top.my_cpu.arlet_cpu.cond_code; + // release core_top.my_cpu.arlet_cpu.shift_right; + // release core_top.my_cpu.arlet_cpu.alu_shift_right; + // release core_top.my_cpu.arlet_cpu.op; + // release core_top.my_cpu.arlet_cpu.alu_op; + // release core_top.my_cpu.arlet_cpu.adc_bcd; + // release core_top.my_cpu.arlet_cpu.adj_bcd; + // release core_top.my_cpu.arlet_cpu.bit_ins; + // release core_top.my_cpu.arlet_cpu.plp; + // release core_top.my_cpu.arlet_cpu.php; + // release core_top.my_cpu.arlet_cpu.clc; + // release core_top.my_cpu.arlet_cpu.sec; + // release core_top.my_cpu.arlet_cpu.cld; + // release core_top.my_cpu.arlet_cpu.sed; + // release core_top.my_cpu.arlet_cpu.sei; + // release core_top.my_cpu.arlet_cpu.clv; + // release core_top.my_cpu.arlet_cpu.brk; + // release core_top.my_cpu.arlet_cpu.res; + // release core_top.my_cpu.arlet_cpu.write_register; + // release core_top.my_cpu.arlet_cpu.ADJL; + // release core_top.my_cpu.arlet_cpu.ADJH; + // release core_top.my_cpu.arlet_cpu.NMI_1; + // release core_top.my_cpu.arlet_cpu.ALU.OUT; + // release core_top.my_cpu.arlet_cpu.ALU.CO; + // release core_top.my_cpu.arlet_cpu.ALU.N; + // release core_top.my_cpu.arlet_cpu.ALU.HC; + // release core_top.my_cpu.arlet_cpu.ALU.AI7; + // release core_top.my_cpu.arlet_cpu.ALU.BI7; + // release core_top.my_cpu.arlet_cpu.ALU.temp_logic; + // release core_top.my_cpu.arlet_cpu.ALU.temp_BI; + // release core_top.my_cpu.arlet_cpu.ALU.temp_l; + // release core_top.my_cpu.arlet_cpu.ALU.temp_h; $display("Starting..."); $dumpfile("apple1_top_tb.vcd"); diff --git a/rtl/apple1.v b/rtl/apple1.v index 750e3a1..992a7e0 100644 --- a/rtl/apple1.v +++ b/rtl/apple1.v @@ -4,7 +4,9 @@ module apple1( input uart_rx, output uart_tx, - output uart_cts + output uart_cts, + + output [15:0] pc_monitor // spy for program counter / debugging ); parameter RAM_FILENAME = "../../roms/ram.hex"; parameter WOZ_FILENAME = "../../roms/wozmon.hex"; @@ -16,7 +18,7 @@ module apple1( wire [7:0] dbi; wire [7:0] dbo; wire we; - + ////////////////////////////////////////////////////////////////////////// // Clocks @@ -29,19 +31,36 @@ module apple1( // in simulation // - reg [4:0] clk_div; - reg cpu_clken; - always @(posedge clk25) - begin - // note: clk_div should be compared to - // N-1, where N is the clock divisor - if ((clk_div == 24) || (rst_n == 1'b0)) - clk_div <= 0; - else - clk_div <= clk_div + 1'b1; + //`define SLOWCPU + `ifdef SLOWCPU + reg [25:0] clk_div; + reg cpu_clken; + always @(posedge clk25) + begin + // note: clk_div should be compared to + // N-1, where N is the clock divisor + if ((clk_div == 4999999) || (rst_n == 1'b0)) + clk_div <= 0; + else + clk_div <= clk_div + 1'b1; - cpu_clken <= (clk_div[4:0] == 0); - end + cpu_clken <= (clk_div[25:0] == 0); + end + `else + reg [4:0] clk_div; + reg cpu_clken; + always @(posedge clk25) + begin + // note: clk_div should be compared to + // N-1, where N is the clock divisor + if ((clk_div == 24) || (rst_n == 1'b0)) + clk_div <= 0; + else + clk_div <= clk_div + 1'b1; + + cpu_clken <= (clk_div[4:0] == 0); + end + `endif ////////////////////////////////////////////////////////////////////////// // Reset @@ -80,7 +99,8 @@ module apple1( .we (we), .irq_n (1'b1), .nmi_n (1'b1), - .ready (cpu_clken) + .ready (cpu_clken), + .pc_monitor (pc_monitor) ); ////////////////////////////////////////////////////////////////////////// diff --git a/rtl/boards/terasic_de0/apple1_de0_top.v b/rtl/boards/terasic_de0/apple1_de0_top.v index 4c2df0e..fb8687a 100644 --- a/rtl/boards/terasic_de0/apple1_de0_top.v +++ b/rtl/boards/terasic_de0/apple1_de0_top.v @@ -28,27 +28,67 @@ module apple1_de0_top( // UART I/O signals output UART_TXD, // UART transmit pin on DE0 board input UART_RXD, // UART receive pin on DE0 board - output UART_CTS // UART clear-to-send pin on DE0 board + output UART_CTS, // UART clear-to-send pin on DE0 board + + output [7:0] LEDG, // monitoring for lower 8 address bits + input [2:0] BUTTON, // BUTTON[0] for reset + output [6:0] HEX0_D, + output [6:0] HEX1_D, + output [6:0] HEX2_D, + output [6:0] HEX3_D ); ////////////////////////////////////////////////////////////////////////// // Registers and Wires reg clk25; + wire [15:0] pc_monitor; // generate 25MHz clock from 50MHz master clock always @(posedge CLOCK_50) begin clk25 <= ~clk25; end - + ////////////////////////////////////////////////////////////////////////// // Core of system apple1 apple1_top( .clk25(clk25), - .rst_n(1'b1), // we don't have any reset pulse.. + .rst_n(BUTTON[0]), // we don't have any reset pulse.. .uart_rx(UART_RXD), .uart_tx(UART_TXD), - .uart_cts(UART_CTS) + .uart_cts(UART_CTS), + .pc_monitor(pc_monitor) ); + ////////////////////////////////////////////////////////////////////////// + // Display 6502 address on 7-segment displays + + segmentdisplay seg1( + .clk(clk25), + .latch(1'b1), + .hexdigit_in(pc_monitor[3:0]), + .display_out(HEX0_D) + ); + + segmentdisplay seg2( + .clk(clk25), + .latch(1'b1), + .hexdigit_in(pc_monitor[7:4]), + .display_out(HEX1_D) + ); + + segmentdisplay seg3( + .clk(clk25), + .latch(1'b1), + .hexdigit_in(pc_monitor[11:8]), + .display_out(HEX2_D) + ); + + segmentdisplay seg4( + .clk(clk25), + .latch(1'b1), + .hexdigit_in(pc_monitor[15:12]), + .display_out(HEX3_D) + ); + endmodule \ No newline at end of file diff --git a/rtl/cpu/arlet/cpu.v b/rtl/cpu/arlet/cpu.v index 6c0c531..edb4e86 100644 --- a/rtl/cpu/arlet/cpu.v +++ b/rtl/cpu/arlet/cpu.v @@ -21,7 +21,7 @@ // FIXME - Need to make this flag reach out to test bench //`define SIM -module cpu( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY ); +module cpu( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY, PC_MONITOR ); input clk; // CPU clock input reset; // reset signal @@ -32,6 +32,7 @@ output WE; // write enable input IRQ; // interrupt request input NMI; // non-maskable interrupt request input RDY; // Ready signal. Pauses CPU when RDY=0 +output PC_MONITOR; // signal to spy / monitor the program counter for debugging /* * internal signals @@ -72,6 +73,8 @@ wire CO; // Carry Out wire [7:0] PCH = PC[15:8]; wire [7:0] PCL = PC[7:0]; +assign PC_MONITOR = PC; // generate PC monitor signal + reg NMI_edge = 0; // captured NMI edge reg [1:0] regsel; // Select A, X, Y or S register diff --git a/rtl/cpu/arlet_6502.v b/rtl/cpu/arlet_6502.v index 3cd7f1e..e44ab50 100644 --- a/rtl/cpu/arlet_6502.v +++ b/rtl/cpu/arlet_6502.v @@ -1,14 +1,15 @@ module arlet_6502( - input clk, - input enable, - input reset, - output reg [15:0] ab, - input [7:0] dbi, - output reg [7:0] dbo, - output reg we, - input irq_n, - input nmi_n, - input ready + input clk, // clock signal + input enable, // clock enable strobe + input reset, // active high reset signal + output reg [15:0] ab, // address bus + input [7:0] dbi, // 8-bit data bus (input) + output reg [7:0] dbo, // 8-bit data bus (output) + output reg we, // active high write enable strobe + input irq_n, // active low interrupt request + input nmi_n, // active low non-maskable interrupt + input ready, // CPU updates when ready = 1 + output [15:0] pc_monitor // program counter monitor signal for debugging ); wire [7:0] dbo_c; @@ -24,7 +25,8 @@ module arlet_6502( .WE(we_c), .IRQ(irq_n), .NMI(nmi_n), - .RDY(ready) + .RDY(ready), + .PC_MONITOR(pc_monitor) ); always @(posedge clk or posedge reset)