diff --git a/boards/ice40hx8k/appleone_sbt.project b/boards/ice40hx8k/appleone_sbt.project
index bae845f..92b5e8f 100644
--- a/boards/ice40hx8k/appleone_sbt.project
+++ b/boards/ice40hx8k/appleone_sbt.project
@@ -4,7 +4,7 @@ Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Bui
 ProjectName=appleone
 Vendor=SiliconBlue
 Synthesis=synplify
-ProjectVFiles=../../rtl/rom_wozmon.v=work,../../rtl/apple1.v=work,../../rtl/ram.v=work,../../rtl/boards/ice40hx8k/clock_pll.v=work,../../rtl/uart/async_tx_rx.v=work,../../rtl/uart/uart.v=work,../../rtl/boards/ice40hx8k/apple1_hx8k.v=work,../../rtl/cpu/arlet_6502.v=work,../../rtl/cpu/arlet/ALU.v=work,../../rtl/cpu/arlet/cpu.v=work
+ProjectVFiles=../../rtl/rom_wozmon.v=work,../../rtl/apple1.v=work,../../rtl/ram.v=work,../../rtl/boards/ice40hx8k/clock_pll.v=work,../../rtl/uart/async_tx_rx.v=work,../../rtl/uart/uart.v=work,../../rtl/boards/ice40hx8k/apple1_hx8k.v=work,../../rtl/cpu/arlet_6502.v=work,../../rtl/cpu/arlet/ALU.v=work,../../rtl/cpu/arlet/cpu.v=work,../../rtl/rom_basic.v
 ProjectCFiles=appleone_syn.sdc
 CurImplementation=appleone_Implmnt
 Implementations=appleone_Implmnt
@@ -19,9 +19,9 @@ DevicePower=
 NetlistFile=appleone_Implmnt/appleone.edf
 AdditionalEDIFFile=
 IPEDIFFile=
-DesignLib=
-DesignView=
-DesignCell=
+DesignLib=appleone_Implmnt/sbt/netlist/oadb-apple1_top
+DesignView=_rt
+DesignCell=apple1_top
 SynthesisSDCFile=appleone_Implmnt/appleone.scf
 UserPinConstraintFile=
 UserSDCFile=
diff --git a/boards/ice40hx8k/appleone_syn.prj b/boards/ice40hx8k/appleone_syn.prj
index c6c901d..1ec75b6 100644
--- a/boards/ice40hx8k/appleone_syn.prj
+++ b/boards/ice40hx8k/appleone_syn.prj
@@ -18,6 +18,7 @@ add_file -verilog -lib work "../../rtl/boards/ice40hx8k/apple1_hx8k.v"
 add_file -verilog -lib work "../../rtl/cpu/arlet_6502.v" 
 add_file -verilog -lib work "../../rtl/cpu/arlet/ALU.v" 
 add_file -verilog -lib work "../../rtl/cpu/arlet/cpu.v" 
+add_file -verilog -lib work "../../rtl/rom_basic.v" 
 add_file -constraint -lib work "appleone_syn.sdc"
 #implementation: "appleone_Implmnt"
 impl -add appleone_Implmnt -type fpga
diff --git a/boards/ice40hx8k/ice40hx8k.pcf b/boards/ice40hx8k/ice40hx8k.pcf
index eee573e..8a95350 100644
--- a/boards/ice40hx8k/ice40hx8k.pcf
+++ b/boards/ice40hx8k/ice40hx8k.pcf
@@ -9,12 +9,7 @@ set_io uart_tx B12
 set_io uart_cts A15
 #set_io uart_rts B13
 
-### TM1638 Display
-#set_io tm_clk P1
-#set_io tm_dio P2
-#set_io tm_cs R1
-
-### LEDs
+### Breakout Board LEDs
 set_io led[7] B5
 set_io led[6] B4
 set_io led[5] A2
@@ -24,25 +19,23 @@ set_io led[2] C4
 set_io led[1] B3
 set_io led[0] C3
 
-set_io ledx[7] J1
-set_io ledx[6] J2
-set_io ledx[5] K1
-set_io ledx[4] K3
-set_io ledx[3] L1
-set_io ledx[2] L3
-set_io ledx[1] M1
-set_io ledx[0] M2
+### YL-4 Switch Matrix LEDs (inverted)
+set_io led[15] J1
+set_io led[14] J2
+set_io led[13] K1
+set_io led[12] K3
+set_io led[11] L1
+set_io led[10] L3
+set_io led[9] M1
+set_io led[8] M2
 
-#set_io d[0] B1
-#set_io d[1] B2
-#set_io d[2] C1
-#set_io d[3] C2
-#set_io d[4] D1
-#set_io d[5] D2
-#set_io d[6] E2
-#set_io d[7] F1
-#set_io d[8] F2
-#set_io d[9] G1
-#set_io d[10] G2
-#set_io d[11] H1
-#set_io d[12] H2
+### YL-4 Switch Marix Buttons
+set_io button[3] E2
+set_io button[2] F1
+set_io button[1] F2
+set_io button[0] G1
+
+### TM1638 Display
+#set_io tm_clk P1
+#set_io tm_dio P2
+#set_io tm_cs R1
diff --git a/iverilog/apple1_files.txt b/iverilog/apple1_files.txt
index 0a57e43..8a5a227 100644
--- a/iverilog/apple1_files.txt
+++ b/iverilog/apple1_files.txt
@@ -5,5 +5,6 @@
 ../rtl/uart/uart.v
 ../rtl/ram.v
 ../rtl/rom_wozmon.v
+../rtl/rom_basic.v
 ../rtl/apple1.v
 apple1_tb.v
diff --git a/iverilog/apple1_tb.v b/iverilog/apple1_tb.v
index f51f0ec..d1d14e6 100644
--- a/iverilog/apple1_tb.v
+++ b/iverilog/apple1_tb.v
@@ -216,7 +216,8 @@ module apple1_tb;
     // Core of system
     apple1 #(
         "../roms/ram.hex",
-        "../roms/wozmon.hex"
+        "../roms/wozmon.hex",
+        "../roms/basic.hex"
     ) core_top (
         .clk25(clk25),
         .rst_n(rst_n),
diff --git a/rtl/apple1.v b/rtl/apple1.v
index 13ff6d0..256f024 100644
--- a/rtl/apple1.v
+++ b/rtl/apple1.v
@@ -5,11 +5,12 @@ module apple1(
     input  uart_rx,
     output uart_tx,
     output uart_cts,
-    
+
     output [15:0] pc_monitor    // spy for program counter / debugging
 );
     parameter RAM_FILENAME = "../../roms/ram.hex";
     parameter WOZ_FILENAME = "../../roms/wozmon.hex";
+    parameter BASIC_FILENAME = "../../roms/basic.hex";
 
     //////////////////////////////////////////////////////////////////////////
     // Registers and Wires
@@ -18,11 +19,11 @@ module apple1(
     wire [7:0] dbi;
     wire [7:0] dbo;
     wire we;
-    
+
     //////////////////////////////////////////////////////////////////////////
     // Clocks
-    
-    // generate clock enable once every 
+
+    // generate clock enable once every
     // 25 clocks. This will (hopefully) make
     // the 6502 run at 1 MHz or 1Hz
     //
@@ -45,7 +46,7 @@ module apple1(
                 clk_div <= clk_div + 1'b1;
 
             cpu_clken <= (clk_div[25:0] == 0);
-        end    
+        end
     `else
         reg [4:0] clk_div;
         reg cpu_clken;
@@ -115,7 +116,6 @@ module apple1(
     wire [7:0] ram_dout;
     ram #(RAM_FILENAME) my_ram (
         .clk(clk25),
-        .reset(reset),
         .address(ab[12:0]),
         .w_en(we & ram_cs),
         .din(dbo),
@@ -126,19 +126,26 @@ module apple1(
     wire [7:0] rom_dout;
     rom_wozmon #(WOZ_FILENAME) my_rom_wozmon (
         .clk(clk25),
-        .reset(reset),
         .address(ab[7:0]),
         .dout(rom_dout)
     );
 
+    // Basic ROM
+    wire [7:0] basic_dout;
+    rom_basic #(BASIC_FILENAME) my_rom_basic (
+        .clk(clk25),
+        .address(ab[7:0]),
+        .dout(basic_dout)
+    );
+
     // UART
     wire [7:0] uart_dout;
     uart #(
+        `ifdef SIM
+        100, 10, 2 // for simulation don't need real baud rates
+        `else
         25000000, 115200, 8
-// FIXME:
-// If simulated, need to reduce baud rate etc down
-// else the UARTs don't work.
-//        100, 10, 2
+        `endif
     )my_uart (
         .clk(clk25),
         .reset(reset),
@@ -155,8 +162,9 @@ module apple1(
     );
 
     // link up chip selected device to cpu input
-    assign dbi = ram_cs  ? ram_dout : 
-                 rom_cs  ? rom_dout :
-                 uart_cs ? uart_dout :
+    assign dbi = ram_cs   ? ram_dout :
+                 rom_cs   ? rom_dout :
+                 basic_cs ? basic_dout :
+                 uart_cs  ? uart_dout :
                  8'hFF;
 endmodule
diff --git a/rtl/boards/ice40hx8k/apple1_hx8k.v b/rtl/boards/ice40hx8k/apple1_hx8k.v
index 075fdab..4f5b4b6 100644
--- a/rtl/boards/ice40hx8k/apple1_hx8k.v
+++ b/rtl/boards/ice40hx8k/apple1_hx8k.v
@@ -3,7 +3,9 @@ module apple1_top(
 
     input  uart_rx,
     output uart_tx,
-    output uart_cts
+    output uart_cts,
+    output [15:0] led,
+    output [1:0] button
 );
 
     wire clk25;
@@ -16,13 +18,18 @@ module apple1_top(
             .RESET(1'b1)
             );
 
+    wire [15:0] pc_monitor;
+    assign led[7:0] = pc_monitor[7:0];
+    assign led[15:8] = ~pc_monitor[15:8];
+
     // apple one main system
     apple1 my_apple1(
         .clk25(clk25),
         .rst_n(1'b1),
         .uart_rx(uart_rx),
         .uart_tx(uart_tx),
-        .uart_cts(uart_cts)
+        .uart_cts(uart_cts),
+        .pc_monitor(pc_monitor)
     );
     
 endmodule
diff --git a/rtl/ram.v b/rtl/ram.v
index f04886f..f5f9a0d 100644
--- a/rtl/ram.v
+++ b/rtl/ram.v
@@ -1,6 +1,5 @@
 module ram(
     input clk,
-    input reset,
     input [12:0] address,
     input w_en,
     input [7:0] din,
@@ -16,8 +15,8 @@ module ram(
 
     always @(posedge clk)
     begin
-        dout <= reset ? 8'h0 : ram[address];
-        if (w_en && ~reset) ram[address] <= din;
+        dout <= ram[address];
+        if (w_en) ram[address] <= din;
     end
 
 endmodule
diff --git a/rtl/rom_basic.v b/rtl/rom_basic.v
new file mode 100644
index 0000000..cc52cc7
--- /dev/null
+++ b/rtl/rom_basic.v
@@ -0,0 +1,17 @@
+module rom_basic(
+    input clk,
+    input [7:0] address,
+    output reg [7:0] dout
+    );
+
+    parameter ROM_FILENAME = "../roms/basic.hex";
+
+    reg [7:0] rom[0:4095];
+
+    initial
+        $readmemh(ROM_FILENAME, rom, 0, 4095);
+
+    always @(posedge clk)
+        dout <= rom[address];
+
+endmodule
diff --git a/rtl/rom_wozmon.v b/rtl/rom_wozmon.v
index c6a0464..46efb84 100644
--- a/rtl/rom_wozmon.v
+++ b/rtl/rom_wozmon.v
@@ -1,6 +1,5 @@
 module rom_wozmon(
     input clk,
-    input reset,
     input [7:0] address,
     output reg [7:0] dout
     );
@@ -13,9 +12,7 @@ module rom_wozmon(
         $readmemh(ROM_FILENAME, rom, 0, 255);
 
     always @(posedge clk)
-    begin
-        dout <= reset ? 8'h0 : rom[address];
-    end
+        dout <= rom[address];
 
 endmodule
     
diff --git a/rtl/uart/uart.v b/rtl/uart/uart.v
index f04d03c..247bdc9 100644
--- a/rtl/uart/uart.v
+++ b/rtl/uart/uart.v
@@ -108,13 +108,18 @@ module uart(
                 begin
                     // Apple 1 terminal only uses 7 bits, MSB indicates
                     // terminal has ack'd RX
+                    //
+                    // uart_tx_init is a flag to stop the first character
+                    // sent to the UART from being sent. Wozmon initializes
+                    // the PIA which normally isn't sent to the terminal.
+                    // This causes the UART to ignore the very first byte sent.
                     if (~uart_tx_status && uart_tx_init)
                     begin
                         uart_tx_byte <= {1'b0, din[6:0]};
                         uart_tx_stb <= 1;
                     end
-                    else
-                        uart_tx_init <= 1;
+                    else if (~uart_tx_init)
+                        uart_tx_init <= 1 && enable;
                 end
             end