mirror of
https://github.com/alangarf/apple-one.git
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Added Spartan 3E starter kit implementation (work in progress!).
This commit is contained in:
Niels Moseley
parent
20ffe41999
commit
77b5847611
13
boards/spartan3e_starterkit/README.md
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13
boards/spartan3e_starterkit/README.md
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# Apple One<br>Digilent Spartan 3E Starter Kit Board target
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Maintainer: Niels Moseley https://github.com/trcwm
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### Build environment
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The project was developed using Xilinx ISE 14.7. Using other versions might work, YMMV.
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### Features
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* UART support via the on-board RS-232 interface.
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* VGA support via the on-board VGA connector.
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* PS/2 keyboard support via the on-board PS/2 connector.
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BIN
boards/spartan3e_starterkit/images/spartan3e_starterkit.jpg
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BIN
boards/spartan3e_starterkit/images/spartan3e_starterkit.jpg
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Binary file not shown.
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After Width: | Height: | Size: 52 KiB |
30
boards/spartan3e_starterkit/webpack_ise/Apple-One.gise
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30
boards/spartan3e_starterkit/webpack_ise/Apple-One.gise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="Apple-One.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:fileType="FILE_NCD" xil_pn:name="apple1_s3e_starterkit_top_guide.ncd" xil_pn:origination="imported"/>
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
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</generated_project>
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131
boards/spartan3e_starterkit/webpack_ise/Apple-One.xise
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131
boards/spartan3e_starterkit/webpack_ise/Apple-One.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="../../../rtl/boards/spartan3e_starterkit/apple1_s3e_starterkit_top.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
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</file>
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<file xil_pn:name="../../../rtl/cpu/arlet/ALU.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="../../../rtl/cpu/arlet/cpu.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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</file>
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<file xil_pn:name="../../../rtl/cpu/arlet_6502.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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</file>
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<file xil_pn:name="../../../rtl/ps2keyboard/debounce.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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</file>
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<file xil_pn:name="../../../rtl/ps2keyboard/ps2keyboard.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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</file>
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<file xil_pn:name="../../../rtl/uart/async_tx_rx.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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</file>
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<file xil_pn:name="../../../rtl/uart/uart.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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</file>
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<file xil_pn:name="../../../rtl/vga/font_rom.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</file>
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<file xil_pn:name="../../../rtl/vga/vga.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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</file>
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<file xil_pn:name="../../../rtl/vga/vram.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="../../../rtl/apple1.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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</file>
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<file xil_pn:name="../../../rtl/clock.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
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</file>
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<file xil_pn:name="../../../rtl/pwr_reset.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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</file>
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<file xil_pn:name="../../../rtl/ram.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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</file>
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<file xil_pn:name="../../../rtl/rom_basic.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
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</file>
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<file xil_pn:name="../../../rtl/rom_wozmon.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
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</file>
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<file xil_pn:name="apple1_s3e_starterkit_top.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3E Starter Board" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Module|apple1_s3e_starterkit_top" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="../../../rtl/boards/spartan3e_starterkit/apple1_s3e_starterkit_top.v" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/apple1_s3e_starterkit_top" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Target UCF File Name" xil_pn:value="apple1_s3e_starterkit_top.ucf" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="Apple-One" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-02-11T23:27:18" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="44155E32156B424F8EA41D66911C47DB" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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<bindings/>
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<libraries/>
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<autoManagedFiles>
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<!-- The following files are identified by `include statements in verilog -->
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<!-- source files and are automatically managed by Project Navigator. -->
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<!-- -->
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<!-- Do not hand-edit this section, as it will be overwritten when the -->
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<!-- project is analyzed based on files automatically identified as -->
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<!-- include files. -->
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</autoManagedFiles>
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</project>
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#Pin definitions
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# clocks
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NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
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# ps/2 keyboard
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NET "PS2_KBDAT" LOC = G13 | IOSTANDARD = LVCMOS33;
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NET "PS2_KBCLK" LOC = G14 | IOSTANDARD = LVCMOS33;
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# VGA pins
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NET "VGA_R" LOC = H14 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_G" LOC = H15 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_B" LOC = G15 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_HS" LOC = F15 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_VS" LOC = F14 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
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# RS-232 pins
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#NET "UART_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
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#NET "UART_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
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NET "UART_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
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NET "UART_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
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# RESET BUTTON / SOUTH on the board
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NET "BUTTON" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
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#Created by Constraints Editor (xc3s500e-fg320-4) - 2018/02/11
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NET "CLK_50MHZ" TNM_NET = CLK_50MHZ;
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NET "clk25" TNM_NET = clk25;
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TIMESPEC TS_CLOCK_50 = PERIOD "CLK_50MHZ" 20 ns HIGH 50%;
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TIMESPEC TS_CLOCK_25 = PERIOD "clk25" 40 ns HIGH 50%;
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12
tools/ise_hexer/README.md
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12
tools/ise_hexer/README.md
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# ISE_HEXER 1.0<br><h2>Convert a $readmemh HEX file so that Xilinx ISE can use them<br>Niels A. Moseley
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Xilinx ISE is a piece of sh*t when it comes to reading HEX file using $readmemh. It will only read files that are _exactly_ the right length for the ROM/RAM to be instantiated.
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Furthermore, it only allows _one_ data entry per line and _no_ comments.
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This program makes sure there is only one data entry per line.
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Comments will still be copied and cause erros.
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It was programmed for the TinyCC portable compiler: http://download.savannah.gnu.org/releases/tinycc/
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Install TCC in the subdir tcc.
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81
tools/ise_hexer/main.c
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81
tools/ise_hexer/main.c
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/* Converts vga_font.bin into vga_font.hex
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Author: Niels A. Moseley
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*/
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#include<stdio.h>
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#include<stdint.h>
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const char hextbl[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'};
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uint8_t isWhiteSpace(char c)
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{
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if ((c==' ') || (c=='\t'))
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{
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return 1;
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}
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return 0;
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}
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uint8_t convert(const char *infilename, const char *outfilename)
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{
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FILE *fin = fopen(infilename,"rt");
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if (fin == NULL)
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{
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printf("Error: cannot open %s!\n", infilename);
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return 1;
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}
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FILE *fout = fopen(outfilename,"wt");
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if (fout == NULL)
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{
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printf("Error: cannot open %s for writing!\n", outfilename);
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fclose(fin);
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return 1;
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}
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uint8_t inWhiteSpace = 1;
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while(!feof(fin))
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{
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char c = fgetc(fin);
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if (inWhiteSpace == 0)
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{
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if (isWhiteSpace(c))
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{
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inWhiteSpace = 1;
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fprintf(fout, "\n");
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}
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else
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{
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fprintf(fout,"%c", c);
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}
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}
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else
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{
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if (!isWhiteSpace(c))
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{
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fprintf(fout,"%c", c);
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inWhiteSpace = 0;
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}
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else
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{
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// still in white space .. do nothing
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}
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}
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}
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fclose(fin);
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fclose(fout);
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}
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int main(int argc, char *argv[])
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{
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printf("ISE_HEXER v1.0\n");
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convert("..\\..\\roms\\basic.hex", "..\\..\\roms\\basic_ise.hex");
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convert("..\\..\\roms\\ram.hex", "..\\..\\roms\\ram_ise.hex");
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convert("..\\..\\roms\\wozmon.hex", "..\\..\\roms\\wozmon_ise.hex");
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printf("Done\n");
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return 0;
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}
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1
tools/ise_hexer/run.bat
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1
tools/ise_hexer/run.bat
Normal file
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tcc\tcc -run main.c
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