* Added missing S3E top level verilog file.
* Updated wozmon.hex to be ISE compliant.
This commit is contained in:
parent
2bcb58e039
commit
7a260619a5
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@ -103,7 +103,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1518446552" xil_pn:in_ck="-2402892782883100176" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8720043281624233679" xil_pn:start_ts="1518446533">
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<transform xil_pn:end_ts="1518447977" xil_pn:in_ck="-2402892782883100176" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8720043281624233679" xil_pn:start_ts="1518447958">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -125,7 +125,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1518446557" xil_pn:in_ck="-3894786652928293112" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-581701490373080307" xil_pn:start_ts="1518446552">
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<transform xil_pn:end_ts="1518447982" xil_pn:in_ck="-3894786652928293112" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-581701490373080307" xil_pn:start_ts="1518447977">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_ngo"/>
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@ -134,11 +134,9 @@
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<outfile xil_pn:name="apple1_s3e_starterkit_top.ngd"/>
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<outfile xil_pn:name="apple1_s3e_starterkit_top_ngdbuild.xrpt"/>
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</transform>
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<transform xil_pn:end_ts="1518446561" xil_pn:in_ck="8375880660293788329" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1518446557">
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<transform xil_pn:end_ts="1518447986" xil_pn:in_ck="8375880660293788329" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1518447982">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
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<outfile xil_pn:name="apple1_s3e_starterkit_top.pcf"/>
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<outfile xil_pn:name="apple1_s3e_starterkit_top_map.map"/>
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@ -149,7 +147,7 @@
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<outfile xil_pn:name="apple1_s3e_starterkit_top_summary.xml"/>
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<outfile xil_pn:name="apple1_s3e_starterkit_top_usage.xml"/>
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</transform>
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<transform xil_pn:end_ts="1518446578" xil_pn:in_ck="-3296291810439397278" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1518446561">
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<transform xil_pn:end_ts="1518448003" xil_pn:in_ck="-3296291810439397278" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1518447986">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
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@ -163,7 +161,7 @@
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<outfile xil_pn:name="apple1_s3e_starterkit_top_pad.txt"/>
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<outfile xil_pn:name="apple1_s3e_starterkit_top_par.xrpt"/>
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</transform>
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<transform xil_pn:end_ts="1518446588" xil_pn:in_ck="-5976217886481471090" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1518446578">
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<transform xil_pn:end_ts="1518448066" xil_pn:in_ck="-5976217886481471090" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1518448055">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
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@ -178,8 +176,10 @@
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<transform xil_pn:end_ts="1518446623" xil_pn:in_ck="-5976217886481483944" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1518446622">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="InputChanged"/>
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</transform>
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<transform xil_pn:end_ts="1518446578" xil_pn:in_ck="-6485470272289971291" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518446575">
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<transform xil_pn:end_ts="1518448003" xil_pn:in_ck="-6485470272289971291" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518447999">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
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288
roms/wozmon.hex
288
roms/wozmon.hex
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@ -1,32 +1,256 @@
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D8 58 A0 7F 8C 12 D0 A9
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A7 8D 11 D0 8D 13 D0 C9
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DF F0 13 C9 9B F0 03 C8
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10 0F A9 DC 20 EF FF A9
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F0 C9 BA F0 EB C9 D2 F0
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3B 86 28 86 29 84 2A B9
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69 88 C9 FA 90 11 0A 0A
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00
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@ -0,0 +1,90 @@
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level Apple 1 module for Digilent Spartan 3E
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// starter kit board
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//
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// Author.....: Niels A. Moseley
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// Date.......: 11-2-2018
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//
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module apple1_s3e_starterkit_top #(
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parameter BASIC_FILENAME = "../../../roms/basic_ise.hex",
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parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
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parameter RAM_FILENAME = "../../../roms/ram_ise.hex",
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parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
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parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon_ise.hex"
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) (
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input CLK_50MHZ, // the 50 MHz master clock
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// UART I/O signals
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output UART_TXD, // UART transmit pin on board
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input UART_RXD, // UART receive pin on board
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input PS2_KBCLK,
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input PS2_KBDAT,
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input BUTTON,
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output VGA_R,
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output VGA_G,
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output VGA_B,
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output VGA_HS,
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output VGA_VS
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);
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//////////////////////////////////////////////////////////////////////////
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// Registers and Wires
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reg clk25;
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wire [15:0] pc_monitor;
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wire rst_n;
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assign rst_n = ~BUTTON;
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// generate 25MHz clock from 50MHz master clock
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always @(posedge CLK_50MHZ)
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begin
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clk25 <= ~clk25;
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end
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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apple1 #(
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.BASIC_FILENAME (BASIC_FILENAME),
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.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
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.RAM_FILENAME (RAM_FILENAME),
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.VRAM_FILENAME (VRAM_FILENAME),
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.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
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) apple1_top(
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.clk25(clk25),
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.rst_n(rst_n), // we don't have any reset pulse..
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.uart_rx(UART_RXD),
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.uart_tx(UART_TXD),
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//.uart_cts(UART_CTS), // there is no CTS on the board :(
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.ps2_clk(PS2_KBCLK),
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.ps2_din(PS2_KBDAT),
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.ps2_select(1'b1),
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.vga_h_sync(VGA_HS),
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.vga_v_sync(VGA_VS),
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.vga_red(VGA_R),
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.vga_grn(VGA_G),
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.vga_blu(VGA_B),
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.pc_monitor(pc_monitor)
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);
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endmodule
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Reference in New Issue