moved sources into rtl to clean up root

apple1_sbt.project

@@ -4,7 +4,7 @@ Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Bui
 ProjectName=apple1
 Vendor=SiliconBlue
 Synthesis=synplify
-ProjectVFiles=basic.v=work,uart.v=work,tm1638.v=work,led_and_key.v=work,chip_6502.v=work,MUX.v=work
+ProjectVFiles=rtl/MUX.v,rtl/basic.v,rtl/chip_6502.v,rtl/led_and_key.v,rtl/tm1638.v,rtl/uart.v
 ProjectCFiles=
 CurImplementation=apple1_Implmnt
 Implementations=apple1_Implmnt
@@ -19,9 +19,9 @@ DevicePower=
 NetlistFile=apple1_Implmnt/apple1.edf
 AdditionalEDIFFile=
 IPEDIFFile=
-DesignLib=apple1_Implmnt/sbt/netlist/oadb-top
-DesignView=_rt
-DesignCell=top
+DesignLib=
+DesignView=
+DesignCell=
 SynthesisSDCFile=apple1_Implmnt/apple1.scf
 UserPinConstraintFile=
 UserSDCFile=

apple1_syn.prj

@@ -8,12 +8,12 @@
 
 
 
-add_file -verilog -lib work "basic.v" 
-add_file -verilog -lib work "uart.v" 
-add_file -verilog -lib work "tm1638.v" 
-add_file -verilog -lib work "led_and_key.v" 
-add_file -verilog -lib work "chip_6502.v" 
-add_file -verilog -lib work "MUX.v" 
+add_file -verilog -lib work "rtl/MUX.v" 
+add_file -verilog -lib work "rtl/basic.v" 
+add_file -verilog -lib work "rtl/chip_6502.v" 
+add_file -verilog -lib work "rtl/led_and_key.v" 
+add_file -verilog -lib work "rtl/tm1638.v" 
+add_file -verilog -lib work "rtl/uart.v" 
 #implementation: "apple1_Implmnt"
 impl -add apple1_Implmnt -type fpga
 

rom.hex

@@ -1,256 +0,0 @@
-D8
-58
-A0
-7F
-8C
-12
-D0
-A9
-A7
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-FB
-8D
-12
-D0
-60
-00
-00
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-0F
-00
-FF
-00
-00

roms/rom.hex

@@ -0,0 +1,32 @@
+D8 58 A0 7F 8C 12 D0 A9
+A7 8D 11 D0 8D 13 D0 C9
+DF F0 13 C9 9B F0 03 C8
+10 0F A9 DC 20 EF FF A9
+8D 20 EF FF A0 01 88 30
+F6 AD 11 D0 10 FB AD 10
+D0 99 00 02 20 EF FF C9
+8D D0 D4 A0 FF A9 00 AA
+0A 85 2B C8 B9 00 02 C9
+8D F0 D4 C9 AE 90 F4 F0
+F0 C9 BA F0 EB C9 D2 F0
+3B 86 28 86 29 84 2A B9
+00 02 49 B0 C9 0A 90 06
+69 88 C9 FA 90 11 0A 0A
+0A 0A A2 04 0A 26 28 26
+29 CA D0 F8 C8 D0 E0 C4
+2A F0 97 24 2B 50 10 A5
+28 81 26 E6 26 D0 B5 E6
+27 4C 44 FF 6C 24 00 30
+2B A2 02 B5 27 95 25 95
+23 CA D0 F7 D0 14 A9 8D
+20 EF FF A5 25 20 DC FF
+A5 24 20 DC FF A9 BA 20
+EF FF A9 A0 20 EF FF A1
+24 20 DC FF 86 2B A5 24
+C5 28 A5 25 E5 29 B0 C1
+E6 24 D0 02 E6 25 A5 24
+29 07 10 C8 48 4A 4A 4A
+4A 20 E5 FF 68 29 0F 09
+B0 C9 BA 90 02 69 06 2C
+12 D0 30 FB 8D 12 D0 60
+00 00 00 0F 00 FF 00 00

rtl/basic.v

@@ -150,9 +150,9 @@ module top(
     reg [7:0] basic[0:4095] /* synthesis syn_ramstyle = "block_ram" */;
     
     initial begin
-        $readmemh("../ram.hex", ram, 0, 8191);
-        $readmemh("../rom.hex", rom, 0, 255);
-        $readmemh("../basic.hex", basic, 0, 4095);
+        $readmemh("../roms/ram.hex", ram, 0, 8191);
+        $readmemh("../roms/rom.hex", rom, 0, 255);
+        $readmemh("../roms/basic.hex", basic, 0, 4095);
     end
 
     always @(posedge clk_phi)