From 93713037892290564ff698733a47c7ef2f8a4b31 Mon Sep 17 00:00:00 2001
From: Alan Garfield <alan@fromorbit.com>
Date: Thu, 8 Feb 2018 01:06:35 +1100
Subject: [PATCH] Fixed minor verilator complaint

---
 rtl/apple1.v  | 12 ++++++------
 rtl/vga/vga.v | 10 +++++-----
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/rtl/apple1.v b/rtl/apple1.v
index dc659b5..5b40c6a 100644
--- a/rtl/apple1.v
+++ b/rtl/apple1.v
@@ -88,8 +88,8 @@ module apple1(
         .we     (we),
         .irq_n  (1'b1),
         .nmi_n  (1'b1),
-        .ready  (cpu_clken)
-        //.pc_monitor (pc_monitor)
+        .ready  (cpu_clken),
+        .pc_monitor (pc_monitor)
     );
 
     //////////////////////////////////////////////////////////////////////////
@@ -112,8 +112,6 @@ module apple1(
     wire basic_cs = (ab[15:12] ==  4'b1110);            // 0xE000 -> 0xEFFF
     wire rom_cs =   (ab[15:8]  ==  8'b11111111);        // 0xFF00 -> 0xFFFF
 
-    wire mode_cs = (ab[15:12]  == 4'b1100); // 0xC000
-
     //////////////////////////////////////////////////////////////////////////
     // RAM and ROM
 
@@ -199,10 +197,12 @@ module apple1(
         .address(ab[0]),
         .w_en(we & vga_cs),
         .din(dbo),
-        .mode(vga_mode),
-        .debug(pc_monitor)
+        .mode(vga_mode)
     );
 
+    // FIXME: REMOVE THIS
+    wire mode_cs = (ab[15:12]  == 4'b1100); // 0xC000
+
     always @(posedge clk25 or posedge rst)
     begin
         if (rst)
diff --git a/rtl/vga/vga.v b/rtl/vga/vga.v
index f4ae96a..d5521f6 100644
--- a/rtl/vga/vga.v
+++ b/rtl/vga/vga.v
@@ -10,8 +10,7 @@ module vga(
     input address,          // address bus
     input w_en,             // active high write enable strobe
     input [7:0] din,        // 8-bit data bus (input)
-    input [1:0] mode,       // 2-bit mode setting for pixel doubling
-    output [15:0] debug
+    input [1:0] mode        // 2-bit mode setting for pixel doubling
     );
 
     //////////////////////////////////////////////////////////////////////////
@@ -43,6 +42,7 @@ module vga(
     reg [4:0] vram_v_addr;
     reg [4:0] vram_start_addr;
     reg [4:0] vram_end_addr;
+    reg [4:0] vram_clr_addr;
 
     // vram registers
     wire [10:0] vram_r_addr;
@@ -200,11 +200,11 @@ module vga(
     assign vga_h_sync = (h_cnt < h_pulse) ? 0 : 1;
     assign vga_v_sync = (v_cnt < v_pulse) ? 0 : 1;
 
-    assign debug = {v_cursor, 6'd0, vram_start_addr};
-
     //////////////////////////////////////////////////////////////////////////
     // CPU control and hardware cursor
 
+    assign vram_clr_addr = vram_end_addr + {3'd0, vram_v_addr[1:0]};
+
     always @(posedge clk25 or posedge rst)
     begin
         if (rst)
@@ -264,7 +264,7 @@ module vga(
             end
             else
             begin
-                vram_w_addr <= {(vram_end_addr + 2), vram_h_addr};
+                vram_w_addr <= {vram_clr_addr, vram_h_addr};
                 vram_din <= 6'd32;
                 vram_w_en <= 1;
             end