Apple-1-HW/verilog-apple-one
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more project file fiddles by the tool. :/

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Alan Garfield
2018-01-28 00:23:43 +11:00
parent 0fc84e0b37
commit e9ff2b294e
1 changed files with 1 additions and 1 deletions
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boards/ice40hx8k/appleone_sbt.project
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@@ -20,7 +20,7 @@ NetlistFile=appleone_Implmnt/appleone.edf
AdditionalEDIFFile=
IPEDIFFile=
DesignLib=appleone_Implmnt/sbt/netlist/oadb-apple1_top
DesignView=_ep
DesignView=_rt
DesignCell=apple1_top
SynthesisSDCFile=appleone_Implmnt/appleone.scf
UserPinConstraintFile=